rggen-systemverilog 0.14.0 → 0.15.0
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- checksums.yaml +4 -4
- data/lib/rggen/systemverilog/ral/setup.rb +1 -1
- data/lib/rggen/systemverilog/rtl.rb +2 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb +10 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb +21 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb +10 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb +21 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +1 -1
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +7 -3
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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1
1
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---
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2
2
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SHA256:
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3
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-
metadata.gz:
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4
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-
data.tar.gz:
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3
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+
metadata.gz: cc0fa0eebf47d5df307cb4c9ed64ab2946267979155d84d2ff9f946f5fe73276
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4
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+
data.tar.gz: 329fa0ec20a90177423cabe340b82e1b351f4464cffddd3bd67079eb023f4ca0
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5
5
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SHA512:
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6
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-
metadata.gz:
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7
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-
data.tar.gz:
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6
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+
metadata.gz: 3d549ee0707e59423177fb364ebd95d65008930c712816720322fbf9ed11fc87fa59aed077c422b9aac85853c93d631d46c2c98be12bdd7788a974e0a14d099e
|
7
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+
data.tar.gz: 32ad0b9fb29df9625232ada4c7952a26ff384db80faccfdb1b3bedd9ae22effa60c34dc3cb252b87f3b9f6384c3eafec6a66fccacd761ebc996ba4fd856aef93
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@@ -19,6 +19,8 @@ module RgGen
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19
19
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'rtl/bit_field/type/rwe',
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20
20
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'rtl/bit_field/type/rwl',
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21
21
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'rtl/bit_field/type/rws',
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22
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+
'rtl/bit_field/type/w0crs_w1crs',
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23
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+
'rtl/bit_field/type/w0src_w1src',
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22
24
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'rtl/bit_field/type/w0trg_w1trg',
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23
25
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'rtl/global/array_port_format',
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24
26
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'rtl/global/fold_sv_interface_port',
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@@ -0,0 +1,10 @@
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1
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+
rggen_bit_field_w01crs #(
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2
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+
.CLEAR_VALUE (<%= clear_value %>),
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3
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+
.WIDTH (<%= width %>),
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4
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+
.INITIAL_VALUE (<%= initial_value %>)
|
5
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+
) u_bit_field (
|
6
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+
.i_clk (<%= clock %>),
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7
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+
.i_rst_n (<%= reset %>),
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8
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+
.bit_field_if (<%= bit_field_if %>),
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9
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+
.o_value (<%= value_out[loop_variables] %>)
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10
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+
);
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@@ -0,0 +1,21 @@
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1
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+
# frozen_string_literal: true
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2
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+
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3
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+
RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
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4
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+
sv_rtl do
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5
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+
build do
|
6
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+
output :register_block, :value_out, {
|
7
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+
name: "o_#{full_name}", data_type: :logic, width: width,
|
8
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+
array_size: array_size, array_format: array_port_format
|
9
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+
}
|
10
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+
end
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11
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+
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12
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+
main_code :bit_field, from_template: true
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13
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+
|
14
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+
private
|
15
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+
|
16
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+
def clear_value
|
17
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+
value = (bit_field.type == :w0crs && 0) || 1
|
18
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+
bin(value, 1)
|
19
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+
end
|
20
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+
end
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21
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+
end
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@@ -0,0 +1,10 @@
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1
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+
rggen_bit_field_w01src #(
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2
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+
.SET_VALUE (<%= set_value %>),
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3
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+
.WIDTH (<%= width %>),
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4
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+
.INITIAL_VALUE (<%= initial_value %>)
|
5
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+
) u_bit_field (
|
6
|
+
.i_clk (<%= clock %>),
|
7
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+
.i_rst_n (<%= reset %>),
|
8
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+
.bit_field_if (<%= bit_field_if %>),
|
9
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+
.o_value (<%= value_out[loop_variables] %>)
|
10
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+
);
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@@ -0,0 +1,21 @@
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|
1
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+
# frozen_string_literal: true
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2
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+
|
3
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+
RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
|
4
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+
sv_rtl do
|
5
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+
build do
|
6
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+
output :register_block, :value_out, {
|
7
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+
name: "o_#{full_name}", data_type: :logic, width: width,
|
8
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+
array_size: array_size, array_format: array_port_format
|
9
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+
}
|
10
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+
end
|
11
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+
|
12
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+
main_code :bit_field, from_template: true
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13
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+
|
14
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+
private
|
15
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+
|
16
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+
def set_value
|
17
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+
value = (bit_field.type == :w0src && 0) || 1
|
18
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+
bin(value, 1)
|
19
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+
end
|
20
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+
end
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21
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+
end
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metadata
CHANGED
@@ -1,14 +1,14 @@
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1
1
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--- !ruby/object:Gem::Specification
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2
2
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name: rggen-systemverilog
|
3
3
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version: !ruby/object:Gem::Version
|
4
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-
version: 0.
|
4
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+
version: 0.15.0
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5
5
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platform: ruby
|
6
6
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authors:
|
7
7
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- Taichi Ishitani
|
8
8
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autorequire:
|
9
9
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bindir: bin
|
10
10
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cert_chain: []
|
11
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-
date: 2019-09-
|
11
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+
date: 2019-09-18 00:00:00.000000000 Z
|
12
12
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dependencies:
|
13
13
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- !ruby/object:Gem::Dependency
|
14
14
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name: docile
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@@ -119,6 +119,10 @@ files:
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119
119
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- lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb
|
120
120
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- lib/rggen/systemverilog/rtl/bit_field/type/rws.erb
|
121
121
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- lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
|
122
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+
- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb
|
123
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+
- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb
|
124
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+
- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb
|
125
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+
- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb
|
122
126
|
- lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
|
123
127
|
- lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
|
124
128
|
- lib/rggen/systemverilog/rtl/feature.rb
|
@@ -166,5 +170,5 @@ requirements: []
|
|
166
170
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rubygems_version: 3.0.3
|
167
171
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signing_key:
|
168
172
|
specification_version: 4
|
169
|
-
summary: rggen-systemverilog-0.
|
173
|
+
summary: rggen-systemverilog-0.15.0
|
170
174
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test_files: []
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