rggen-systemverilog 0.14.0 → 0.15.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 19dd7072e4a6d974adff622812b8687a3f9d4124b28fed40ca2f4e6f4c7c0a60
-  data.tar.gz: e36c2c9907a4da9c7ff5cf38bbdbc76427a3a409be7b430d54064ffd51ae610f
+  metadata.gz: cc0fa0eebf47d5df307cb4c9ed64ab2946267979155d84d2ff9f946f5fe73276
+  data.tar.gz: 329fa0ec20a90177423cabe340b82e1b351f4464cffddd3bd67079eb023f4ca0
 SHA512:
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-  data.tar.gz: 31fc31da516047f204f385e7fbb22316ad7edeb4252eebba47d0c571df77e5ec5078af1b9729248f784297a8f3bea1e5d654ce582b05c03535441f649ad713ec
+  metadata.gz: 3d549ee0707e59423177fb364ebd95d65008930c712816720322fbf9ed11fc87fa59aed077c422b9aac85853c93d631d46c2c98be12bdd7788a974e0a14d099e
+  data.tar.gz: 32ad0b9fb29df9625232ada4c7952a26ff384db80faccfdb1b3bedd9ae22effa60c34dc3cb252b87f3b9f6384c3eafec6a66fccacd761ebc996ba4fd856aef93

data/lib/rggen/systemverilog/ral/setup.rb

@@ -2,6 +2,6 @@
 
 require 'rggen/systemverilog/ral'
 
-RgGen.setup :'sv-ral', RgGen::SystemVerilog::RAL do |builder|
+RgGen.setup :'rggen-sv-ral', RgGen::SystemVerilog::RAL do |builder|
   builder.enable :register_block, [:sv_ral_package]
 end

data/lib/rggen/systemverilog/rtl.rb

@@ -19,6 +19,8 @@ module RgGen
         'rtl/bit_field/type/rwe',
         'rtl/bit_field/type/rwl',
         'rtl/bit_field/type/rws',
+        'rtl/bit_field/type/w0crs_w1crs',
+        'rtl/bit_field/type/w0src_w1src',
         'rtl/bit_field/type/w0trg_w1trg',
         'rtl/global/array_port_format',
         'rtl/global/fold_sv_interface_port',

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb

@@ -0,0 +1,10 @@
+rggen_bit_field_w01crs #(
+  .CLEAR_VALUE    (<%= clear_value %>),
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .o_value      (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb

@@ -0,0 +1,21 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
+  sv_rtl do
+    build do
+      output :register_block, :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def clear_value
+      value = (bit_field.type == :w0crs && 0) || 1
+      bin(value, 1)
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb

@@ -0,0 +1,10 @@
+rggen_bit_field_w01src #(
+  .SET_VALUE      (<%= set_value %>),
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .o_value      (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb

@@ -0,0 +1,21 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
+  sv_rtl do
+    build do
+      output :register_block, :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def set_value
+      value = (bit_field.type == :w0src && 0) || 1
+      bin(value, 1)
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/setup.rb

@@ -2,7 +2,7 @@
 
 require 'rggen/systemverilog/rtl'
 
-RgGen.setup :'sv-rtl', RgGen::SystemVerilog::RTL do |builder|
+RgGen.setup :'rggen-sv-rtl', RgGen::SystemVerilog::RTL do |builder|
   builder.enable :global, [
     :array_port_format, :fold_sv_interface_port
   ]

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.14.0'
+    VERSION = '0.15.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.14.0
+  version: 0.15.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2019-09-03 00:00:00.000000000 Z
+date: 2019-09-18 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: docile
@@ -119,6 +119,10 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
 - lib/rggen/systemverilog/rtl/feature.rb
@@ -166,5 +170,5 @@ requirements: []
 rubygems_version: 3.0.3
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.14.0
+summary: rggen-systemverilog-0.15.0
 test_files: []