rggen-systemverilog 0.9.0

checksums.yaml

@@ -0,0 +1,7 @@
+---
+SHA256:
+  metadata.gz: a6878079652346d464c360c256e886f9225c102dd31bc8ae3ffdcc943ced8c99
+  data.tar.gz: 0f7f5723562004a98e2ebba3c96f51b5ca0387d46e82282f5da38d96acbf8fb2
+SHA512:
+  metadata.gz: 670df6b890abef983d23d1a6c31861193fdeb1c3eb2a00bdc82990a23d01b043e4bd698878dbe7ef1206239414ff45c952fedd64f68ce08aaf110ea19157f759
+  data.tar.gz: 03e2e64799595dedea6725d38ad886aa377edac14839bed6f474ffdc6d886d5ef58bb08c489b117942eea123180ac6dbc24d713593737b16ed018a953c52d144

data/CODE_OF_CONDUCT.md

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+# Contributor Covenant Code of Conduct
+
+## Our Pledge
+
+In the interest of fostering an open and welcoming environment, we as
+contributors and maintainers pledge to making participation in our project and
+our community a harassment-free experience for everyone, regardless of age, body
+size, disability, ethnicity, gender identity and expression, level of experience,
+nationality, personal appearance, race, religion, or sexual identity and
+orientation.
+
+## Our Standards
+
+Examples of behavior that contributes to creating a positive environment
+include:
+
+* Using welcoming and inclusive language
+* Being respectful of differing viewpoints and experiences
+* Gracefully accepting constructive criticism
+* Focusing on what is best for the community
+* Showing empathy towards other community members
+
+Examples of unacceptable behavior by participants include:
+
+* The use of sexualized language or imagery and unwelcome sexual attention or
+advances
+* Trolling, insulting/derogatory comments, and personal or political attacks
+* Public or private harassment
+* Publishing others' private information, such as a physical or electronic
+  address, without explicit permission
+* Other conduct which could reasonably be considered inappropriate in a
+  professional setting
+
+## Our Responsibilities
+
+Project maintainers are responsible for clarifying the standards of acceptable
+behavior and are expected to take appropriate and fair corrective action in
+response to any instances of unacceptable behavior.
+
+Project maintainers have the right and responsibility to remove, edit, or
+reject comments, commits, code, wiki edits, issues, and other contributions
+that are not aligned to this Code of Conduct, or to ban temporarily or
+permanently any contributor for other behaviors that they deem inappropriate,
+threatening, offensive, or harmful.
+
+## Scope
+
+This Code of Conduct applies both within project spaces and in public spaces
+when an individual is representing the project or its community. Examples of
+representing a project or community include using an official project e-mail
+address, posting via an official social media account, or acting as an appointed
+representative at an online or offline event. Representation of a project may be
+further defined and clarified by project maintainers.
+
+## Enforcement
+
+Instances of abusive, harassing, or otherwise unacceptable behavior may be
+reported by contacting the project team at taichi730@gmail.com. All
+complaints will be reviewed and investigated and will result in a response that
+is deemed necessary and appropriate to the circumstances. The project team is
+obligated to maintain confidentiality with regard to the reporter of an incident.
+Further details of specific enforcement policies may be posted separately.
+
+Project maintainers who do not follow or enforce the Code of Conduct in good
+faith may face temporary or permanent repercussions as determined by other
+members of the project's leadership.
+
+## Attribution
+
+This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4,
+available at [http://contributor-covenant.org/version/1/4][version]
+
+[homepage]: http://contributor-covenant.org
+[version]: http://contributor-covenant.org/version/1/4/

data/LICENSE

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+The MIT License (MIT)
+
+Copyright (c) 2019 Taichi Ishitani
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.

data/README.md

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+[![Build Status](https://travis-ci.org/rggen/rggen-systemverilog.svg?branch=master)](https://travis-ci.org/rggen/rggen-systemverilog)
+[![Maintainability](https://api.codeclimate.com/v1/badges/88086c5be538a1564a35/maintainability)](https://codeclimate.com/github/rggen/rggen-systemverilog/maintainability)
+[![codecov](https://codecov.io/gh/rggen/rggen-systemverilog/branch/master/graph/badge.svg)](https://codecov.io/gh/rggen/rggen-systemverilog)
+[![Quality Gate Status](https://sonarcloud.io/api/project_badges/measure?project=rggen_rggen-systemverilog&metric=alert_status)](https://sonarcloud.io/dashboard?id=rggen_rggen-systemverilog)
+
+# RgGen::SystemVerilog
+
+RgGen::SystemVerilog provides for features listed below:
+
+* Structure for defining SystemVerilog RTL and UVM RAL model writers
+* Convience APIs for SystemVerilog code
+    * Declaring signals, ports and variables
+    * Generating code to define module, class and package
+    * Etc.
+
+## Installation
+
+During RgGen installation, RgGen::SytemVerilog will also be installed automatically.
+
+```
+$ gem install rggen
+```
+
+If you want to install RgGen::SytemVerilog only, use the command below:
+
+```
+$ gem isntall rggen-systemverilog
+```
+
+## Contact
+
+Feedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:
+
+* [GitHub Issue Tracker](https://github.com/rggen/rggen-systemverilog/issues)
+* [Mail](mailto:taichi730@gmail.com)
+
+## Copyright & License
+
+Copyright © 2019 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+
+## Code of Conduct
+
+Everyone interacting in the RgGen project’s codebases, issue trackers, chat rooms and mailing lists is expected to follow the [code of conduct](https://github.com/rggen/rggen-systemverilog/blob/master/CODE_OF_CONDUCT.md).

data/lib/rggen/systemverilog.rb

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+# frozen_string_literal: true
+
+require 'docile'
+require 'facets/kernel/attr_singleton'
+
+require_relative 'systemverilog/version'
+
+require_relative 'systemverilog/utility/identifier'
+require_relative 'systemverilog/utility/data_object'
+require_relative 'systemverilog/utility/interface_port'
+require_relative 'systemverilog/utility/interface_instance'
+require_relative 'systemverilog/utility/structure_definition'
+require_relative 'systemverilog/utility/class_definition'
+require_relative 'systemverilog/utility/function_definition'
+require_relative 'systemverilog/utility/local_scope'
+require_relative 'systemverilog/utility/module_definition'
+require_relative 'systemverilog/utility/package_definition'
+require_relative 'systemverilog/utility/source_file'
+require_relative 'systemverilog/utility'
+
+require_relative 'systemverilog/component'
+require_relative 'systemverilog/feature'
+require_relative 'systemverilog/feature_rtl'
+require_relative 'systemverilog/feature_ral'
+require_relative 'systemverilog/factories'
+
+module RgGen
+  module SystemVerilog
+    class << self
+      def setup_sv_component(builder, name, sv_feature)
+        builder.output_component_registry(name) do
+          register_component [
+            :register_map, :register_block, :register, :bit_field
+          ] do |category|
+            component Component, ComponentFactory
+            feature sv_feature, FeatureFactory if category != :register_map
+          end
+        end
+      end
+
+      def setup(builder)
+        setup_sv_component(builder, :sv_rtl, FeatureRTL)
+        setup_sv_component(builder, :sv_ral, FeatureRAL)
+      end
+    end
+  end
+
+  setup :systemverilog, SystemVerilog
+end

data/lib/rggen/systemverilog/component.rb

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+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    class Component < Core::OutputBase::Component
+      def declarations(domain, type)
+        body = ->(r) { r.declarations(domain, type) }
+        [
+          @features.each_value.map(&body),
+          @children.map(&body)
+        ].flatten
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/factories.rb

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+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    class ComponentFactory < Core::OutputBase::ComponentFactory
+    end
+
+    class FeatureFactory < Core::OutputBase::FeatureFactory
+    end
+  end
+end

data/lib/rggen/systemverilog/feature.rb

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+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    class Feature < Core::OutputBase::Feature
+      include Utility
+      template_engine Core::OutputBase::ERBEngine
+
+      EntityContext =
+        Struct.new(:entity_type, :creation_method, :declaration_type)
+
+      class << self
+        private
+
+        def define_entity(entity_type, creation_method, declaration_type)
+          context =
+            EntityContext.new(entity_type, creation_method, declaration_type)
+          define_method(entity_type) do |domain, name, **attributes, &block|
+            entity =
+              create_entity(context, { name: name }.merge(attributes), block)
+            add_entity(entity, context, domain, name)
+          end
+        end
+      end
+
+      def declarations(domain, type)
+        @declarations[domain][type]
+      end
+
+      private
+
+      def post_initialize
+        super
+        @declarations = Hash.new do |h0, k0|
+          h0[k0] = Hash.new { |h1, k1| h1[k1] = [] }
+        end
+      end
+
+      def create_entity(context, attributes, block)
+        creation_method = context.creation_method
+        entity_type = context.entity_type
+        __send__(creation_method, entity_type, attributes, block)
+      end
+
+      def add_entity(entity, context, domain, name)
+        add_declaration(context, domain, entity.declaration)
+        add_identifier(name, entity.identifier)
+      end
+
+      def add_declaration(context, domain, declaration)
+        declaration_type = context.declaration_type
+        @declarations[domain][declaration_type] << declaration
+      end
+
+      def add_identifier(name, identifier)
+        instance_variable_set("@#{name}", identifier)
+        attr_singleton_reader(name)
+        export(name)
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/feature_ral.rb

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+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    class FeatureRAL < Feature
+      private
+
+      def create_variable(_, attributes, block)
+        DataObject.new(
+          :variable, attributes.merge(array_format: :unpacked), &block
+        )
+      end
+
+      def create_parameter(_, attributes, block)
+        DataObject.new(
+          :parameter, attributes, &block
+        )
+      end
+
+      define_entity :variable, :create_variable, :variable
+      define_entity :parameter, :create_parameter, :parameter
+    end
+  end
+end

data/lib/rggen/systemverilog/feature_rtl.rb

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+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    class FeatureRTL < Feature
+      private
+
+      def create_variable(data_type, attributes, block)
+        DataObject.new(
+          :variable, attributes.merge(data_type: data_type), &block
+        )
+      end
+
+      def create_interface(_, attributes, block)
+        InterfaceInstance.new(attributes, &block)
+      end
+
+      def create_argument(direction, attributes, block)
+        DataObject.new(
+          :argument, attributes.merge(direction: direction), &block
+        )
+      end
+
+      def create_interface_port(_, attributes, block)
+        InterfacePort.new(attributes, &block)
+      end
+
+      def create_parameter(_, attributes, block)
+        DataObject.new(
+          :parameter, attributes.merge(parameter_type: :parameter), &block
+        )
+      end
+
+      [
+        [:logic, :create_variable, :variable],
+        [:interface, :create_interface, :variable],
+        [:input, :create_argument, :port],
+        [:output, :create_argument, :port],
+        [:interface_port, :create_interface_port, :port],
+        [:parameter, :create_parameter, :parameter]
+      ].each do |entity, creation_method, declaration_type|
+        define_entity(entity, creation_method, declaration_type)
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/utility.rb

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+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module Utility
+      include Core::Utility::CodeUtility
+
+      def create_blank_file(path)
+        SourceFile.new(path)
+      end
+
+      private
+
+      def create_identifier(name)
+        Identifier.new(name)
+      end
+
+      def assign(lhs, rhs)
+        "assign #{lhs} = #{rhs};"
+      end
+
+      def concat(expressions)
+        "{#{Array(expressions).join(', ')}}"
+      end
+
+      def array(expressions)
+        "'#{concat(expressions)}"
+      end
+
+      def function_call(name, expressions = nil)
+        "#{name}(#{Array(expressions).join(', ')})"
+      end
+
+      def macro_call(name, expressions = nil)
+        if (expression_array = Array(expressions)).empty?
+          "`#{name}"
+        else
+          "`#{name}(#{expression_array.join(', ')})"
+        end
+      end
+
+      def bin(value, width = nil)
+        if width
+          width = bit_width(value, width)
+          format("%d'b%0*b", width, width, value)
+        else
+          format("'b%b", value)
+        end
+      end
+
+      def dec(value, width = nil)
+        if width
+          width = bit_width(value, width)
+          format("%0d'd%d", width, value)
+        else
+          format("'d%d", value)
+        end
+      end
+
+      def hex(value, width = nil)
+        if width
+          width = bit_width(value, width)
+          print_width = (width + 3) / 4
+          format("%0d'h%0*x", width, print_width, value)
+        else
+          format("'h%x", value)
+        end
+      end
+
+      def bit_width(value, width)
+        bit_length = value.bit_length
+        bit_length = 1 if bit_length.zero?
+        [width, bit_length].max
+      end
+
+      def argument(name, **attribute)
+        DataObject.new(:argument, attribute.merge(name: name)).declaration
+      end
+
+      {
+        class_definition: ClassDefinition,
+        function_definition: FunctionDefinition,
+        local_scope: LocalScope,
+        module_definition: ModuleDefinition,
+        package_definition: PackageDefinition
+      }.each do |method_name, definition|
+        define_method(method_name) do |name, **attributes, &block|
+          definition.new(attributes.merge(name: name), &block).to_code
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/utility/class_definition.rb

@@ -0,0 +1,43 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module Utility
+      class ClassDefinition < StructureDefinition
+        define_attribute :name
+        define_attribute :base
+        define_attribute :parameters
+        define_attribute :variables
+
+        private
+
+        def header_code(code)
+          code << [:class, space, name]
+          parameter_declarations(code)
+          class_inheritance(code)
+          code << semicolon
+        end
+
+        def parameter_declarations(code)
+          declarations = Array(parameters)
+          declarations.empty? || wrap(code << space, '#(', ')') do
+            add_declarations_to_header(code, declarations)
+          end
+        end
+
+        def class_inheritance(code)
+          return unless base
+          code << [space, :extends, space, base]
+        end
+
+        def pre_body_code(code)
+          add_declarations_to_body(code, Array(variables))
+        end
+
+        def footer_code
+          :endclass
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/utility/data_object.rb

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+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module Utility
+      class DataObject
+        include Core::Utility::AttributeSetter
+
+        def initialize(object_type, **default_attributes)
+          @object_type = object_type
+          apply_attributes(default_attributes)
+          block_given? && yield(self)
+        end
+
+        define_attribute :name
+        define_attribute :direction
+        define_attribute :parameter_type
+        define_attribute :data_type
+        define_attribute :width
+        define_attribute :array_size
+        define_attribute :array_format, :packed
+        define_attribute :random
+        define_attribute :default
+
+        def declaration
+          declaration_snippets
+            .select(&:itself)
+            .reject(&:empty?)
+            .join(' ')
+        end
+
+        def identifier
+          Identifier.new(name) do |identifier|
+            identifier.__width__(width)
+            identifier.__array_size__(array_size)
+            identifier.__array_format__(array_format)
+          end
+        end
+
+        private
+
+        def declaration_snippets
+          [
+            rand_keyword,
+            argument_direction,
+            paraemter_keyword,
+            data_type,
+            packed_dimensions,
+            object_identifier,
+            default_value
+          ]
+        end
+
+        def rand_keyword
+          return unless @object_type == :variable
+          return unless random
+          return :rand if random.equal?(true)
+          random
+        end
+
+        def argument_direction
+          @object_type == :argument && direction
+        end
+
+        def paraemter_keyword
+          @object_type == :parameter && parameter_type
+        end
+
+        def packed_dimensions
+          (vectorized_array? ? vectorized_array_size : packed_array_size)
+            .map { |size| "[#{msb(size)}:0]" }
+            .join
+        end
+
+        def msb(size)
+          (size.is_a?(Integer) && size - 1) || "#{size}-1"
+        end
+
+        def array?
+          return false unless array_size
+          !array_size.empty?
+        end
+
+        def vectorized_array?
+          array? && array_format == :vectorized
+        end
+
+        def vectorized_array_size
+          size = [(width || 1), *array_size]
+          if size.all? { |s| s.is_a?(Integer) }
+            [size.inject(&:*)]
+          else
+            [size.join('*')]
+          end
+        end
+
+        def packed_array_size
+          size = []
+          size.concat(Array(array_size)) if array_format == :packed
+          size << width if valid_width?
+          size
+        end
+
+        def valid_width?
+          return false unless width
+          return true unless width.is_a?(Integer)
+          width > 1
+        end
+
+        def object_identifier
+          "#{name}#{unpacked_dimensions}"
+        end
+
+        def unpacked_array?
+          array? && array_format == :unpacked
+        end
+
+        def unpacked_dimensions
+          return unless unpacked_array?
+          array_size.map { |size| "[#{size}]" }.join
+        end
+
+        def default_value
+          default && "= #{default}"
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/utility/function_definition.rb

@@ -0,0 +1,45 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module Utility
+      class FunctionDefinition < StructureDefinition
+        define_attribute :name
+        define_attribute :return_type
+        define_attribute :arguments
+
+        def return_type(**attributes)
+          attributes.size.zero? || (
+            @return_type = DataObject.new(:variable, **attributes)
+          )
+          @return_type
+        end
+
+        private
+
+        def header_code(code)
+          code << :function
+          return_type_declaration(code)
+          code << [space, name]
+          argument_declarations(code)
+          code << semicolon
+        end
+
+        def return_type_declaration(code)
+          return unless @return_type
+          code << [space, return_type.declaration]
+        end
+
+        def argument_declarations(code)
+          wrap(code, '(', ')') do
+            add_declarations_to_header(code, Array(arguments))
+          end
+        end
+
+        def footer_code
+          :endfunction
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/utility/identifier.rb

@@ -0,0 +1,112 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module Utility
+      class Identifier
+        def initialize(name)
+          @name = name
+          block_given? && yield(self)
+        end
+
+        def __width__(width)
+          @width = width
+        end
+
+        def __array_size__(array_size)
+          @array_size = array_size
+        end
+
+        def __array_format__(array_format)
+          @array_format = array_format
+        end
+
+        def __sub_identifiers__(sub_identifiers)
+          Array(sub_identifiers).each do |sub_identifier|
+            (@sub_identifiers ||= []) << sub_identifier
+            define_singleton_method(sub_identifier) do
+              Identifier.new("#{@name}.#{__method__}")
+            end
+          end
+        end
+
+        def to_s
+          @name.to_s
+        end
+
+        def [](array_index_or_lsb, width = nil)
+          if array_index_or_lsb
+            __create_new_identifier__(array_index_or_lsb, width)
+          else
+            self
+          end
+        end
+
+        private
+
+        def __create_new_identifier__(array_index_or_lsb, width)
+          select = __create_select__(array_index_or_lsb, width)
+          Identifier.new("#{@name}#{select}") do |identifier|
+            identifier.__sub_identifiers__(@sub_identifiers)
+          end
+        end
+
+        def __create_select__(array_index_or_lsb, width)
+          if array_index_or_lsb.is_a?(::Array)
+            __array_select__(array_index_or_lsb)
+          elsif width
+            "[#{array_index_or_lsb}+:#{width}]"
+          else
+            "[#{array_index_or_lsb}]"
+          end
+        end
+
+        def __array_select__(array_index)
+          if @array_format == :vectorized
+            "[#{__vecotr_lsb__(array_index)}+:#{@width}]"
+          else
+            array_index
+              .map { |index| "[#{index}]" }
+              .join
+          end
+        end
+
+        def __vecotr_lsb__(array_index)
+          __reduce_array__([@width, __vecotr_index__(array_index)], :*, 1)
+        end
+
+        def __vecotr_index__(array_index)
+          index_values =
+            array_index
+              .reverse
+              .zip(__index_factors__)
+              .map { |i, f| __calc_index_value__(i, f) }
+          index = __reduce_array__(index_values.reverse, :+, 0)
+          integer?(index) ? index : "(#{index})"
+        end
+
+        def __index_factors__
+          Array.new(@array_size.size) do |i|
+            i.zero? ? nil : __reduce_array__(@array_size[-i..-1], :*, 1)
+          end
+        end
+
+        def __calc_index_value__(index, factor)
+          __reduce_array__([factor, index].compact, :*, 1)
+        end
+
+        def __reduce_array__(array, operator, initial_value)
+          if array.all?(&method(:integer?))
+            array.reduce(initial_value, &operator)
+          else
+            array.join(operator.to_s)
+          end
+        end
+
+        def integer?(value)
+          value.is_a?(Integer)
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/utility/interface_instance.rb

@@ -0,0 +1,55 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module Utility
+      class InterfaceInstance
+        include Core::Utility::AttributeSetter
+
+        def initialize(**default_attributes)
+          apply_attributes(default_attributes)
+          block_given? && yield(self)
+        end
+
+        define_attribute :name
+        define_attribute :interface_type
+        define_attribute :parameter_values
+        define_attribute :port_connections
+        define_attribute :array_size
+        define_attribute :variables
+
+        def instantiation
+          [
+            interface_type,
+            parameter_value_assignments,
+            instance_identifier
+          ].select(&:itself).join(' ')
+        end
+
+        alias_method :declaration, :instantiation
+
+        def identifier
+          Identifier.new(name) do |identifier|
+            identifier.__array_size__(array_size)
+            identifier.__sub_identifiers__(variables)
+          end
+        end
+
+        private
+
+        def parameter_value_assignments
+          values = Array(parameter_values)
+          values.size.positive? && "#(#{values.join(', ')})"
+        end
+
+        def instance_identifier
+          [
+            name,
+            *Array(array_size).map { |size| "[#{size}]" },
+            "(#{Array(port_connections).join(', ')})"
+          ].join
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/utility/interface_port.rb

@@ -0,0 +1,49 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module Utility
+      class InterfacePort
+        include Core::Utility::AttributeSetter
+
+        def initialize(**default_attributes)
+          apply_attributes(default_attributes)
+          block_given? && yield(self)
+        end
+
+        define_attribute :name
+        define_attribute :interface_type
+        define_attribute :modport
+        define_attribute :array_size
+
+        def modport(name, ports = nil)
+          @modport_name = name
+          @modport_ports = ports
+        end
+
+        def declaration
+          "#{port_type} #{port_identifier}"
+        end
+
+        def identifier
+          Identifier.new(name) do |identifier|
+            identifier.__array_size__(array_size)
+            identifier.__sub_identifiers__(@modport_ports)
+          end
+        end
+
+        private
+
+        def port_type
+          [@interface_type, @modport_name].compact.join('.')
+        end
+
+        def port_identifier
+          [
+            name, *Array(array_size).map { |size| "[#{size}]" }
+          ].join
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/utility/local_scope.rb

@@ -0,0 +1,62 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module Utility
+      class LocalScope < StructureDefinition
+        define_attribute :name
+        define_attribute :variables
+        define_attribute :loop_size
+
+        def top_scope
+          @top_scope = true
+        end
+
+        private
+
+        def header_code(code)
+          code << [:generate, space] if @top_scope
+          code << "if (1) begin : #{name}" << nl
+        end
+
+        def footer_code(code)
+          code << :end
+          code << [space, :endgenerate] if @top_scope
+        end
+
+        def pre_body_code(code)
+          genvar_declarations(code)
+          generate_for_header(code)
+          variable_declarations(code)
+        end
+
+        def genvar_declarations(code)
+          genvars = Array(loop_size&.keys).map { |genvar| "genvar #{genvar}" }
+          add_declarations_to_body(code, genvars)
+        end
+
+        def generate_for_header(code)
+          loop_size&.each do |genvar, size|
+            code << generate_for(genvar, size) << nl
+            code.indent += 2
+          end
+        end
+
+        def generate_for(genvar, size)
+          "for (#{genvar} = 0;#{genvar} < #{size};++#{genvar}) begin : g"
+        end
+
+        def variable_declarations(code)
+          add_declarations_to_body(code, Array(variables))
+        end
+
+        def post_body_code(code)
+          (loop_size&.size || 0).times do
+            code.indent -= 2
+            code << :end << nl
+          end
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/utility/module_definition.rb

@@ -0,0 +1,74 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module Utility
+      class ModuleDefinition < StructureDefinition
+        define_attribute :name
+        define_attribute :package_imports
+        define_attribute :parameters
+        define_attribute :ports
+        define_attribute :variables
+
+        def package_imports(packages)
+          @package_imports ||= []
+          @package_imports.concat(Array(packages))
+        end
+
+        def package_import(package)
+          package_imports([package])
+        end
+
+        private
+
+        def header_code(code)
+          code << [:module, space, name]
+          package_import_declaration(code)
+          parameter_declarations(code)
+          port_declarations(code)
+          code << semicolon
+        end
+
+        def package_import_declaration(code)
+          if (items = pacakge_import_items).empty?
+            code << space
+            return
+          end
+          add_declarations_to_header(code, items, semicolon)
+        end
+
+        def pacakge_import_items
+          Array(@package_imports).map.with_index do |package, i|
+            if i.zero?
+              [:import, "#{package}::*"].join(space)
+            else
+              [space(6), "#{package}::*"].join(space)
+            end
+          end
+        end
+
+        def parameter_declarations(code)
+          declarations = Array(parameters)
+          declarations.empty? || wrap(code, '#(', ')') do
+            add_declarations_to_header(code, declarations)
+          end
+        end
+
+        def port_declarations(code)
+          declarations = Array(ports)
+          wrap(code, '(', ')') do
+            add_declarations_to_header(code, declarations)
+          end
+        end
+
+        def pre_body_code(code)
+          add_declarations_to_body(code, Array(variables))
+        end
+
+        def footer_code
+          :endmodule
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/utility/package_definition.rb

@@ -0,0 +1,59 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module Utility
+      class PackageDefinition < StructureDefinition
+        define_attribute :name
+        define_attribute :package_imports
+        define_attribute :include_files
+
+        def package_imports(packages)
+          @package_imports ||= []
+          @package_imports.concat(Array(packages))
+        end
+
+        def package_import(package)
+          package_imports([package])
+        end
+
+        def include_files(files)
+          @include_files ||= []
+          @include_files.concat(Array(files))
+        end
+
+        def include_file(file)
+          include_files([file])
+        end
+
+        private
+
+        def header_code(code)
+          code << [:package, space, name, semicolon]
+        end
+
+        def pre_body_code(code)
+          package_import_declaration(code)
+          file_include_directives(code)
+        end
+
+        def package_import_declaration(code)
+          declarations =
+            Array(@package_imports)
+              .map { |package| [:import, space, package, '::*'] }
+          add_declarations_to_body(code, declarations)
+        end
+
+        def file_include_directives(code)
+          Array(@include_files).each do |file|
+            code << [:'`include', space, string(file), nl]
+          end
+        end
+
+        def footer_code
+          :endpackage
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/utility/source_file.rb

@@ -0,0 +1,14 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module Utility
+      class SourceFile < Core::Utility::CodeUtility::SourceFile
+        ifndef_keyword :'`ifndef'
+        endif_keyword :'`endif'
+        define_keyword :'`define'
+        include_keyword :'`include'
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/utility/structure_definition.rb

@@ -0,0 +1,37 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module Utility
+      class StructureDefinition <
+        Core::Utility::CodeUtility::StructureDefinition
+
+        include Core::Utility::AttributeSetter
+
+        def initialize(**default_attributes, &block)
+          apply_attributes(default_attributes)
+          super(&block)
+        end
+
+        private
+
+        def add_declarations_to_header(code, declarations, end_charactor = '')
+          declarations.empty? || indent(code, 2) do
+            declarations.each_with_index do |d, i|
+              code <<
+                if i < (declarations.size - 1)
+                  [d, comma, nl]
+                else
+                  [d, end_charactor]
+                end
+            end
+          end
+        end
+
+        def add_declarations_to_body(code, declarations, end_charactor = ';')
+          declarations.each { |d| code << d << end_charactor << nl }
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/version.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    VERSION = '0.9.0'
+  end
+end

metadata

@@ -0,0 +1,112 @@
+--- !ruby/object:Gem::Specification
+name: rggen-systemverilog
+version: !ruby/object:Gem::Version
+  version: 0.9.0
+platform: ruby
+authors:
+- Taichi Ishitani
+autorequire: 
+bindir: bin
+cert_chain: []
+date: 2019-07-26 00:00:00.000000000 Z
+dependencies:
+- !ruby/object:Gem::Dependency
+  name: docile
+  requirement: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: 1.1.5
+  type: :runtime
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: 1.1.5
+- !ruby/object:Gem::Dependency
+  name: facets
+  requirement: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: '3.0'
+  type: :runtime
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: '3.0'
+- !ruby/object:Gem::Dependency
+  name: bundler
+  requirement: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: '0'
+  type: :development
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: '0'
+description: 'Structure of SystemVerilog RTL and UVM RAL model writers for Rggen.
+
+'
+email:
+- taichi730@gmail.com
+executables: []
+extensions: []
+extra_rdoc_files: []
+files:
+- CODE_OF_CONDUCT.md
+- LICENSE
+- README.md
+- lib/rggen/systemverilog.rb
+- lib/rggen/systemverilog/component.rb
+- lib/rggen/systemverilog/factories.rb
+- lib/rggen/systemverilog/feature.rb
+- lib/rggen/systemverilog/feature_ral.rb
+- lib/rggen/systemverilog/feature_rtl.rb
+- lib/rggen/systemverilog/utility.rb
+- lib/rggen/systemverilog/utility/class_definition.rb
+- lib/rggen/systemverilog/utility/data_object.rb
+- lib/rggen/systemverilog/utility/function_definition.rb
+- lib/rggen/systemverilog/utility/identifier.rb
+- lib/rggen/systemverilog/utility/interface_instance.rb
+- lib/rggen/systemverilog/utility/interface_port.rb
+- lib/rggen/systemverilog/utility/local_scope.rb
+- lib/rggen/systemverilog/utility/module_definition.rb
+- lib/rggen/systemverilog/utility/package_definition.rb
+- lib/rggen/systemverilog/utility/source_file.rb
+- lib/rggen/systemverilog/utility/structure_definition.rb
+- lib/rggen/systemverilog/version.rb
+homepage: https://github.com/rggen/rggen-systemverilog
+licenses:
+- MIT
+metadata:
+  bug_tracker_uri: https://github.com/rggen/rggen-systemverilog/issues
+  source_code_uri: https://github.com/rggen/rggen-systemverilog
+  wiki_uri: https://github.com/rggen/rggen/wiki
+post_install_message: 
+rdoc_options: []
+require_paths:
+- lib
+required_ruby_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: '2.3'
+required_rubygems_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: '0'
+requirements: []
+rubygems_version: 3.0.3
+signing_key: 
+specification_version: 4
+summary: rggen-systemverilog-0.9.0
+test_files: []