rggen-systemverilog 0.35.0 → 0.36.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019-2025 Taichi Ishitani
+Copyright (c) 2019-2026 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -2,7 +2,7 @@
 [![CI](https://github.com/rggen/rggen-systemverilog/workflows/CI/badge.svg)](https://github.com/rggen/rggen-systemverilog/actions?query=workflow%3ACI)
 [![Maintainability](https://qlty.sh/badges/1b06df23-43bd-413d-90f9-b98c565be895/maintainability.svg)](https://qlty.sh/gh/rggen/projects/rggen-systemverilog)
 [![codecov](https://codecov.io/gh/rggen/rggen-systemverilog/branch/master/graph/badge.svg)](https://codecov.io/gh/rggen/rggen-systemverilog)
-[![Gitter](https://badges.gitter.im/rggen/rggen.svg)](https://gitter.im/rggen/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
+[![Discord](https://img.shields.io/discord/1406572699467124806?style=flat&logo=discord)](https://discord.com/invite/KWya83ZZxr)
 
 # RgGen::SystemVerilog
 
@@ -28,13 +28,13 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 
 * [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)
 * [GitHub Discussions](https://github.com/rggen/rggen/discussions)
-* [Chat Room](https://gitter.im/rggen/rggen)
+* [Discord](https://discord.com/invite/KWya83ZZxr)
 * [Mailing List](https://groups.google.com/d/forum/rggen)
 * [Mail](mailto:rggen@googlegroups.com)
 
 ## Copyright & License
 
-Copyright © 2019-2025 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2019-2026 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/systemverilog/common/feature.rb

@@ -5,6 +5,7 @@ module RgGen
     module Common
       class Feature < Core::OutputBase::Feature
         include Common::Utility
+
         template_engine Core::OutputBase::ERBEngine
 
         EntityContext =

data/lib/rggen/systemverilog/ral/bit_field/type/counter_rwc_rwhw_rws.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:counter, :rwc, :rwhw, :rws]) do
+  sv_ral { access 'RW' }
+end

data/lib/rggen/systemverilog/ral/register/type/maskable.rb

@@ -0,0 +1,19 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :maskable) do
+  sv_ral do
+    main_code :ral_package do
+      class_definition(model_name) do |sv_class|
+        sv_class.base 'rggen_ral_maskable_reg'
+        sv_class.variables variables
+        sv_class.body { model_body }
+      end
+    end
+
+    private
+
+    def model_body
+      process_template(File.join(__dir__, 'default.erb'))
+    end
+  end
+end

data/lib/rggen/systemverilog/ral.rb

@@ -22,13 +22,14 @@ RgGen.setup_plugin :'rggen-sv-ral' do |plugin|
     'ral/register/type',
     'ral/register/type/external',
     'ral/register/type/indirect',
+    'ral/register/type/maskable',
     'ral/bit_field/type',
+    'ral/bit_field/type/counter_rwc_rwhw_rws',
     'ral/bit_field/type/custom',
     'ral/bit_field/type/rof_rohw',
     'ral/bit_field/type/rotrg_rwtrg_wotrg',
     'ral/bit_field/type/row0trg_row1trg_w0trg_w1trg',
     'ral/bit_field/type/rowo_rowotrg',
-    'ral/bit_field/type/rwc_rwhw_rws',
     'ral/bit_field/type/rwe_rwl'
   ]
 

data/lib/rggen/systemverilog/rtl/bit_field/type/counter.erb

@@ -0,0 +1,16 @@
+rggen_bit_field_counter #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .UP_WIDTH       (<%= up_width %>),
+  .DOWN_WIDTH     (<%= down_width %>),
+  .WRAP_AROUND    (<%= wrap_around %>),
+  .USE_CLEAR      (<%= use_clear_value %>)
+) u_bit_field (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .i_clear      (<%= clear_signal %>),
+  .i_up         (<%= up[loop_variables]%>),
+  .i_down       (<%= down[loop_variables] %>),
+  .o_count      (<%= count[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/counter.rb

@@ -0,0 +1,59 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :counter) do
+  sv_rtl do
+    build do
+      parameter :up_width, {
+        name: "#{full_name}_up_width".upcase,
+        data_type: :int, default: 1
+      }
+      parameter :down_width, {
+        name: "#{full_name}_down_width".upcase,
+        data_type: :int, default: 1
+      }
+      parameter :wrap_around, {
+        name: "#{full_name}_wrap_around".upcase,
+        data_type: :bit, default: 0
+      }
+      if external_clear?
+        parameter :use_clear, {
+          name: "#{full_name}_use_clear".upcase,
+          data_type: :bit, default: 1
+        }
+      end
+
+      input :up, {
+        name: "i_#{full_name}_up",
+        width: function_call(:rggen_clip_width, [up_width]), array_size:
+      }
+      input :down, {
+        name: "i_#{full_name}_down",
+        width: function_call(:rggen_clip_width, [down_width]), array_size:
+      }
+      if external_clear?
+        input :clear, {
+          name: "i_#{full_name}_clear", width: 1, array_size:
+        }
+      end
+      output :count, {
+        name: "o_#{full_name}", width:, array_size:
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def external_clear?
+      !bit_field.reference?
+    end
+
+    def use_clear_value
+      external_clear? && use_clear || 1
+    end
+
+    def clear_signal
+      reference_bit_field || clear[loop_variables]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/custom.erb

@@ -4,6 +4,7 @@ rggen_bit_field #(
   .SW_READ_ACTION     (<%= sw_read_action %>),
   .SW_WRITE_ACTION    (<%= sw_write_action %>),
   .SW_WRITE_ONCE      (<%= write_once %>),
+  .HW_ACCESS          (<%= hw_access %>),
   .STORAGE            (<%= storage %>),
   .EXTERNAL_READ_DATA (<%= external_read_data %>),
   .TRIGGER            (<%= trigger %>)

data/lib/rggen/systemverilog/rtl/bit_field/type/custom.rb

@@ -82,6 +82,15 @@ RgGen.define_list_item_feature(:bit_field, :type, :custom) do
       bit_field.sw_write_once? && 1 || 0
     end
 
+    def hw_access
+      values = [
+        bit_field.hw_clear? && 1 || 0,
+        bit_field.hw_set? && 1 || 0,
+        bit_field.hw_write? && 1 || 0
+      ]
+      "3'b#{values.join}"
+    end
+
     def storage
       external_read_data? && 0 || 1
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb

@@ -2,14 +2,16 @@ rggen_bit_field #(
   .WIDTH            (<%= width %>),
   .INITIAL_VALUE    (<%= initial_value %>),
   .SW_READ_ACTION   (<%= read_action %>),
-  .SW_WRITE_ACTION  (<%= write_action %>)
+  .SW_WRITE_ACTION  (<%= write_action %>),
+  .HW_ACCESS        (3'b010),
+  .EXTERNAL_MASK    (<%= external_mask %>)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
   .o_write_trigger    (),
   .o_read_trigger     (),
-  .i_sw_write_enable  (<%= write_enable %>),
+  .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),
   .i_hw_set           (<%= set[loop_variables] %>),

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb

@@ -40,12 +40,12 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc])
       }[bit_field.type]
     end
 
-    def write_enable
-      bit_field.writable? && all_bits_1 || all_bits_0
-    end
-
     def value_out_unmasked
       (bit_field.reference? || nil) && value_unmasked[loop_variables]
     end
+
+    def external_mask
+      bit_field.reference? && 1 || 0
+    end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/rohw.erb

@@ -1,7 +1,8 @@
 rggen_bit_field #(
   .WIDTH            (<%= width %>),
   .INITIAL_VALUE    (<%= initial_value %>),
-  .SW_WRITE_ACTION  (RGGEN_WRITE_NONE)
+  .SW_WRITE_ACTION  (RGGEN_WRITE_NONE),
+  .HW_ACCESS        (3'b001)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -2,14 +2,15 @@ rggen_bit_field #(
   .WIDTH            (<%= width %>),
   .INITIAL_VALUE    (<%= initial_value %>),
   .SW_READ_ACTION   (<%= read_action %>),
-  .SW_WRITE_ACTION  (<%= write_action %>)
+  .SW_WRITE_ACTION  (<%= write_action %>),
+  .HW_ACCESS        (3'b100)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
   .o_write_trigger    (),
   .o_read_trigger     (),
-  .i_sw_write_enable  (<%= write_enable %>),
+  .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),
   .i_hw_set           ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb

@@ -34,9 +34,5 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos])
         wos: 'RGGEN_WRITE_SET'
       }[bit_field.type]
     end
-
-    def write_enable
-      bit_field.writable? && all_bits_1 || all_bits_0
-    end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb

@@ -1,6 +1,7 @@
 rggen_bit_field #(
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>),
+  .HW_ACCESS      (3'b100),
   .HW_CLEAR_WIDTH (1)
 ) u_bit_field (
   .i_clk              (<%= clock %>),

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb

@@ -1,6 +1,7 @@
 rggen_bit_field #(
   .WIDTH                    (<%= width %>),
   .INITIAL_VALUE            (<%= initial_value %>),
+  .SW_WRITE_CONTROL         (1),
   .SW_WRITE_ENABLE_POLARITY (<%= polarity %>)
 ) u_bit_field (
   .i_clk              (<%= clock %>),

data/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.erb

@@ -1,6 +1,7 @@
 rggen_bit_field #(
   .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .HW_ACCESS      (3'b001)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb

@@ -1,6 +1,7 @@
 rggen_bit_field #(
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>),
+  .HW_ACCESS      (3'b010),
   .HW_SET_WIDTH   (1)
 ) u_bit_field (
   .i_clk              (<%= clock %>),

data/lib/rggen/systemverilog/rtl/register/type/maskable.erb

@@ -0,0 +1,14 @@
+rggen_maskable_register #(
+  .READABLE       (<%= readable %>),
+  .WRITABLE       (<%= writable %>),
+  .ADDRESS_WIDTH  (<%= address_width %>),
+  .OFFSET_ADDRESS (<%= offset_address %>),
+  .BUS_WIDTH      (<%= bus_width %>),
+  .DATA_WIDTH     (<%= width %>),
+  .VALUE_WIDTH    (<%= value_width %>)
+) u_register (
+  .i_clk        (<%= register_block.clock %>),
+  .i_rst_n      (<%= register_block.reset %>),
+  .register_if  (<%= register_if %>),
+  .bit_field_if (<%= bit_field_if %>)
+);

data/lib/rggen/systemverilog/rtl/register/type/maskable.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :maskable) do
+  sv_rtl do
+    main_code :register, from_template: true
+  end
+end

data/lib/rggen/systemverilog/rtl/register_block/protocol.rb

@@ -6,13 +6,17 @@ RgGen.define_list_feature(:register_block, :protocol) do
       feature_registries << registry
     end
 
+    def no_rtl_writers?
+      feature_registries
+        .none? { |registry| registry.enabled_features.include?(:protocol) }
+    end
+
     def default_protocol
       available_protocols.first
     end
 
     def find_protocol(value)
-      available_protocols
-        .find { value.to_sym.casecmp?(_1) }
+      available_protocols.find { value.to_sym.casecmp?(_1) }
     end
 
     private
@@ -23,7 +27,7 @@ RgGen.define_list_feature(:register_block, :protocol) do
 
     def available_protocols
       feature_registries
-        .map { |registry| registry.enabled_features(:protocol) }
+        .filter_map { |registry| registry.enabled_features(:protocol) }
         .inject(:&)
     end
   end
@@ -39,6 +43,14 @@ RgGen.define_list_feature(:register_block, :protocol) do
 
       factory do
         convert_value do |value, position|
+          find_protocol(value, position)
+        end
+
+        private
+
+        def find_protocol(value, position)
+          return if shared_context.no_rtl_writers?
+
           shared_context.find_protocol(value) ||
             (error "unknown protocol: #{value.inspect}", position)
         end
@@ -54,13 +66,21 @@ RgGen.define_list_feature(:register_block, :protocol) do
 
     factory do
       default_value do |position|
-        shared_context.default_protocol ||
-          (error 'no protocols are available', position)
+        default_protocol(position)
       end
 
       def target_feature_key(data)
         data.value
       end
+
+      private
+
+      def default_protocol(position)
+        return if shared_context.no_rtl_writers?
+
+        shared_context.default_protocol ||
+          (error 'no protocols are available', position)
+      end
     end
   end
 

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb

@@ -1,11 +1,13 @@
 `ifndef rggen_connect_bit_field_if
   `define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \
-  assign  FIF.valid                 = RIF.valid; \
-  assign  FIF.read_mask             = RIF.read_mask[LSB+:WIDTH]; \
-  assign  FIF.write_mask            = RIF.write_mask[LSB+:WIDTH]; \
-  assign  FIF.write_data            = RIF.write_data[LSB+:WIDTH]; \
-  assign  RIF.read_data[LSB+:WIDTH] = FIF.read_data; \
-  assign  RIF.value[LSB+:WIDTH]     = FIF.value;
+  always_comb begin \
+    FIF.write_valid           = RIF.write_valid; \
+    FIF.read_valid            = RIF.read_valid; \
+    FIF.mask                  = RIF.mask[LSB+:WIDTH]; \
+    FIF.write_data            = RIF.write_data[LSB+:WIDTH]; \
+    RIF.read_data[LSB+:WIDTH] = FIF.read_data; \
+    RIF.value[LSB+:WIDTH]     = FIF.value; \
+  end
 `endif
 `ifndef rggen_tie_off_unused_signals
   `define rggen_tie_off_unused_signals(WIDTH, VALID_BITS, RIF) \
@@ -13,8 +15,10 @@
     genvar  __i; \
     for (__i = 0;__i < WIDTH;++__i) begin : g \
       if ((((VALID_BITS) >> __i) % 2) == 0) begin : g \
-        assign  RIF.read_data[__i]  = 1'b0; \
-        assign  RIF.value[__i]      = 1'b0; \
+        always_comb begin \
+          RIF.read_data[__i]  = '0; \
+          RIF.value[__i]      = '0; \
+        end \
       end \
     end \
   end

data/lib/rggen/systemverilog/rtl.rb

@@ -33,9 +33,11 @@ RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
     'rtl/register/type',
     'rtl/register/type/external',
     'rtl/register/type/indirect',
+    'rtl/register/type/maskable',
     'rtl/register/type/rw',
     'rtl/bit_field/sv_rtl_top',
     'rtl/bit_field/type',
+    'rtl/bit_field/type/counter',
     'rtl/bit_field/type/custom',
     'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
     'rtl/bit_field/type/ro_rotrg',

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.35.0'
+    VERSION = '0.36.0'
   end
 end

metadata

@@ -1,13 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.35.0
+  version: 0.36.0
 platform: ruby
 authors:
 - Taichi Ishitani
 bindir: bin
 cert_chain: []
-date: 2025-02-19 00:00:00.000000000 Z
+date: 1980-01-02 00:00:00.000000000 Z
 dependencies: []
 description: 'SystemVerilog RTL and UVM RAL model generators for RgGen.
 
@@ -40,12 +40,12 @@ files:
 - lib/rggen/systemverilog/common/utility/structure_definition.rb
 - lib/rggen/systemverilog/ral.rb
 - lib/rggen/systemverilog/ral/bit_field/type.rb
+- lib/rggen/systemverilog/ral/bit_field/type/counter_rwc_rwhw_rws.rb
 - lib/rggen/systemverilog/ral/bit_field/type/custom.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rof_rohw.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb
 - lib/rggen/systemverilog/ral/bit_field/type/row0trg_row1trg_w0trg_w1trg.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb
-- lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw_rws.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb
 - lib/rggen/systemverilog/ral/feature.rb
 - lib/rggen/systemverilog/ral/register/type.rb
@@ -53,6 +53,7 @@ files:
 - lib/rggen/systemverilog/ral/register/type/external.rb
 - lib/rggen/systemverilog/ral/register/type/indirect.erb
 - lib/rggen/systemverilog/ral/register/type/indirect.rb
+- lib/rggen/systemverilog/ral/register/type/maskable.rb
 - lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb
 - lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb
 - lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb
@@ -64,6 +65,8 @@ files:
 - lib/rggen/systemverilog/rtl.rb
 - lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/bit_field/type.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/counter.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/counter.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/custom.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/custom.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
@@ -111,6 +114,8 @@ files:
 - lib/rggen/systemverilog/rtl/register/type/external.rb
 - lib/rggen/systemverilog/rtl/register/type/indirect.erb
 - lib/rggen/systemverilog/rtl/register/type/indirect.rb
+- lib/rggen/systemverilog/rtl/register/type/maskable.erb
+- lib/rggen/systemverilog/rtl/register/type/maskable.rb
 - lib/rggen/systemverilog/rtl/register/type/rw.erb
 - lib/rggen/systemverilog/rtl/register/type/rw.rb
 - lib/rggen/systemverilog/rtl/register_block/protocol.rb
@@ -150,14 +155,14 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '3.1'
+      version: '3.2'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.6.2
+rubygems_version: 4.0.3
 specification_version: 4
-summary: rggen-systemverilog-0.35.0
+summary: rggen-systemverilog-0.36.0
 test_files: []

data/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw_rws.rb

@@ -1,5 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rwhw, :rws]) do
-  sv_ral { access 'RW' }
-end