rggen-systemverilog 0.35.0 → 0.35.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: d847affbd147ff2959eb902a7faafde4e99b9612a65ea0d001508a86fcb94862
-  data.tar.gz: 4e1a31f3c1f8fa082fed1eb115ad01f4e06f4310dd7dc99fe91ec2d66886d038
+  metadata.gz: 5441e91c3aba911ffc939b52377fbe897b4b6d22eae77885a2d84c9ad039f514
+  data.tar.gz: 0a6537fbd0bd1c6aca0bf386a01639ecaa9eb872aa7ab9a457cdf081c629b4e0
 SHA512:
-  metadata.gz: 7c6084365cfaa7de447a6f5022646f42fa2e6e7eb7f713cd7d1ce4ed6d4b758795d4e66442c8c016ccb46d2fbbe38cb0b881068ab75d3780a4a7ac42797b91ff
-  data.tar.gz: 140f2292d953d72185b0bf03a04b55818ca29618a3b23f8f4ed02b38ff5833b277cb06dfe89bd472722b7c930f72e43aeca7bcbb70f39506ceb8be5ebf9c5a74
+  metadata.gz: 2512a43cb38779c6ba0180c5aea816708f9a085d7f6cb80d6ad4b2f7f4e387aa110451aeddc47c5df9b212343caa106e23cca671b068978dd49e36ac39dbf379
+  data.tar.gz: c8a517c58dc5846adf3241d11abed8007e8e347ee0417a8603ff879661dfb50f5d49656130146bba2c27cd487e9a45880a98b7717b9bb0d59d7c1b5fcac19b6c

data/lib/rggen/systemverilog/rtl/bit_field/type/custom.erb

@@ -4,6 +4,7 @@ rggen_bit_field #(
   .SW_READ_ACTION     (<%= sw_read_action %>),
   .SW_WRITE_ACTION    (<%= sw_write_action %>),
   .SW_WRITE_ONCE      (<%= write_once %>),
+  .HW_ACCESS          (<%= hw_access %>),
   .STORAGE            (<%= storage %>),
   .EXTERNAL_READ_DATA (<%= external_read_data %>),
   .TRIGGER            (<%= trigger %>)

data/lib/rggen/systemverilog/rtl/bit_field/type/custom.rb

@@ -82,6 +82,15 @@ RgGen.define_list_item_feature(:bit_field, :type, :custom) do
       bit_field.sw_write_once? && 1 || 0
     end
 
+    def hw_access
+      values = [
+        bit_field.hw_clear? && 1 || 0,
+        bit_field.hw_set? && 1 || 0,
+        bit_field.hw_write? && 1 || 0
+      ]
+      "3'b#{values.join}"
+    end
+
     def storage
       external_read_data? && 0 || 1
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb

@@ -2,14 +2,16 @@ rggen_bit_field #(
   .WIDTH            (<%= width %>),
   .INITIAL_VALUE    (<%= initial_value %>),
   .SW_READ_ACTION   (<%= read_action %>),
-  .SW_WRITE_ACTION  (<%= write_action %>)
+  .SW_WRITE_ACTION  (<%= write_action %>),
+  .HW_ACCESS        (3'b010),
+  .EXTERNAL_MASK    (<%= external_mask %>)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
   .o_write_trigger    (),
   .o_read_trigger     (),
-  .i_sw_write_enable  (<%= write_enable %>),
+  .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),
   .i_hw_set           (<%= set[loop_variables] %>),

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb

@@ -40,12 +40,12 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc])
       }[bit_field.type]
     end
 
-    def write_enable
-      bit_field.writable? && all_bits_1 || all_bits_0
-    end
-
     def value_out_unmasked
       (bit_field.reference? || nil) && value_unmasked[loop_variables]
     end
+
+    def external_mask
+      bit_field.reference? && 1 || 0
+    end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/rohw.erb

@@ -1,7 +1,8 @@
 rggen_bit_field #(
   .WIDTH            (<%= width %>),
   .INITIAL_VALUE    (<%= initial_value %>),
-  .SW_WRITE_ACTION  (RGGEN_WRITE_NONE)
+  .SW_WRITE_ACTION  (RGGEN_WRITE_NONE),
+  .HW_ACCESS        (3'b001)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -2,14 +2,15 @@ rggen_bit_field #(
   .WIDTH            (<%= width %>),
   .INITIAL_VALUE    (<%= initial_value %>),
   .SW_READ_ACTION   (<%= read_action %>),
-  .SW_WRITE_ACTION  (<%= write_action %>)
+  .SW_WRITE_ACTION  (<%= write_action %>),
+  .HW_ACCESS        (3'b100)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
   .o_write_trigger    (),
   .o_read_trigger     (),
-  .i_sw_write_enable  (<%= write_enable %>),
+  .i_sw_write_enable  ('1),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),
   .i_hw_set           ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb

@@ -34,9 +34,5 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos])
         wos: 'RGGEN_WRITE_SET'
       }[bit_field.type]
     end
-
-    def write_enable
-      bit_field.writable? && all_bits_1 || all_bits_0
-    end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb

@@ -1,6 +1,7 @@
 rggen_bit_field #(
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>),
+  .HW_ACCESS      (3'b100),
   .HW_CLEAR_WIDTH (1)
 ) u_bit_field (
   .i_clk              (<%= clock %>),

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb

@@ -1,6 +1,7 @@
 rggen_bit_field #(
   .WIDTH                    (<%= width %>),
   .INITIAL_VALUE            (<%= initial_value %>),
+  .SW_WRITE_CONTROL         (1),
   .SW_WRITE_ENABLE_POLARITY (<%= polarity %>)
 ) u_bit_field (
   .i_clk              (<%= clock %>),

data/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.erb

@@ -1,6 +1,7 @@
 rggen_bit_field #(
   .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .HW_ACCESS      (3'b001)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb

@@ -1,6 +1,7 @@
 rggen_bit_field #(
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>),
+  .HW_ACCESS      (3'b010),
   .HW_SET_WIDTH   (1)
 ) u_bit_field (
   .i_clk              (<%= clock %>),

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb

@@ -1,11 +1,13 @@
 `ifndef rggen_connect_bit_field_if
   `define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \
-  assign  FIF.valid                 = RIF.valid; \
-  assign  FIF.read_mask             = RIF.read_mask[LSB+:WIDTH]; \
-  assign  FIF.write_mask            = RIF.write_mask[LSB+:WIDTH]; \
-  assign  FIF.write_data            = RIF.write_data[LSB+:WIDTH]; \
-  assign  RIF.read_data[LSB+:WIDTH] = FIF.read_data; \
-  assign  RIF.value[LSB+:WIDTH]     = FIF.value;
+  always_comb begin \
+    FIF.write_valid           = RIF.write_valid; \
+    FIF.read_valid            = RIF.read_valid; \
+    FIF.mask                  = RIF.mask[LSB+:WIDTH]; \
+    FIF.write_data            = RIF.write_data[LSB+:WIDTH]; \
+    RIF.read_data[LSB+:WIDTH] = FIF.read_data; \
+    RIF.value[LSB+:WIDTH]     = FIF.value; \
+  end
 `endif
 `ifndef rggen_tie_off_unused_signals
   `define rggen_tie_off_unused_signals(WIDTH, VALID_BITS, RIF) \
@@ -13,8 +15,10 @@
     genvar  __i; \
     for (__i = 0;__i < WIDTH;++__i) begin : g \
       if ((((VALID_BITS) >> __i) % 2) == 0) begin : g \
-        assign  RIF.read_data[__i]  = 1'b0; \
-        assign  RIF.value[__i]      = 1'b0; \
+        always_comb begin \
+          RIF.read_data[__i]  = '0; \
+          RIF.value[__i]      = '0; \
+        end \
       end \
     end \
   end

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.35.0'
+    VERSION = '0.35.1'
   end
 end

metadata

@@ -1,13 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.35.0
+  version: 0.35.1
 platform: ruby
 authors:
 - Taichi Ishitani
 bindir: bin
 cert_chain: []
-date: 2025-02-19 00:00:00.000000000 Z
+date: 2025-06-01 00:00:00.000000000 Z
 dependencies: []
 description: 'SystemVerilog RTL and UVM RAL model generators for RgGen.
 
@@ -159,5 +159,5 @@ required_rubygems_version: !ruby/object:Gem::Requirement
 requirements: []
 rubygems_version: 3.6.2
 specification_version: 4
-summary: rggen-systemverilog-0.35.0
+summary: rggen-systemverilog-0.35.1
 test_files: []