rggen-systemverilog 0.33.0 → 0.33.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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-  data.tar.gz: cc255cc91600d54a8481b733fc80350b9b43a7d5f3dd9ea39cc4679bd9c1b6ab
+  metadata.gz: a3d95e17a462a9401886ea4a6923921ad4ba9aa698c2bd9133f7b513110c120b
+  data.tar.gz: 4d80681f90d4cb38ca782821fe9820fa6e9c4cbcc3b723c63a1ec75d87c2d35d
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+  metadata.gz: 38bf92bf7e6f0d27cb99ed6a6d2e3753f3bf60ff199fc876e8f99875bbdbf0da665b5f2c0dae40c44510acee6555487c56a1381ac3264f00ce6ae4f2731e34a4
+  data.tar.gz: d7f396a29d716c6f854bbeb2fb5c331eb67ffb85143f764b9e62a3c8f89c388367a56ef54c6a31311129229859f37452b5bee51457a76db4272360898f744ff7

data/lib/rggen/systemverilog/rtl/indirect_index.rb

@@ -8,26 +8,55 @@ module RgGen
 
         def index_fields
           @index_fields ||=
-            register.collect_index_fields(register_block.bit_fields)
+            register
+              .collect_index_fields(register_block.bit_fields)
         end
 
-        def index_width
-          @index_width ||= index_fields.sum(&:width)
+        def index_match_width
+          index_fields.size
         end
 
         def index_values
+          @index_values ||= collect_index_values
+        end
+
+        def collect_index_values
           loop_variables = register.local_loop_variables
           register.index_entries.zip(index_fields).map do |entry, field|
             if entry.array_index?
-              loop_variables.shift[0, field.width]
+              array_index_value(loop_variables.shift, field.width)
             else
-              hex(entry.value, field.width)
+              fixed_index_value(entry.value, field.width)
             end
           end
         end
 
-        def indirect_index_assignment
-          assign(indirect_index, concat(index_fields.map(&:value)))
+        def array_index_value(value, width)
+          "#{width}'(#{value})"
+        end
+
+        def fixed_index_value(value, width)
+          hex(value, width)
+        end
+
+        def indirect_index_matches(code)
+          index_fields.each_with_index do |field, i|
+            rhs = index_match_rhs(i)
+            lhs = index_match_lhs(field.value, index_values[i])
+            code << assign(rhs, lhs) << nl
+          end
+        end
+
+        def index_match_rhs(index)
+          if index_match_width == 1
+            indirect_match
+          else
+            indirect_match[index]
+          end
+        end
+
+        def index_match_lhs(field, value)
+          "#{field} == #{value}"
         end
       end
     end

data/lib/rggen/systemverilog/rtl/register/type/indirect.erb

@@ -6,12 +6,11 @@ rggen_indirect_register #(
   .BUS_WIDTH            (<%= bus_width %>),
   .DATA_WIDTH           (<%= width %>),
   .VALUE_WIDTH          (<%= value_width %>),
-  .INDIRECT_INDEX_WIDTH (<%= index_width %>),
-  .INDIRECT_INDEX_VALUE (<%= concat(index_values) %>)
+  .INDIRECT_MATCH_WIDTH (<%= index_match_width %>)
 ) u_register (
   .i_clk            (<%= register_block.clock %>),
   .i_rst_n          (<%= register_block.reset %>),
   .register_if      (<%= register_if %>),
-  .i_indirect_index (<%= indirect_index %>),
+  .i_indirect_match (<%= indirect_match %>),
   .bit_field_if     (<%= bit_field_if %>)
 );

data/lib/rggen/systemverilog/rtl/register/type/indirect.rb

@@ -5,11 +5,11 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
     include RgGen::SystemVerilog::RTL::IndirectIndex
 
     build do
-      logic :indirect_index, { width: index_width }
+      logic :indirect_match, { width: index_match_width }
     end
 
     main_code :register do |code|
-      code << indirect_index_assignment << nl
+      indirect_index_matches(code)
       code << process_template
     end
   end

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.33.0'
+    VERSION = '0.33.1'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.33.0
+  version: 0.33.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2024-01-22 00:00:00.000000000 Z
+date: 2024-11-28 00:00:00.000000000 Z
 dependencies: []
 description: 'SystemVerilog RTL and UVM RAL model generators for RgGen.
 
@@ -154,8 +154,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.5.3
+rubygems_version: 3.5.16
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.33.0
+summary: rggen-systemverilog-0.33.1
 test_files: []