rggen-systemverilog 0.32.0 → 0.33.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: c295b2c383ee9a080cf33b8faf85f81ed3946cf607be733a1a0ff44d43fdf456
-  data.tar.gz: a38e7790669fe49a736076383a627f87e6468e38635376f2a07e79ca1a372884
+  metadata.gz: a3d95e17a462a9401886ea4a6923921ad4ba9aa698c2bd9133f7b513110c120b
+  data.tar.gz: 4d80681f90d4cb38ca782821fe9820fa6e9c4cbcc3b723c63a1ec75d87c2d35d
 SHA512:
-  metadata.gz: '0876b350261500e1c6f9ca6614713c3a251c7c779d656150301972b1be9f4b7defd044df1a37cecd1d70860fa92a09adbcad4abad0654386f2c7416387c6710a'
-  data.tar.gz: 7dbd42dcfa9fc6285a9d0790f92c9543007b3d472a57f2ce8f06e7fb967bff4094a55ff0ee8eb7cbcf2d050b496bbf30dbbed41f08714dc4a7976adf820b9314
+  metadata.gz: 38bf92bf7e6f0d27cb99ed6a6d2e3753f3bf60ff199fc876e8f99875bbdbf0da665b5f2c0dae40c44510acee6555487c56a1381ac3264f00ce6ae4f2731e34a4
+  data.tar.gz: d7f396a29d716c6f854bbeb2fb5c331eb67ffb85143f764b9e62a3c8f89c388367a56ef54c6a31311129229859f37452b5bee51457a76db4272360898f744ff7

data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019-2023 Taichi Ishitani
+Copyright (c) 2019-2024 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -34,7 +34,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 
 ## Copyright & License
 
-Copyright © 2019-2023 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2019-2024 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/systemverilog/ral/bit_field/type/rof_rohw.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rof, :rohw]) do
+  sv_ral { access 'RO' }
+end

data/lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw_rws.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rwhw, :rws]) do
+  sv_ral { access 'RW' }
+end

data/lib/rggen/systemverilog/ral.rb

@@ -23,11 +23,11 @@ RgGen.setup_plugin :'rggen-sv-ral' do |plugin|
     'ral/register/type/indirect',
     'ral/bit_field/type',
     'ral/bit_field/type/custom',
-    'ral/bit_field/type/rof_rol',
+    'ral/bit_field/type/rof_rohw',
     'ral/bit_field/type/rotrg_rwtrg_wotrg',
     'ral/bit_field/type/row0trg_row1trg_w0trg_w1trg',
     'ral/bit_field/type/rowo_rowotrg',
-    'ral/bit_field/type/rwc_rws',
+    'ral/bit_field/type/rwc_rwhw_rws',
     'ral/bit_field/type/rwe_rwl'
   ]
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/{rol.erb → rohw.erb}

@@ -9,7 +9,7 @@ rggen_bit_field #(
   .o_write_trigger    (),
   .o_read_trigger     (),
   .i_sw_write_enable  ('1),
-  .i_hw_write_enable  (<%= latch_signal %>),
+  .i_hw_write_enable  (<%= valid_signal %>),
   .i_hw_write_data    (<%= value_in[loop_variables] %>),
   .i_hw_set           ('0),
   .i_hw_clear         ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/{rol.rb → rohw.rb}

@@ -1,11 +1,11 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, :rol) do
+RgGen.define_list_item_feature(:bit_field, :type, :rohw) do
   sv_rtl do
     build do
       unless bit_field.reference?
-        input :latch, {
-          name: "i_#{full_name}_latch", width: 1,
+        input :valid, {
+          name: "i_#{full_name}_valid", width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
@@ -23,8 +23,8 @@ RgGen.define_list_item_feature(:bit_field, :type, :rol) do
 
     private
 
-    def latch_signal
-      reference_bit_field || latch[loop_variables]
+    def valid_signal
+      reference_bit_field || valid[loop_variables]
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.erb

@@ -0,0 +1,19 @@
+rggen_bit_field #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  (<%= valid_signal %>),
+  .i_hw_write_data    (<%= value_in[loop_variables] %>),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.rb

@@ -0,0 +1,30 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rwhw) do
+  sv_rtl do
+    build do
+      unless bit_field.reference?
+        input :valid, {
+          name: "i_#{full_name}_valid", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      input :value_in, {
+        name: "i_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def valid_signal
+      reference_bit_field || valid[loop_variables]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb

@@ -1,6 +1,7 @@
 rggen_bit_field #(
   .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .HW_SET_WIDTH   (1)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
@@ -8,9 +9,9 @@ rggen_bit_field #(
   .o_write_trigger    (),
   .o_read_trigger     (),
   .i_sw_write_enable  ('1),
-  .i_hw_write_enable  (<%= set_signal %>),
-  .i_hw_write_data    (<%= value_in[loop_variables] %>),
-  .i_hw_set           ('0),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           (<%= set_signal %>),
   .i_hw_clear         ('0),
   .i_value            ('0),
   .i_mask             ('1),

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb

@@ -9,10 +9,6 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
           array_size: array_size, array_format: array_port_format
         }
       end
-      input :value_in, {
-        name: "i_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
-      }
       output :value_out, {
         name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format

data/lib/rggen/systemverilog/rtl/indirect_index.rb

@@ -8,26 +8,55 @@ module RgGen
 
         def index_fields
           @index_fields ||=
-            register.collect_index_fields(register_block.bit_fields)
+            register
+              .collect_index_fields(register_block.bit_fields)
         end
 
-        def index_width
-          @index_width ||= index_fields.sum(&:width)
+        def index_match_width
+          index_fields.size
         end
 
         def index_values
+          @index_values ||= collect_index_values
+        end
+
+        def collect_index_values
           loop_variables = register.local_loop_variables
           register.index_entries.zip(index_fields).map do |entry, field|
             if entry.array_index?
-              loop_variables.shift[0, field.width]
+              array_index_value(loop_variables.shift, field.width)
             else
-              hex(entry.value, field.width)
+              fixed_index_value(entry.value, field.width)
             end
           end
         end
 
-        def indirect_index_assignment
-          assign(indirect_index, concat(index_fields.map(&:value)))
+        def array_index_value(value, width)
+          "#{width}'(#{value})"
+        end
+
+        def fixed_index_value(value, width)
+          hex(value, width)
+        end
+
+        def indirect_index_matches(code)
+          index_fields.each_with_index do |field, i|
+            rhs = index_match_rhs(i)
+            lhs = index_match_lhs(field.value, index_values[i])
+            code << assign(rhs, lhs) << nl
+          end
+        end
+
+        def index_match_rhs(index)
+          if index_match_width == 1
+            indirect_match
+          else
+            indirect_match[index]
+          end
+        end
+
+        def index_match_lhs(field, value)
+          "#{field} == #{value}"
         end
       end
     end

data/lib/rggen/systemverilog/rtl/register/type/indirect.erb

@@ -6,12 +6,11 @@ rggen_indirect_register #(
   .BUS_WIDTH            (<%= bus_width %>),
   .DATA_WIDTH           (<%= width %>),
   .VALUE_WIDTH          (<%= value_width %>),
-  .INDIRECT_INDEX_WIDTH (<%= index_width %>),
-  .INDIRECT_INDEX_VALUE (<%= concat(index_values) %>)
+  .INDIRECT_MATCH_WIDTH (<%= index_match_width %>)
 ) u_register (
   .i_clk            (<%= register_block.clock %>),
   .i_rst_n          (<%= register_block.reset %>),
   .register_if      (<%= register_if %>),
-  .i_indirect_index (<%= indirect_index %>),
+  .i_indirect_match (<%= indirect_match %>),
   .bit_field_if     (<%= bit_field_if %>)
 );

data/lib/rggen/systemverilog/rtl/register/type/indirect.rb

@@ -5,11 +5,11 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
     include RgGen::SystemVerilog::RTL::IndirectIndex
 
     build do
-      logic :indirect_index, { width: index_width }
+      logic :indirect_match, { width: index_match_width }
     end
 
     main_code :register do |code|
-      code << indirect_index_assignment << nl
+      indirect_index_matches(code)
       code << process_template
     end
   end

data/lib/rggen/systemverilog/rtl.rb

@@ -38,13 +38,14 @@ RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
     'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
     'rtl/bit_field/type/ro_rotrg',
     'rtl/bit_field/type/rof',
-    'rtl/bit_field/type/rol',
+    'rtl/bit_field/type/rohw',
     'rtl/bit_field/type/row0trg_row1trg',
     'rtl/bit_field/type/rowo_rowotrg',
     'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
     'rtl/bit_field/type/rw_rwtrg_w1',
     'rtl/bit_field/type/rwc',
     'rtl/bit_field/type/rwe_rwl',
+    'rtl/bit_field/type/rwhw',
     'rtl/bit_field/type/rws',
     'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
     'rtl/bit_field/type/w0t_w1t',

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.32.0'
+    VERSION = '0.33.1'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.32.0
+  version: 0.33.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2023-12-28 00:00:00.000000000 Z
+date: 2024-11-28 00:00:00.000000000 Z
 dependencies: []
 description: 'SystemVerilog RTL and UVM RAL model generators for RgGen.
 
@@ -42,11 +42,11 @@ files:
 - lib/rggen/systemverilog/ral.rb
 - lib/rggen/systemverilog/ral/bit_field/type.rb
 - lib/rggen/systemverilog/ral/bit_field/type/custom.rb
-- lib/rggen/systemverilog/ral/bit_field/type/rof_rol.rb
+- lib/rggen/systemverilog/ral/bit_field/type/rof_rohw.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb
 - lib/rggen/systemverilog/ral/bit_field/type/row0trg_row1trg_w0trg_w1trg.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb
-- lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb
+- lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw_rws.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb
 - lib/rggen/systemverilog/ral/feature.rb
 - lib/rggen/systemverilog/ral/register/type.rb
@@ -71,8 +71,8 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rol.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rol.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rohw.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rohw.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb
@@ -85,6 +85,8 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rwhw.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rwhw.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
@@ -152,8 +154,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.5.3
+rubygems_version: 3.5.16
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.32.0
+summary: rggen-systemverilog-0.33.1
 test_files: []

data/lib/rggen/systemverilog/ral/bit_field/type/rof_rol.rb

@@ -1,5 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rof, :rol]) do
-  sv_ral { access 'RO' }
-end

data/lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb

@@ -1,5 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rws]) do
-  sv_ral { access 'RW' }
-end