rggen-systemverilog 0.30.2 → 0.32.0
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- checksums.yaml +4 -4
- data/README.md +0 -1
- data/lib/rggen/systemverilog/common/utility/function_definition.rb +2 -3
- data/lib/rggen/systemverilog/rtl/register/type/external.erb +1 -0
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +5 -2
- data/lib/rggen/systemverilog/rtl/register/type/rw.erb +14 -0
- data/lib/rggen/systemverilog/rtl/register/type/rw.rb +7 -0
- data/lib/rggen/systemverilog/rtl.rb +1 -0
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +8 -20
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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1
1
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---
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2
2
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SHA256:
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3
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-
metadata.gz:
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4
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-
data.tar.gz:
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3
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+
metadata.gz: c295b2c383ee9a080cf33b8faf85f81ed3946cf607be733a1a0ff44d43fdf456
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4
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+
data.tar.gz: a38e7790669fe49a736076383a627f87e6468e38635376f2a07e79ca1a372884
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5
5
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SHA512:
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6
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-
metadata.gz:
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7
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-
data.tar.gz:
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6
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+
metadata.gz: '0876b350261500e1c6f9ca6614713c3a251c7c779d656150301972b1be9f4b7defd044df1a37cecd1d70860fa92a09adbcad4abad0654386f2c7416387c6710a'
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7
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+
data.tar.gz: 7dbd42dcfa9fc6285a9d0790f92c9543007b3d472a57f2ce8f06e7fb967bff4094a55ff0ee8eb7cbcf2d050b496bbf30dbbed41f08714dc4a7976adf820b9314
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data/README.md
CHANGED
@@ -2,7 +2,6 @@
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2
2
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[![CI](https://github.com/rggen/rggen-systemverilog/workflows/CI/badge.svg)](https://github.com/rggen/rggen-systemverilog/actions?query=workflow%3ACI)
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3
3
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[![Maintainability](https://api.codeclimate.com/v1/badges/88086c5be538a1564a35/maintainability)](https://codeclimate.com/github/rggen/rggen-systemverilog/maintainability)
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4
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[![codecov](https://codecov.io/gh/rggen/rggen-systemverilog/branch/master/graph/badge.svg)](https://codecov.io/gh/rggen/rggen-systemverilog)
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5
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-
[![Quality Gate Status](https://sonarcloud.io/api/project_badges/measure?project=rggen_rggen-systemverilog&metric=alert_status)](https://sonarcloud.io/dashboard?id=rggen_rggen-systemverilog)
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6
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[![Gitter](https://badges.gitter.im/rggen/rggen.svg)](https://gitter.im/rggen/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
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7
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8
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# RgGen::SystemVerilog
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@@ -10,9 +10,8 @@ module RgGen
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10
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define_attribute :arguments
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11
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12
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def return_type(**attributes)
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13
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-
attributes.
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14
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-
@return_type = DataObject.new(:variable, **attributes)
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15
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-
)
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13
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+
attributes.empty? ||
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14
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(@return_type = DataObject.new(:variable, **attributes))
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16
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@return_type
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16
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end
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18
17
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@@ -3,10 +3,13 @@
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3
3
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RgGen.define_list_item_feature(:register, :type, :external) do
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4
4
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sv_rtl do
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5
5
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build do
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6
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+
parameter :strobe_width, {
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7
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+
name: "#{register.name}_strobe_width".upcase,
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8
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+
data_type: :int, default: configuration.bus_width / 8
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9
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+
}
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6
10
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interface_port :bus_if, {
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7
11
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name: "#{register.name}_bus_if",
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8
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-
interface_type: 'rggen_bus_if',
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9
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-
modport: 'master'
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12
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+
interface_type: 'rggen_bus_if', modport: 'master'
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10
13
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}
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14
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end
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12
15
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@@ -0,0 +1,14 @@
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1
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+
rggen_default_register #(
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2
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.READABLE (1),
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3
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.WRITABLE (1),
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4
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+
.ADDRESS_WIDTH (<%= address_width %>),
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5
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+
.OFFSET_ADDRESS (<%= offset_address %>),
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6
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+
.BUS_WIDTH (<%= bus_width %>),
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7
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+
.DATA_WIDTH (<%= width %>),
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8
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+
.VALUE_WIDTH (<%= value_width %>)
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9
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+
) u_register (
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10
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+
.i_clk (<%= register_block.clock %>),
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11
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+
.i_rst_n (<%= register_block.reset %>),
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12
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+
.register_if (<%= register_if %>),
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13
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+
.bit_field_if (<%= bit_field_if %>)
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14
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+
);
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metadata
CHANGED
@@ -1,29 +1,15 @@
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1
1
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--- !ruby/object:Gem::Specification
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2
2
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name: rggen-systemverilog
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3
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version: !ruby/object:Gem::Version
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4
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-
version: 0.
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4
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+
version: 0.32.0
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platform: ruby
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authors:
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- Taichi Ishitani
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autorequire:
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bindir: bin
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cert_chain: []
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date: 2023-
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dependencies:
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-
- !ruby/object:Gem::Dependency
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name: bundler
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requirement: !ruby/object:Gem::Requirement
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requirements:
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-
- - ">="
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-
- !ruby/object:Gem::Version
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version: '0'
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type: :development
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prerelease: false
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22
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version_requirements: !ruby/object:Gem::Requirement
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-
requirements:
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-
- - ">="
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25
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-
- !ruby/object:Gem::Version
|
26
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-
version: '0'
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11
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+
date: 2023-12-28 00:00:00.000000000 Z
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12
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+
dependencies: []
|
27
13
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description: 'SystemVerilog RTL and UVM RAL model generators for RgGen.
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28
14
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29
15
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'
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@@ -123,6 +109,8 @@ files:
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123
109
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- lib/rggen/systemverilog/rtl/register/type/external.rb
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124
110
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- lib/rggen/systemverilog/rtl/register/type/indirect.erb
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125
111
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- lib/rggen/systemverilog/rtl/register/type/indirect.rb
|
112
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+
- lib/rggen/systemverilog/rtl/register/type/rw.erb
|
113
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+
- lib/rggen/systemverilog/rtl/register/type/rw.rb
|
126
114
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- lib/rggen/systemverilog/rtl/register_block/protocol.rb
|
127
115
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- lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb
|
128
116
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- lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb
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@@ -157,15 +145,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
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157
145
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requirements:
|
158
146
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- - ">="
|
159
147
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- !ruby/object:Gem::Version
|
160
|
-
version: '
|
148
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+
version: '3.0'
|
161
149
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required_rubygems_version: !ruby/object:Gem::Requirement
|
162
150
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requirements:
|
163
151
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- - ">="
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164
152
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- !ruby/object:Gem::Version
|
165
153
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version: '0'
|
166
154
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requirements: []
|
167
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-
rubygems_version: 3.
|
155
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+
rubygems_version: 3.5.3
|
168
156
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signing_key:
|
169
157
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specification_version: 4
|
170
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-
summary: rggen-systemverilog-0.
|
158
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+
summary: rggen-systemverilog-0.32.0
|
171
159
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test_files: []
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