rggen-systemverilog 0.30.1 → 0.31.0

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checksums.yaml CHANGED
@@ -1,7 +1,7 @@
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  SHA256:
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  SHA512:
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+ data.tar.gz: 2718107de54e94abf23b58348565a4d6b0ef6f5aded9468fe47dd3d294af805a829756dcbbcb3b5d98025b45b75da6a28bf415337f1ca11c84d480fcb7887886
@@ -2,6 +2,7 @@ rggen_external_register #(
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  .ADDRESS_WIDTH (<%= address_width %>),
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  .BUS_WIDTH (<%= bus_width %>),
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  .VALUE_WIDTH (<%= value_width %>),
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+ .STROBE_WIDTH (<%= strobe_width %>),
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  .START_ADDRESS (<%= start_address %>),
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  .BYTE_SIZE (<%= byte_size %>)
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  ) u_register (
@@ -3,10 +3,13 @@
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  RgGen.define_list_item_feature(:register, :type, :external) do
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  sv_rtl do
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  build do
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+ parameter :strobe_width, {
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+ name: "#{register.name}_strobe_width".upcase,
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+ data_type: :int, default: configuration.bus_width / 8
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+ }
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  interface_port :bus_if, {
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  name: "#{register.name}_bus_if",
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- interface_type: 'rggen_bus_if',
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- modport: 'master'
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+ interface_type: 'rggen_bus_if', modport: 'master'
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  }
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  end
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@@ -0,0 +1,14 @@
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+ rggen_default_register #(
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+ .READABLE (1),
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+ .WRITABLE (1),
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+ .ADDRESS_WIDTH (<%= address_width %>),
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+ .OFFSET_ADDRESS (<%= offset_address %>),
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+ .BUS_WIDTH (<%= bus_width %>),
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+ .DATA_WIDTH (<%= width %>),
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+ .VALUE_WIDTH (<%= value_width %>)
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+ ) u_register (
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+ .i_clk (<%= register_block.clock %>),
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+ .i_rst_n (<%= register_block.reset %>),
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+ .register_if (<%= register_if %>),
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+ .bit_field_if (<%= bit_field_if %>)
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+ );
@@ -0,0 +1,7 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_list_item_feature(:register, :type, :rw) do
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+ sv_rtl do
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+ main_code :register, from_template: true
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+ end
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+ end
@@ -5,7 +5,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
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  verify(:component) do
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  error_condition { ![32, 64].include?(configuration.bus_width) }
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  message do
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- 'bus width eigher 32 bit or 64 bit is only supported: ' \
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+ 'bus width either 32 bit or 64 bit is only supported: ' \
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  "#{configuration.bus_width}"
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  end
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  end
@@ -31,6 +31,7 @@ RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
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  'rtl/register/type',
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  'rtl/register/type/external',
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  'rtl/register/type/indirect',
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+ 'rtl/register/type/rw',
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  'rtl/bit_field/sv_rtl_top',
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  'rtl/bit_field/type',
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  'rtl/bit_field/type/custom',
@@ -2,6 +2,6 @@
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  module RgGen
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  module SystemVerilog
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- VERSION = '0.30.1'
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+ VERSION = '0.31.0'
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  end
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  end
metadata CHANGED
@@ -1,14 +1,14 @@
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  --- !ruby/object:Gem::Specification
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  name: rggen-systemverilog
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  version: !ruby/object:Gem::Version
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- version: 0.30.1
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+ version: 0.31.0
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  platform: ruby
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  authors:
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  - Taichi Ishitani
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2023-06-09 00:00:00.000000000 Z
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+ date: 2023-09-12 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: bundler
@@ -123,6 +123,8 @@ files:
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  - lib/rggen/systemverilog/rtl/register/type/external.rb
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  - lib/rggen/systemverilog/rtl/register/type/indirect.erb
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  - lib/rggen/systemverilog/rtl/register/type/indirect.rb
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+ - lib/rggen/systemverilog/rtl/register/type/rw.erb
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+ - lib/rggen/systemverilog/rtl/register/type/rw.rb
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  - lib/rggen/systemverilog/rtl/register_block/protocol.rb
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  - lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb
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  - lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb
@@ -164,8 +166,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
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  - !ruby/object:Gem::Version
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  version: '0'
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  requirements: []
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- rubygems_version: 3.4.10
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+ rubygems_version: 3.4.17
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  signing_key:
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  specification_version: 4
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- summary: rggen-systemverilog-0.30.1
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+ summary: rggen-systemverilog-0.31.0
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  test_files: []