rggen-systemverilog 0.30.1 → 0.31.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/lib/rggen/systemverilog/rtl/register/type/external.erb +1 -0
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +5 -2
- data/lib/rggen/systemverilog/rtl/register/type/rw.erb +14 -0
- data/lib/rggen/systemverilog/rtl/register/type/rw.rb +7 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +1 -1
- data/lib/rggen/systemverilog/rtl.rb +1 -0
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +6 -4
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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1
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---
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SHA256:
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3
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-
metadata.gz:
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4
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-
data.tar.gz:
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3
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+
metadata.gz: 58a725dee672c4e2153845b860d7bd846593dc993d37b4dc521a34647679d641
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4
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+
data.tar.gz: 5641e7e6c48c1ad49b82942fca87751abf01bcdee820d791e76c4e2669d9445b
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5
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SHA512:
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6
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-
metadata.gz:
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7
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-
data.tar.gz:
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6
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+
metadata.gz: 6dceef1d3d02176039c1894d88cd8b138a4db62fd1591c4afe233a59f2acdda80f7daa37328232ae71f4f1bfa171645f990e54c66c2aa0764d681e4276a8c0dc
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7
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+
data.tar.gz: 2718107de54e94abf23b58348565a4d6b0ef6f5aded9468fe47dd3d294af805a829756dcbbcb3b5d98025b45b75da6a28bf415337f1ca11c84d480fcb7887886
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@@ -3,10 +3,13 @@
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RgGen.define_list_item_feature(:register, :type, :external) do
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sv_rtl do
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build do
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parameter :strobe_width, {
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name: "#{register.name}_strobe_width".upcase,
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data_type: :int, default: configuration.bus_width / 8
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}
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interface_port :bus_if, {
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name: "#{register.name}_bus_if",
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-
interface_type: 'rggen_bus_if',
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-
modport: 'master'
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+
interface_type: 'rggen_bus_if', modport: 'master'
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}
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end
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@@ -0,0 +1,14 @@
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1
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+
rggen_default_register #(
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.READABLE (1),
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.WRITABLE (1),
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.ADDRESS_WIDTH (<%= address_width %>),
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.OFFSET_ADDRESS (<%= offset_address %>),
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.BUS_WIDTH (<%= bus_width %>),
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.DATA_WIDTH (<%= width %>),
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.VALUE_WIDTH (<%= value_width %>)
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) u_register (
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.i_clk (<%= register_block.clock %>),
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.i_rst_n (<%= register_block.reset %>),
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.register_if (<%= register_if %>),
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.bit_field_if (<%= bit_field_if %>)
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);
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@@ -5,7 +5,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
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verify(:component) do
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error_condition { ![32, 64].include?(configuration.bus_width) }
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message do
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-
'bus width
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'bus width either 32 bit or 64 bit is only supported: ' \
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"#{configuration.bus_width}"
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end
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end
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metadata
CHANGED
@@ -1,14 +1,14 @@
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--- !ruby/object:Gem::Specification
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name: rggen-systemverilog
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version: !ruby/object:Gem::Version
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-
version: 0.
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version: 0.31.0
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platform: ruby
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authors:
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- Taichi Ishitani
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autorequire:
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bindir: bin
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cert_chain: []
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-
date: 2023-
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+
date: 2023-09-12 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: bundler
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@@ -123,6 +123,8 @@ files:
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- lib/rggen/systemverilog/rtl/register/type/external.rb
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- lib/rggen/systemverilog/rtl/register/type/indirect.erb
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- lib/rggen/systemverilog/rtl/register/type/indirect.rb
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+
- lib/rggen/systemverilog/rtl/register/type/rw.erb
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+
- lib/rggen/systemverilog/rtl/register/type/rw.rb
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- lib/rggen/systemverilog/rtl/register_block/protocol.rb
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- lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb
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- lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb
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@@ -164,8 +166,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
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- !ruby/object:Gem::Version
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version: '0'
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requirements: []
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rubygems_version: 3.4.
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rubygems_version: 3.4.17
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signing_key:
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specification_version: 4
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-
summary: rggen-systemverilog-0.
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+
summary: rggen-systemverilog-0.31.0
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test_files: []
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