rggen-systemverilog 0.30.0 → 0.30.2

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checksums.yaml CHANGED
@@ -1,7 +1,7 @@
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@@ -87,6 +87,10 @@ module RgGen
87
87
  [width, bit_length].max
88
88
  end
89
89
 
90
+ def width_cast(expression, width)
91
+ "#{width}'(#{expression})"
92
+ end
93
+
90
94
  def argument(name, attribute = {})
91
95
  DataObject.new(:argument, attribute.merge(name: name)).declaration
92
96
  end
@@ -4,7 +4,8 @@ rggen_default_register #(
4
4
  .ADDRESS_WIDTH (<%= address_width %>),
5
5
  .OFFSET_ADDRESS (<%= offset_address %>),
6
6
  .BUS_WIDTH (<%= bus_width %>),
7
- .DATA_WIDTH (<%= width %>)
7
+ .DATA_WIDTH (<%= width %>),
8
+ .VALUE_WIDTH (<%= value_width %>)
8
9
  ) u_register (
9
10
  .i_clk (<%= register_block.clock %>),
10
11
  .i_rst_n (<%= register_block.reset %>),
@@ -1,8 +1,9 @@
1
1
  rggen_external_register #(
2
2
  .ADDRESS_WIDTH (<%= address_width %>),
3
3
  .BUS_WIDTH (<%= bus_width %>),
4
+ .VALUE_WIDTH (<%= value_width %>),
4
5
  .START_ADDRESS (<%= start_address %>),
5
- .END_ADDRESS (<%= end_address %>)
6
+ .BYTE_SIZE (<%= byte_size %>)
6
7
  ) u_register (
7
8
  .i_clk (<%= register_block.clock %>),
8
9
  .i_rst_n (<%= register_block.reset %>),
@@ -14,16 +14,12 @@ RgGen.define_list_item_feature(:register, :type, :external) do
14
14
 
15
15
  private
16
16
 
17
- def byte_width
18
- configuration.byte_width
19
- end
20
-
21
17
  def start_address
22
18
  hex(register.address_range.begin, address_width)
23
19
  end
24
20
 
25
- def end_address
26
- hex(register.address_range.last, address_width)
21
+ def byte_size
22
+ register.total_byte_size
27
23
  end
28
24
  end
29
25
  end
@@ -5,6 +5,7 @@ rggen_indirect_register #(
5
5
  .OFFSET_ADDRESS (<%= offset_address %>),
6
6
  .BUS_WIDTH (<%= bus_width %>),
7
7
  .DATA_WIDTH (<%= width %>),
8
+ .VALUE_WIDTH (<%= value_width %>),
8
9
  .INDIRECT_INDEX_WIDTH (<%= index_width %>),
9
10
  .INDIRECT_INDEX_VALUE (<%= concat(index_values) %>)
10
11
  ) u_register (
@@ -5,7 +5,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
5
5
  verify(:component) do
6
6
  error_condition { ![32, 64].include?(configuration.bus_width) }
7
7
  message do
8
- 'bus width eigher 32 bit or 64 bit is only supported: ' \
8
+ 'bus width either 32 bit or 64 bit is only supported: ' \
9
9
  "#{configuration.bus_width}"
10
10
  end
11
11
  end
@@ -26,11 +26,5 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
26
26
  end
27
27
 
28
28
  main_code :register_block, from_template: true
29
-
30
- private
31
-
32
- def id_port_width
33
- "((#{id_width}>0)?#{id_width}:1)"
34
- end
35
29
  end
36
30
  end
@@ -17,12 +17,6 @@ RgGen.define_list_feature(:register_block, :protocol) do
17
17
  def feature_registries
18
18
  @feature_registries ||= []
19
19
  end
20
-
21
- def collect_available_protocols(registry)
22
- registry
23
- .enabled_features(:protocol)
24
- .select { |protocol| registry.feature?(:protocol, protocol) }
25
- end
26
20
  end
27
21
 
28
22
  configuration do
@@ -100,10 +94,6 @@ RgGen.define_list_feature(:register_block, :protocol) do
100
94
  configuration.bus_width
101
95
  end
102
96
 
103
- def byte_width
104
- configuration.byte_width
105
- end
106
-
107
97
  def local_address_width
108
98
  register_block.local_address_width
109
99
  end
@@ -12,7 +12,7 @@
12
12
  if (1) begin : __g_tie_off \
13
13
  genvar __i; \
14
14
  for (__i = 0;__i < WIDTH;++__i) begin : g \
15
- if (!(((VALID_BITS) >> __i) & 1'b1)) begin : g \
15
+ if ((((VALID_BITS) >> __i) % 2) == 0) begin : g \
16
16
  assign RIF.read_data[__i] = 1'b0; \
17
17
  assign RIF.value[__i] = 1'b0; \
18
18
  end \
@@ -3,6 +3,7 @@
3
3
  RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
4
4
  sv_rtl do
5
5
  export :total_registers
6
+ export :value_width
6
7
 
7
8
  build do
8
9
  input :clock, { name: 'i_clk', width: 1 }
@@ -19,7 +20,11 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
19
20
  end
20
21
 
21
22
  def total_registers
22
- register_block.files_and_registers.sum(&:count)
23
+ @total_registers ||= register_block.files_and_registers.sum(&:count)
24
+ end
25
+
26
+ def value_width
27
+ @value_width ||= register_block.registers.map(&:width).max
23
28
  end
24
29
 
25
30
  private
@@ -32,10 +37,6 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
32
37
  configuration.bus_width
33
38
  end
34
39
 
35
- def value_width
36
- register_block.registers.map(&:width).max
37
- end
38
-
39
40
  def body_code(code)
40
41
  macro_definition(code)
41
42
  sv_module_definition(code)
@@ -16,10 +16,18 @@ module RgGen
16
16
  register.writable? && 1 || 0
17
17
  end
18
18
 
19
+ def width
20
+ register.width
21
+ end
22
+
19
23
  def bus_width
20
24
  configuration.bus_width
21
25
  end
22
26
 
27
+ def value_width
28
+ register_block.value_width
29
+ end
30
+
23
31
  def address_width
24
32
  register_block.local_address_width
25
33
  end
@@ -62,16 +70,15 @@ module RgGen
62
70
  end
63
71
 
64
72
  def format_offset(offset)
65
- offset.is_a?(Integer) ? hex(offset, address_width) : offset
66
- end
67
-
68
- def width
69
- register.width
73
+ case offset
74
+ when Integer then hex(offset, address_width)
75
+ else width_cast(offset, address_width)
76
+ end
70
77
  end
71
78
 
72
79
  def valid_bits
73
80
  bits = register.bit_fields.map(&:bit_map).inject(:|)
74
- hex(bits, register.width)
81
+ hex(bits, width)
75
82
  end
76
83
  end
77
84
  end
@@ -2,6 +2,6 @@
2
2
 
3
3
  module RgGen
4
4
  module SystemVerilog
5
- VERSION = '0.30.0'
5
+ VERSION = '0.30.2'
6
6
  end
7
7
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: rggen-systemverilog
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.30.0
4
+ version: 0.30.2
5
5
  platform: ruby
6
6
  authors:
7
7
  - Taichi Ishitani
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2023-04-28 00:00:00.000000000 Z
11
+ date: 2023-08-08 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: bundler
@@ -164,8 +164,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
164
164
  - !ruby/object:Gem::Version
165
165
  version: '0'
166
166
  requirements: []
167
- rubygems_version: 3.4.10
167
+ rubygems_version: 3.4.17
168
168
  signing_key:
169
169
  specification_version: 4
170
- summary: rggen-systemverilog-0.30.0
170
+ summary: rggen-systemverilog-0.30.2
171
171
  test_files: []