rggen-systemverilog 0.29.0 → 0.30.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 7e5fc548cd3c93e80580efc9d2027ce309b9a6e8900078f3f5bf8bb157357e53
-  data.tar.gz: 4fb5af7f5ad76f4938406a553fe425767e2fc363ce79b79b07213fd292535efb
+  metadata.gz: 3485ee878c14865b7457588e96b43fb62e07e7a699204fe5b5f2e4082b143296
+  data.tar.gz: e4b82e5b367666fe0f1d9f62dd4d647348363bcee8f6749032010cc1ee20bd53
 SHA512:
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-  data.tar.gz: 55600c8bf365ffbbc2d8cc6b020e6cb13c33ebb91f49253d53cef0c5a7a5df86d639a61cc0a1eb2aa5d2a36d86530236e837735721da55def694c2a1c19c9d74
+  metadata.gz: 960d4b3469f87ab1d75c74790a56ded92dfc4e12d38a9dadd6a97cb01ea5c4a003cdf9fd347ab998aa9d72d631fc039cfb9a7aa34e76e6445ad11a80e768f231
+  data.tar.gz: b27c8a3e1a6ae7c3e10f4031cf486b57654c6d62df379908cb0e72c9d6a2c069ab66009e6f8dc649be9e3f0119ddab79ad26d7993a621c44271548eccf7265bb

data/lib/rggen/systemverilog/ral/register_common.rb

@@ -26,7 +26,7 @@ module RgGen
         end
 
         def default_offset_address(index)
-          component.offset_address + component.byte_size(false) * index
+          component.offset_address + component.entry_byte_size * index
         end
 
         def hdl_path(array_index)

data/lib/rggen/systemverilog/rtl/partial_sum.rb

@@ -10,7 +10,7 @@ module RgGen
           operands
             .chunk(&method(:integer?))
             .flat_map(&method(:calc_partial_sum))
-            .reject { |value| integer?(value) && value.zero? }
+            .reject(&method(:integer_zero?))
             .tap { |sums| sums.empty? && (sums << 0) }
         end
 
@@ -22,6 +22,10 @@ module RgGen
         def integer?(value)
           value.is_a?(Integer)
         end
+
+        def integer_zero?(value)
+          integer?(value) && value.zero?
+        end
       end
     end
   end

data/lib/rggen/systemverilog/rtl/register/type/default.erb

@@ -4,8 +4,7 @@ rggen_default_register #(
   .ADDRESS_WIDTH  (<%= address_width %>),
   .OFFSET_ADDRESS (<%= offset_address %>),
   .BUS_WIDTH      (<%= bus_width %>),
-  .DATA_WIDTH     (<%= width %>),
-  .REGISTER_INDEX (<%= register_index %>)
+  .DATA_WIDTH     (<%= width %>)
 ) u_register (
   .i_clk        (<%= register_block.clock %>),
   .i_rst_n      (<%= register_block.reset %>),

data/lib/rggen/systemverilog/rtl/register/type/external.rb

@@ -19,12 +19,11 @@ RgGen.define_list_item_feature(:register, :type, :external) do
     end
 
     def start_address
-      hex(register.offset_address, address_width)
+      hex(register.address_range.begin, address_width)
     end
 
     def end_address
-      address = register.offset_address + register.byte_size - 1
-      hex(address, address_width)
+      hex(register.address_range.last, address_width)
     end
   end
 end

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb

@@ -7,7 +7,8 @@ rggen_apb_adapter #(
   .BASE_ADDRESS         (<%= base_address %>),
   .BYTE_SIZE            (<%= byte_size %>),
   .ERROR_STATUS         (<%= error_status %>),
-  .DEFAULT_READ_DATA    (<%= default_read_data %>)
+  .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .INSERT_SLICER        (<%= insert_slicer %>)
 ) u_adapter (
   .i_clk        (<%= clock %>),
   .i_rst_n      (<%= reset %>),

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb

@@ -9,6 +9,7 @@ rggen_axi4lite_adapter #(
   .BYTE_SIZE            (<%= byte_size %>),
   .ERROR_STATUS         (<%= error_status %>),
   .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .INSERT_SLICER        (<%= insert_slicer %>),
   .WRITE_FIRST          (<%= write_first %>)
 ) u_adapter (
   .i_clk        (<%= clock %>),

data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.erb

@@ -8,6 +8,7 @@ rggen_wishbone_adapter #(
   .BYTE_SIZE            (<%= byte_size %>),
   .ERROR_STATUS         (<%= error_status %>),
   .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .INSERT_SLICER        (<%= insert_slicer %>),
   .USE_STALL            (<%= use_stall %>)
 ) u_adapter (
   .i_clk        (<%= clock %>),

data/lib/rggen/systemverilog/rtl/register_block/protocol.rb

@@ -89,6 +89,9 @@ RgGen.define_list_feature(:register_block, :protocol) do
           name: 'DEFAULT_READ_DATA', data_type: :bit, width: bus_width,
           default: all_bits_0
         }
+        parameter :insert_slicer, {
+          name: 'INSERT_SLICER', data_type: :bit, width: 1, default: 0
+        }
       end
 
       private

data/lib/rggen/systemverilog/rtl/register_index.rb

@@ -102,7 +102,13 @@ module RgGen
             operands.reduce(:*)
           elsif operands.first == 1
             operands.last
-          elsif need_bracket
+          else
+            product_expression(operands, need_bracket)
+          end
+        end
+
+        def product_expression(operands, need_bracket)
+          if need_bracket && /[+\-*\/]/ =~ operands.last
             "#{operands.first}*(#{operands.last})"
           else
             operands.join('*')

data/lib/rggen/systemverilog/rtl/register_type.rb

@@ -32,15 +32,29 @@ module RgGen
         end
 
         def collect_offsets(component)
-          if component.register_file? && component.array?
+          if need_byte_offset?(component)
             [component.offset_address, byte_offset(component)]
           else
             component.offset_address
           end
         end
 
+        def need_byte_offset?(component)
+          if component.register_file?
+            component.array?
+          else
+            component.array? && !component.settings[:support_shared_address]
+          end
+        end
+
         def byte_offset(component)
-          "#{component.byte_size(false)}*(#{component.local_index})"
+          byte_size = component.entry_byte_size
+          local_index = component.local_index
+          if /[+\-*\/]/ =~ local_index
+            "#{byte_size}*(#{local_index})"
+          else
+            "#{byte_size}*#{local_index}"
+          end
         end
 
         def format_offsets(offsets)
@@ -59,10 +73,6 @@ module RgGen
           bits = register.bit_fields.map(&:bit_map).inject(:|)
           hex(bits, register.width)
         end
-
-        def register_index
-          register.local_index || 0
-        end
       end
     end
   end

data/lib/rggen/systemverilog/rtl_package/register/sv_rtl_package.rb

@@ -9,7 +9,7 @@ RgGen.define_simple_feature(:register, :sv_rtl_package) do
       }
       localparam :__byte_size, {
         name: "#{full_name}_byte_size",
-        data_type: :int, default: register.byte_size(hierarchical: true)
+        data_type: :int, default: register.total_byte_size(hierarchical: true)
       }
       define_array_size_localparam
       define_offset_localparams

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.29.0'
+    VERSION = '0.30.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.29.0
+  version: 0.30.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2023-01-02 00:00:00.000000000 Z
+date: 2023-04-28 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -164,8 +164,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.4.1
+rubygems_version: 3.4.10
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.29.0
+summary: rggen-systemverilog-0.30.0
 test_files: []