rggen-systemverilog 0.27.1 → 0.29.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019-2022 Taichi Ishitani
+Copyright (c) 2019-2023 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -35,7 +35,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 
 ## Copyright & License
 
-Copyright © 2019-2022 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2019-2023 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/systemverilog/common/utility/identifier.rb

@@ -76,8 +76,8 @@ module RgGen
           def __serialized_lsb__(array_index, lsb)
             index =
               array_index
-                .yield_self(&method(:__serialized_index__))
-                .yield_self(&method(:__enclose_index_in_parenthesis))
+                .then(&method(:__serialized_index__))
+                .then(&method(:__enclose_index_in_parenthesis))
             array_lsb = __reduce_array__([@width, index], :*, 1)
             __reduce_array__([array_lsb, lsb], :+, 0)
           end
@@ -87,7 +87,7 @@ module RgGen
               .reverse
               .zip(__index_factors__)
               .map { |i, f| __calc_index_value__(i, f) }
-              .yield_self { |values| __reduce_array__(values.reverse, :+, 0) }
+              .then { |values| __reduce_array__(values.reverse, :+, 0) }
           end
 
           def __enclose_index_in_parenthesis(index)

data/lib/rggen/systemverilog/common/utility/package_definition.rb

@@ -8,6 +8,7 @@ module RgGen
           define_attribute :name
           define_attribute :package_imports
           define_attribute :include_files
+          define_attribute :parameters
 
           def package_imports(packages)
             @package_imports ||= []
@@ -36,21 +37,28 @@ module RgGen
           def pre_body_code(code)
             package_import_declaration(code)
             file_include_directives(code)
+            parameter_declarations(code)
           end
 
           def package_import_declaration(code)
             declarations =
-              Array(@package_imports)
-                .map { |package| ['import', space, package, '::*'] }
-            add_declarations_to_body(code, declarations)
+              @package_imports
+                &.map { |package| ['import', space, package, '::*'] }
+            declarations &&
+              add_declarations_to_body(code, declarations)
           end
 
           def file_include_directives(code)
-            Array(@include_files).each do |file|
+            @include_files&.each do |file|
               code << ['`include', space, string(file), nl]
             end
           end
 
+          def parameter_declarations(code)
+            parameters &&
+              add_declarations_to_body(code, parameters)
+          end
+
           def footer_code
             'endpackage'
           end

data/lib/rggen/systemverilog/ral/bit_field/type/custom.rb

@@ -0,0 +1,28 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :custom) do
+  sv_ral do
+    model_name do
+      'rggen_ral_custom_field ' \
+        "#(#{sw_read}, #{sw_write}, #{write_once}, #{hw_update})"
+    end
+
+    private
+
+    def sw_read
+      string(bit_field.sw_read.upcase)
+    end
+
+    def sw_write
+      string(bit_field.sw_write.upcase)
+    end
+
+    def write_once
+      bit_field.sw_write_once? && 1 || 0
+    end
+
+    def hw_update
+      bit_field.hw_update? && 1 || 0
+    end
+  end
+end

data/lib/rggen/systemverilog/ral/bit_field/type/rof_rol.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rof, :rol]) do
+  sv_ral { access 'RO' }
+end

data/lib/rggen/systemverilog/ral.rb

@@ -22,7 +22,8 @@ RgGen.setup_plugin :'rggen-sv-ral' do |plugin|
     'ral/register/type/external',
     'ral/register/type/indirect',
     'ral/bit_field/type',
-    'ral/bit_field/type/rof',
+    'ral/bit_field/type/custom',
+    'ral/bit_field/type/rof_rol',
     'ral/bit_field/type/rotrg_rwtrg_wotrg',
     'ral/bit_field/type/row0trg_row1trg_w0trg_w1trg',
     'ral/bit_field/type/rowo_rowotrg',

data/lib/rggen/systemverilog/rtl/bit_field/type/custom.erb

@@ -0,0 +1,25 @@
+rggen_bit_field #(
+  .WIDTH              (<%= width %>),
+  .INITIAL_VALUE      (<%= initial_value %>),
+  .SW_READ_ACTION     (<%= sw_read_action %>),
+  .SW_WRITE_ACTION    (<%= sw_write_action %>),
+  .SW_WRITE_ONCE      (<%= write_once %>),
+  .STORAGE            (<%= storage %>),
+  .EXTERNAL_READ_DATA (<%= external_read_data %>),
+  .TRIGGER            (<%= trigger %>)
+) u_bit_field (
+  .i_clk              (i_clk),
+  .i_rst_n            (i_rst_n),
+  .bit_field_if       (bit_field_sub_if),
+  .o_write_trigger    (<%= output_port(:write_trigger) %>),
+  .o_read_trigger     (<%= output_port(:read_trigger) %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  (<%= input_port(:hw_write_enable) %>),
+  .i_hw_write_data    (<%= input_port(:hw_write_data) %>),
+  .i_hw_set           (<%= input_port(:hw_set) %>),
+  .i_hw_clear         (<%= input_port(:hw_clear) %>),
+  .i_value            (<%= input_port(:value_in) %>),
+  .i_mask             ('1),
+  .o_value            (<%= output_port(:value_out) %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/custom.rb

@@ -0,0 +1,121 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :custom) do
+  sv_rtl do
+    build do
+      if external_read_data?
+        input :value_in, {
+          name: "i_#{full_name}", width: width,
+          array_size: array_size, array_format: array_port_format
+        }
+      else
+        output :value_out, {
+          name: "o_#{full_name}", width: width,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if bit_field.hw_write?
+        input :hw_write_enable, {
+          name: "i_#{full_name}_hw_write_enable", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+        input :hw_write_data, {
+          name: "i_#{full_name}_hw_write_data", width: width,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if bit_field.hw_set?
+        input :hw_set, {
+          name: "i_#{full_name}_hw_set", width: width,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if bit_field.hw_clear?
+        input :hw_clear, {
+          name: "i_#{full_name}_hw_clear", width: width,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if bit_field.write_trigger?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if bit_field.read_trigger?
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def external_read_data?
+      !bit_field.sw_update? && !bit_field.hw_update?
+    end
+
+    def initial_value
+      external_read_data? && all_bits_0 || super
+    end
+
+    def sw_read_action
+      {
+        none: 'RGGEN_READ_NONE',
+        default: 'RGGEN_READ_DEFAULT',
+        set: 'RGGEN_READ_SET',
+        clear: 'RGGEN_READ_CLEAR'
+      }[bit_field.sw_read]
+    end
+
+    def sw_write_action
+      {
+        none: 'RGGEN_WRITE_NONE',
+        default: 'RGGEN_WRITE_DEFAULT',
+        clear_0: 'RGGEN_WRITE_0_CLEAR',
+        clear_1: 'RGGEN_WRITE_1_CLEAR',
+        clear: 'RGGEN_WRITE_CLEAR',
+        set_0: 'RGGEN_WRITE_0_SET',
+        set_1: 'RGGEN_WRITE_1_SET',
+        set: 'RGGEN_WRITE_SET',
+        toggle_0: 'RGGEN_WRITE_0_TOGGLE',
+        toggle_1: 'RGGEN_WRITE_1_TOGGLE'
+      }[bit_field.sw_write]
+    end
+
+    def write_once
+      bit_field.sw_write_once? && 1 || 0
+    end
+
+    def storage
+      external_read_data? && 0 || 1
+    end
+
+    def external_read_data
+      external_read_data? && 1 || 0
+    end
+
+    def trigger?
+      bit_field.write_trigger? || bit_field.read_trigger?
+    end
+
+    def trigger
+      trigger? && 1 || 0
+    end
+
+    def input_port(name)
+      find_port(name, all_bits_0)
+    end
+
+    def output_port(name)
+      find_port(name, '')
+    end
+
+    def find_port(name, default_value)
+      respond_to?(name) && __send__(name)[loop_variables] || default_value
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rol.erb

@@ -0,0 +1,20 @@
+rggen_bit_field #(
+  .WIDTH            (<%= width %>),
+  .INITIAL_VALUE    (<%= initial_value %>),
+  .SW_WRITE_ACTION  (RGGEN_WRITE_NONE)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  (<%= latch_signal %>),
+  .i_hw_write_data    (<%= value_in[loop_variables] %>),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/rol.rb

@@ -0,0 +1,30 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rol) do
+  sv_rtl do
+    build do
+      unless bit_field.reference?
+        input :latch, {
+          name: "i_#{full_name}_latch", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      input :value_in, {
+        name: "i_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def latch_signal
+      reference_bit_field || latch[loop_variables]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb

@@ -20,7 +20,7 @@ RgGen.define_list_item_feature(
     end
 
     def read_set?
-      [:w0crs, :w1crs, :wcrs].include?(bit_field.type)
+      [:w0crs, :w1crs, :wcrs].any? { |type| bit_field.type == type }
     end
 
     def write_action

data/lib/rggen/systemverilog/rtl/register_index.rb

@@ -51,9 +51,9 @@ module RgGen
 
         def index(offset_or_offsets = nil)
           offset_or_offsets
-            .yield_self(&method(:index_operands))
-            .yield_self(&method(:partial_sums))
-            .yield_self(&method(:reduce_indices))
+            .then(&method(:index_operands))
+            .then(&method(:partial_sums))
+            .then(&method(:reduce_indices))
         end
 
         def inside_loop?

data/lib/rggen/systemverilog/rtl/register_type.rb

@@ -27,8 +27,8 @@ module RgGen
         def offset_address
           [*register_files, register]
             .flat_map(&method(:collect_offsets))
-            .yield_self(&method(:partial_sums))
-            .yield_self(&method(:format_offsets))
+            .then(&method(:partial_sums))
+            .then(&method(:format_offsets))
         end
 
         def collect_offsets(component)

data/lib/rggen/systemverilog/rtl.rb

@@ -7,6 +7,7 @@ require_relative 'rtl/register_index'
 require_relative 'rtl/register_type'
 require_relative 'rtl/indirect_index'
 require_relative 'rtl/bit_field_index'
+require_relative 'rtl_package/feature'
 
 RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
   plugin.version RgGen::SystemVerilog::VERSION
@@ -32,9 +33,11 @@ RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
     'rtl/register/type/indirect',
     'rtl/bit_field/sv_rtl_top',
     'rtl/bit_field/type',
+    'rtl/bit_field/type/custom',
     'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
     'rtl/bit_field/type/ro_rotrg',
     'rtl/bit_field/type/rof',
+    'rtl/bit_field/type/rol',
     'rtl/bit_field/type/row0trg_row1trg',
     'rtl/bit_field/type/rowo_rowotrg',
     'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
@@ -48,4 +51,17 @@ RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
     'rtl/bit_field/type/wo_wo1_wotrg',
     'rtl/bit_field/type/wrc_wrs'
   ]
+
+  plugin.register_component :sv_rtl_package do
+    component RgGen::SystemVerilog::Common::Component,
+              RgGen::SystemVerilog::Common::ComponentFactory
+    feature RgGen::SystemVerilog::RTLPackage::Feature,
+            RgGen::SystemVerilog::Common::FeatureFactory
+  end
+
+  plugin.files [
+    'rtl_package/bit_field/sv_rtl_package',
+    'rtl_package/register/sv_rtl_package',
+    'rtl_package/register_block/sv_rtl_package'
+  ]
 end

data/lib/rggen/systemverilog/rtl_package/bit_field/sv_rtl_package.rb

@@ -0,0 +1,65 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:bit_field, :sv_rtl_package) do
+  sv_rtl_package do
+    build do
+      localparam :__width, {
+        name: "#{full_name}_bit_width",
+        data_type: :int, default: bit_field.width
+      }
+      localparam :__mask, {
+        name: "#{full_name}_bit_mask",
+        data_type: :bit, width: bit_field.width, default: mask_value
+      }
+      define_offset_localparam
+      define_label_localparams
+    end
+
+    private
+
+    def mask_value
+      hex((1 << bit_field.width) - 1, bit_field.width)
+    end
+
+    def define_offset_localparam
+      if bit_field.sequential?
+        define_sequential_offset_localparam
+      else
+        define_single_offset_localparam
+      end
+    end
+
+    def define_sequential_offset_localparam
+      size = bit_field.sequence_size
+      localparam :__offset, {
+        name: "#{full_name}_bit_offset",
+        data_type: :int, array_size: [size], default: offset_value(size)
+      }
+    end
+
+    def offset_value(size)
+      array(Array.new(size, &bit_field.method(:lsb)))
+    end
+
+    def define_single_offset_localparam
+      localparam :__offset, {
+        name: "#{full_name}_bit_offset",
+        data_type: :int, default: bit_field.lsb
+      }
+    end
+
+    def define_label_localparams
+      bit_field.labels
+        .each { |label| define_label_localparam(label) }
+    end
+
+    def define_label_localparam(label)
+      identifier = "label_#{label.name}".downcase.to_sym
+      value = hex(label.value, bit_field.width)
+      localparam identifier, {
+        name: "#{full_name}_#{label.name}",
+        data_type: :bit, width: bit_field.width, default: value
+      }
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl_package/feature.rb

@@ -0,0 +1,28 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTLPackage
+      class Feature < Common::Feature
+        private
+
+        def full_name(separator = '_')
+          component.full_name(separator)
+        end
+
+        def create_parameter(parameter_type, attributes, &block)
+          attributes =
+            attributes.merge(
+              parameter_type: parameter_type, array_format: :unpacked,
+              name: attributes[:name].upcase
+            )
+          DataObject.new(
+            :parameter, attributes, &block
+          )
+        end
+
+        define_entity :localparam, :create_parameter, :parameter, -> { register_block }
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl_package/register/sv_rtl_package.rb

@@ -0,0 +1,83 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register, :sv_rtl_package) do
+  sv_rtl_package do
+    build do
+      localparam :__byte_width, {
+        name: "#{full_name}_byte_width",
+        data_type: :int, default: register.byte_width
+      }
+      localparam :__byte_size, {
+        name: "#{full_name}_byte_size",
+        data_type: :int, default: register.byte_size(hierarchical: true)
+      }
+      define_array_size_localparam
+      define_offset_localparams
+    end
+
+    private
+
+    def define_array_size_localparam
+      return unless array?
+
+      list = array_size_list
+      localparam :__array_size, {
+        name: "#{full_name}_array_size",
+        data_type: :int, array_size: [list.size], default: array(list)
+      }
+    end
+
+    def define_offset_localparams
+      if array?
+        define_array_offset_localparams
+      else
+        define_single_offset_localparam
+      end
+    end
+
+    def define_array_offset_localparams
+      width = register_block.local_address_width
+      size_list = array_size_list
+      value_list = group_address_list(address_list, size_list).first
+      localparam :__offset, {
+        name: "#{full_name}_byte_offset",
+        data_type: :bit, width: width, array_size: size_list, default: value_list
+      }
+    end
+
+    def address_list
+      register
+        .expanded_offset_addresses
+        .map { |address| hex(address, register_block.local_address_width) }
+    end
+
+    def group_address_list(address_list, size_list)
+      list =
+        if size_list.size > 1
+          group_address_list(address_list, size_list[1..])
+        else
+          address_list
+        end
+      list
+        .each_slice(size_list.first)
+        .map(&method(:array))
+    end
+
+    def define_single_offset_localparam
+      width = register_block.local_address_width
+      value = address_list.first
+      localparam :__offset, {
+        name: "#{full_name}_byte_offset",
+        data_type: :bit, width: width, default: value
+      }
+    end
+
+    def array?
+      register.array?(hierarchical: true)
+    end
+
+    def array_size_list
+      register.array_size(hierarchical: true)
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl_package/register_block/sv_rtl_package.rb

@@ -0,0 +1,25 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_block, :sv_rtl_package) do
+  sv_rtl_package do
+    write_file '<%= package_name %>.sv' do |file|
+      file.body { sv_rtl_package_definition }
+    end
+
+    private
+
+    def sv_rtl_package_definition
+      package_definition(package_name) do |package|
+        package.parameters parameters
+      end
+    end
+
+    def package_name
+      "#{register_block.name}_rtl_pkg"
+    end
+
+    def parameters
+      register_block.declarations[:parameter]
+    end
+  end
+end

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.27.1'
+    VERSION = '0.29.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.27.1
+  version: 0.29.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2022-08-30 00:00:00.000000000 Z
+date: 2023-01-02 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -55,7 +55,8 @@ files:
 - lib/rggen/systemverilog/common/utility/structure_definition.rb
 - lib/rggen/systemverilog/ral.rb
 - lib/rggen/systemverilog/ral/bit_field/type.rb
-- lib/rggen/systemverilog/ral/bit_field/type/rof.rb
+- lib/rggen/systemverilog/ral/bit_field/type/custom.rb
+- lib/rggen/systemverilog/ral/bit_field/type/rof_rol.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb
 - lib/rggen/systemverilog/ral/bit_field/type/row0trg_row1trg_w0trg_w1trg.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb
@@ -76,12 +77,16 @@ files:
 - lib/rggen/systemverilog/rtl.rb
 - lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/bit_field/type.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/custom.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/custom.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rol.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rol.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb
@@ -130,6 +135,10 @@ files:
 - lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register_index.rb
 - lib/rggen/systemverilog/rtl/register_type.rb
+- lib/rggen/systemverilog/rtl_package/bit_field/sv_rtl_package.rb
+- lib/rggen/systemverilog/rtl_package/feature.rb
+- lib/rggen/systemverilog/rtl_package/register/sv_rtl_package.rb
+- lib/rggen/systemverilog/rtl_package/register_block/sv_rtl_package.rb
 - lib/rggen/systemverilog/version.rb
 homepage: https://github.com/rggen/rggen-systemverilog
 licenses:
@@ -148,15 +157,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '2.6'
+      version: '2.7'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.3.7
+rubygems_version: 3.4.1
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.27.1
+summary: rggen-systemverilog-0.29.0
 test_files: []

data/lib/rggen/systemverilog/ral/bit_field/type/rof.rb

@@ -1,5 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :rof) do
-  sv_ral { access 'RO' }
-end