rggen-systemverilog 0.26.0 → 0.27.1

checksums.yaml

@@ -1,7 +1,7 @@
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-  data.tar.gz: e2c07ce7eb68f15c9e4d2dbd0f83d7a74dbcb92ba292ba1fae8830c4ca147cb0
+  metadata.gz: b163ec13c4940ca6d489739aaae909dd3d189627eff20383cef519537bade127
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+  data.tar.gz: be673375b40e9d4c8241be45a4feb8ee4a09d815bc4ecd0926759f058dea021e8588b270de22408f8a34fa8cb5f50772f51addc47b3cfa60dba0c858064bccbd

data/README.md

@@ -27,7 +27,8 @@ $ gem isntall rggen-systemverilog
 
 Feedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:
 
-* [GitHub Issue Tracker](https://github.com/rggen/rggen-systemverilog/issues)
+* [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)
+* [GitHub Discussions](https://github.com/rggen/rggen/discussions)
 * [Chat Room](https://gitter.im/rggen/rggen)
 * [Mailing List](https://groups.google.com/d/forum/rggen)
 * [Mail](mailto:rggen@googlegroups.com)

data/lib/rggen/systemverilog/ral/bit_field/type/{w0trg_w1trg.rb → row0trg_row1trg_w0trg_w1trg.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:row0trg, :row1trg, :w0trg, :w1trg]) do
   sv_ral do
     model_name { "rggen_ral_#{bit_field.type}_field" }
   end

data/lib/rggen/systemverilog/ral.rb

@@ -4,35 +4,29 @@ require_relative 'common'
 require_relative 'ral/feature'
 require_relative 'ral/register_common'
 
-module RgGen
-  module SystemVerilog
-    module RAL
-      extend Core::Plugin
+RgGen.setup_plugin :'rggen-sv-ral' do |plugin|
+  plugin.version RgGen::SystemVerilog::VERSION
 
-      setup_plugin :'rggen-sv-ral' do |plugin|
-        plugin.version SystemVerilog::VERSION
-
-        plugin.register_component :sv_ral do
-          component Common::Component, Common::ComponentFactory
-          feature Feature, Common::FeatureFactory
-        end
-
-        plugin.files [
-          'ral/bit_field/type',
-          'ral/bit_field/type/rof',
-          'ral/bit_field/type/rotrg_rwtrg_wotrg',
-          'ral/bit_field/type/rowo_rowotrg',
-          'ral/bit_field/type/rwc_rws',
-          'ral/bit_field/type/rwe_rwl',
-          'ral/bit_field/type/w0trg_w1trg',
-          'ral/register/type',
-          'ral/register/type/external',
-          'ral/register/type/indirect',
-          'ral/register_block/sv_ral_model',
-          'ral/register_block/sv_ral_package',
-          'ral/register_file/sv_ral_model'
-        ]
-      end
-    end
+  plugin.register_component :sv_ral do
+    component RgGen::SystemVerilog::Common::Component,
+              RgGen::SystemVerilog::Common::ComponentFactory
+    feature RgGen::SystemVerilog::RAL::Feature,
+            RgGen::SystemVerilog::Common::FeatureFactory
   end
+
+  plugin.files [
+    'ral/register_block/sv_ral_package',
+    'ral/register_block/sv_ral_model',
+    'ral/register_file/sv_ral_model',
+    'ral/register/type',
+    'ral/register/type/external',
+    'ral/register/type/indirect',
+    'ral/bit_field/type',
+    'ral/bit_field/type/rof',
+    'ral/bit_field/type/rotrg_rwtrg_wotrg',
+    'ral/bit_field/type/row0trg_row1trg_w0trg_w1trg',
+    'ral/bit_field/type/rowo_rowotrg',
+    'ral/bit_field/type/rwc_rws',
+    'ral/bit_field/type/rwe_rwl'
+  ]
 end

data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb

@@ -36,10 +36,6 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
       end
     end
 
-    pre_code :bit_field do |code|
-      code << bit_field_if_connection << nl
-    end
-
     def value(offsets = nil, width = nil)
       value_lsb = bit_field.lsb(offsets&.last || local_index)
       value_width = width || bit_field.width
@@ -113,17 +109,5 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
     def body_code(code)
       bit_field.generate_code(code, :bit_field, :top_down)
     end
-
-    def bit_field_if_connection
-      macro_call(
-        'rggen_connect_bit_field_if',
-        [
-          register.bit_field_if,
-          bit_field.bit_field_sub_if,
-          bit_field.lsb(local_index),
-          bit_field.width
-        ]
-      )
-    end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.erb

@@ -0,0 +1,10 @@
+rggen_bit_field_w01trg #(
+  .TRIGGER_VALUE  (<%= trigger_value %>),
+  .WIDTH          (<%= width %>)
+) u_bit_field (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .i_value      (<%= reference_or_value_in %>),
+  .o_trigger    (<%= trigger[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb

@@ -0,0 +1,30 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:row0trg, :row1trg]) do
+  sv_rtl do
+    build do
+      unless bit_field.reference?
+        input :value_in, {
+          name: "i_#{full_name}", width: width,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      output :trigger, {
+        name: "o_#{full_name}_trigger", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def trigger_value
+      bin({ row0trg: 0, row1trg: 1 }[bit_field.type], 1)
+    end
+
+    def reference_or_value_in
+      reference_bit_field || value_in[loop_variables]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb

@@ -5,5 +5,6 @@ rggen_bit_field_w01trg #(
   .i_clk        (<%= clock %>),
   .i_rst_n      (<%= reset %>),
   .bit_field_if (<%= bit_field_if %>),
+  .i_value      ('0),
   .o_trigger    (<%= trigger[loop_variables] %>)
 );

data/lib/rggen/systemverilog/rtl/bit_field/type.rb

@@ -3,6 +3,10 @@
 RgGen.define_list_feature(:bit_field, :type) do
   sv_rtl do
     base_feature do
+      pre_code :bit_field do |code|
+        code << bit_field_if_connection << nl
+      end
+
       private
 
       def array_port_format
@@ -17,6 +21,10 @@ RgGen.define_list_feature(:bit_field, :type) do
         bit_field.width
       end
 
+      def lsb
+        bit_field.lsb(bit_field.local_index)
+      end
+
       def clock
         register_block.clock
       end
@@ -52,6 +60,13 @@ RgGen.define_list_feature(:bit_field, :type) do
       def loop_variables
         bit_field.loop_variables
       end
+
+      def bit_field_if_connection
+        macro_call(
+          'rggen_connect_bit_field_if',
+          [register.bit_field_if, bit_field_if, lsb, width]
+        )
+      end
     end
 
     factory do

data/lib/rggen/systemverilog/rtl/register/type/default.erb

@@ -5,7 +5,6 @@ rggen_default_register #(
   .OFFSET_ADDRESS (<%= offset_address %>),
   .BUS_WIDTH      (<%= bus_width %>),
   .DATA_WIDTH     (<%= width %>),
-  .VALID_BITS     (<%= valid_bits %>),
   .REGISTER_INDEX (<%= register_index %>)
 ) u_register (
   .i_clk        (<%= register_block.clock %>),

data/lib/rggen/systemverilog/rtl/register/type/indirect.erb

@@ -5,7 +5,6 @@ rggen_indirect_register #(
   .OFFSET_ADDRESS       (<%= offset_address %>),
   .BUS_WIDTH            (<%= bus_width %>),
   .DATA_WIDTH           (<%= width %>),
-  .VALID_BITS           (<%= valid_bits %>),
   .INDIRECT_INDEX_WIDTH (<%= index_width %>),
   .INDIRECT_INDEX_VALUE (<%= concat(index_values) %>)
 ) u_register (

data/lib/rggen/systemverilog/rtl/register/type.rb

@@ -5,6 +5,11 @@ RgGen.define_list_feature(:register, :type) do
     base_feature do
       include RgGen::SystemVerilog::RTL::RegisterType
 
+      pre_code :register do |code|
+        register.bit_fields.empty? ||
+          (code << tie_off_unused_signals << nl)
+      end
+
       private
 
       def register_if
@@ -14,6 +19,13 @@ RgGen.define_list_feature(:register, :type) do
       def bit_field_if
         register.bit_field_if
       end
+
+      def tie_off_unused_signals
+        macro_call(
+          'rggen_tie_off_unused_signals',
+          [width, valid_bits, bit_field_if]
+        )
+      end
     end
 
     default_feature do

data/lib/rggen/systemverilog/rtl/register_block/protocol.rb

@@ -8,7 +8,8 @@ RgGen.define_list_feature(:register_block, :protocol) do
 
     def available_protocols
       feature_registries
-        .map(&method(:collect_available_protocols)).inject(:&)
+        .map { |registry| registry.enabled_features(:protocol) }
+        .inject(:&)
     end
 
     private

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb

@@ -7,3 +7,15 @@
   assign  RIF.read_data[LSB+:WIDTH] = FIF.read_data; \
   assign  RIF.value[LSB+:WIDTH]     = FIF.value;
 `endif
+`ifndef rggen_tie_off_unused_signals
+  `define rggen_tie_off_unused_signals(WIDTH, VALID_BITS, RIF) \
+  if (1) begin : __g_tie_off \
+    genvar  __i; \
+    for (__i = 0;__i < WIDTH;++__i) begin : g \
+      if (!(((VALID_BITS) >> __i) & 1'b1)) begin : g \
+        assign  RIF.read_data[__i]  = 1'b0; \
+        assign  RIF.value[__i]      = 1'b0; \
+      end \
+    end \
+  end
+`endif

data/lib/rggen/systemverilog/rtl.rb

@@ -8,49 +8,44 @@ require_relative 'rtl/register_type'
 require_relative 'rtl/indirect_index'
 require_relative 'rtl/bit_field_index'
 
-module RgGen
-  module SystemVerilog
-    module RTL
-      extend Core::Plugin
+RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
+  plugin.version RgGen::SystemVerilog::VERSION
 
-      setup_plugin :'rggen-sv-rtl' do |plugin|
-        plugin.version SystemVerilog::VERSION
-
-        plugin.register_component :sv_rtl do
-          component Common::Component, Common::ComponentFactory
-          feature Feature, Common::FeatureFactory
-        end
-
-        plugin.files [
-          'rtl/bit_field/sv_rtl_top',
-          'rtl/bit_field/type',
-          'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
-          'rtl/bit_field/type/ro_rotrg',
-          'rtl/bit_field/type/rof',
-          'rtl/bit_field/type/rowo_rowotrg',
-          'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
-          'rtl/bit_field/type/rw_rwtrg_w1',
-          'rtl/bit_field/type/rwc',
-          'rtl/bit_field/type/rwe_rwl',
-          'rtl/bit_field/type/rws',
-          'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
-          'rtl/bit_field/type/w0t_w1t',
-          'rtl/bit_field/type/w0trg_w1trg',
-          'rtl/bit_field/type/wo_wo1_wotrg',
-          'rtl/bit_field/type/wrc_wrs',
-          'rtl/global/array_port_format',
-          'rtl/register/sv_rtl_top',
-          'rtl/register/type',
-          'rtl/register/type/external',
-          'rtl/register/type/indirect',
-          'rtl/register_block/protocol',
-          'rtl/register_block/protocol/apb',
-          'rtl/register_block/protocol/axi4lite',
-          'rtl/register_block/protocol/wishbone',
-          'rtl/register_block/sv_rtl_top',
-          'rtl/register_file/sv_rtl_top'
-        ]
-      end
-    end
+  plugin.register_component :sv_rtl do
+    component RgGen::SystemVerilog::Common::Component,
+              RgGen::SystemVerilog::Common::ComponentFactory
+    feature RgGen::SystemVerilog::RTL::Feature,
+            RgGen::SystemVerilog::Common::FeatureFactory
   end
+
+  plugin.files [
+    'rtl/global/array_port_format',
+    'rtl/register_block/sv_rtl_top',
+    'rtl/register_block/protocol',
+    'rtl/register_block/protocol/apb',
+    'rtl/register_block/protocol/axi4lite',
+    'rtl/register_block/protocol/wishbone',
+    'rtl/register_file/sv_rtl_top',
+    'rtl/register/sv_rtl_top',
+    'rtl/register/type',
+    'rtl/register/type/external',
+    'rtl/register/type/indirect',
+    'rtl/bit_field/sv_rtl_top',
+    'rtl/bit_field/type',
+    'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
+    'rtl/bit_field/type/ro_rotrg',
+    'rtl/bit_field/type/rof',
+    'rtl/bit_field/type/row0trg_row1trg',
+    'rtl/bit_field/type/rowo_rowotrg',
+    'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
+    'rtl/bit_field/type/rw_rwtrg_w1',
+    'rtl/bit_field/type/rwc',
+    'rtl/bit_field/type/rwe_rwl',
+    'rtl/bit_field/type/rws',
+    'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
+    'rtl/bit_field/type/w0t_w1t',
+    'rtl/bit_field/type/w0trg_w1trg',
+    'rtl/bit_field/type/wo_wo1_wotrg',
+    'rtl/bit_field/type/wrc_wrs'
+  ]
 end

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.26.0'
+    VERSION = '0.27.1'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.26.0
+  version: 0.27.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2022-03-25 00:00:00.000000000 Z
+date: 2022-08-30 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -57,10 +57,10 @@ files:
 - lib/rggen/systemverilog/ral/bit_field/type.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rof.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb
+- lib/rggen/systemverilog/ral/bit_field/type/row0trg_row1trg_w0trg_w1trg.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb
-- lib/rggen/systemverilog/ral/bit_field/type/w0trg_w1trg.rb
 - lib/rggen/systemverilog/ral/feature.rb
 - lib/rggen/systemverilog/ral/register/type.rb
 - lib/rggen/systemverilog/ral/register/type/default.erb
@@ -73,7 +73,6 @@ files:
 - lib/rggen/systemverilog/ral/register_common.rb
 - lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb
 - lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb
-- lib/rggen/systemverilog/ral/setup.rb
 - lib/rggen/systemverilog/rtl.rb
 - lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/bit_field/type.rb
@@ -83,6 +82,8 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb
@@ -129,13 +130,12 @@ files:
 - lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register_index.rb
 - lib/rggen/systemverilog/rtl/register_type.rb
-- lib/rggen/systemverilog/rtl/setup.rb
 - lib/rggen/systemverilog/version.rb
 homepage: https://github.com/rggen/rggen-systemverilog
 licenses:
 - MIT
 metadata:
-  bug_tracker_uri: https://github.com/rggen/rggen-systemverilog/issues
+  bug_tracker_uri: https://github.com/rggen/rggen/issues
   mailing_list_uri: https://groups.google.com/d/forum/rggen
   rubygems_mfa_required: 'true'
   source_code_uri: https://github.com/rggen/rggen-systemverilog
@@ -155,8 +155,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.3.3
+rubygems_version: 3.3.7
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.26.0
+summary: rggen-systemverilog-0.27.1
 test_files: []

data/lib/rggen/systemverilog/ral/setup.rb

@@ -1,8 +0,0 @@
-# frozen_string_literal: true
-
-require 'rggen/systemverilog/ral'
-
-RgGen.register_plugin RgGen::SystemVerilog::RAL do |builder|
-  builder.enable :register_block, [:sv_ral_model, :sv_ral_package]
-  builder.enable :register_file, [:sv_ral_model]
-end

data/lib/rggen/systemverilog/rtl/setup.rb

@@ -1,12 +0,0 @@
-# frozen_string_literal: true
-
-require 'rggen/systemverilog/rtl'
-
-RgGen.register_plugin RgGen::SystemVerilog::RTL do |builder|
-  builder.enable :global, [:array_port_format]
-  builder.enable :register_block, [:sv_rtl_top, :protocol]
-  builder.enable :register_block, :protocol, [:apb, :axi4lite, :wishbone]
-  builder.enable :register_file, [:sv_rtl_top]
-  builder.enable :register, [:sv_rtl_top]
-  builder.enable :bit_field, [:sv_rtl_top]
-end