rggen-systemverilog 0.24.0 → 0.25.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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-  data.tar.gz: 75bd4c611fa964f30df059fe39d547daf688322ed1076654744381dc38a67068
+  metadata.gz: f2fe4d8d918cc5291f84654d19f75670ef8fb49e9405e6b2dba2d2fb418ffacb
+  data.tar.gz: a51b6c2fb4589c9c149132132c4087ed01bbfb6a31feccb5247d2056a90c7ede
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+  data.tar.gz: c6a97f80b046acfbde8882fa85371267ba776d90bec180595c146fa9b44913a42453e348c17979a74253baeb00ed5e70448d10d6ba03a796048bdd42ded9a4b7

data/lib/rggen/systemverilog/common.rb

@@ -1,7 +1,5 @@
 # frozen_string_literal: true
 
-require 'facets/kernel/attr_singleton'
-
 require_relative 'version'
 
 require_relative 'common/utility/identifier'

data/lib/rggen/systemverilog/common/factories.rb

@@ -3,7 +3,7 @@
 module RgGen
   module SystemVerilog
     module Common
-      class ComponentFactory < Core::OutputBase::ComponentFactory
+      class ComponentFactory < Core::OutputBase::SourceFileComponentFactory
       end
 
       class FeatureFactory < Core::OutputBase::FeatureFactory

data/lib/rggen/systemverilog/common/feature.rb

@@ -73,7 +73,7 @@ module RgGen
 
         def add_identifier(entity, name)
           instance_variable_set("@#{name}", entity.identifier)
-          attr_singleton_reader(name)
+          singleton_exec { attr_reader name }
           export(name)
         end
 

data/lib/rggen/systemverilog/common/utility.rb

@@ -13,7 +13,7 @@ module RgGen
         private
 
         def create_identifier(name)
-          Identifier.new(name)
+          name && Identifier.new(name)
         end
 
         def assign(lhs, rhs)

data/lib/rggen/systemverilog/common/utility/class_definition.rb

@@ -13,10 +13,14 @@ module RgGen
           private
 
           def header_code(code)
-            code << [:class, space, name]
+            class_header_begin(code)
             parameter_declarations(code)
             class_inheritance(code)
-            code << semicolon
+            class_header_end(code)
+          end
+
+          def class_header_begin(code)
+            code << ['class', space, name]
           end
 
           def parameter_declarations(code)
@@ -28,7 +32,11 @@ module RgGen
 
           def class_inheritance(code)
             return unless base
-            code << [space, :extends, space, base]
+            code << [space, 'extends', space, base]
+          end
+
+          def class_header_end(code)
+            code << semicolon
           end
 
           def pre_body_code(code)
@@ -36,7 +44,7 @@ module RgGen
           end
 
           def footer_code
-            :endclass
+            'endclass'
           end
         end
       end

data/lib/rggen/systemverilog/common/utility/data_object.rb

@@ -25,8 +25,7 @@ module RgGen
 
           def declaration
             declaration_snippets
-              .select(&:itself)
-              .reject(&:empty?)
+              .select { |snippet| snippet && !snippet.empty? }
               .join(' ')
           end
 

data/lib/rggen/systemverilog/common/utility/function_definition.rb

@@ -19,11 +19,15 @@ module RgGen
           private
 
           def header_code(code)
-            code << :function
+            function_header_begin(code)
             return_type_declaration(code)
-            code << [space, name]
+            function_name(code)
             argument_declarations(code)
-            code << semicolon
+            function_header_end(code)
+          end
+
+          def function_header_begin(code)
+            code << 'function'
           end
 
           def return_type_declaration(code)
@@ -31,14 +35,22 @@ module RgGen
             code << [space, return_type.declaration]
           end
 
+          def function_name(code)
+            code << space << name
+          end
+
           def argument_declarations(code)
             wrap(code, '(', ')') do
               add_declarations_to_header(code, Array(arguments))
             end
           end
 
+          def function_header_end(code)
+            code << semicolon
+          end
+
           def footer_code
-            :endfunction
+            'endfunction'
           end
         end
       end

data/lib/rggen/systemverilog/common/utility/identifier.rb

@@ -80,13 +80,12 @@ module RgGen
           end
 
           def __serialized_index__(array_index)
-            index_values =
-              array_index
-                .reverse
-                .zip(__index_factors__)
-                .map { |i, f| __calc_index_value__(i, f) }
-            index = __reduce_array__(index_values.reverse, :+, 0)
-            integer?(index) ? index : "(#{index})"
+            array_index
+              .reverse
+              .zip(__index_factors__)
+              .map { |i, f| __calc_index_value__(i, f) }
+              .yield_self { |values| __reduce_array__(values.reverse, :+, 0) }
+              .yield_self { |index| integer?(index) && index || "(#{index})" }
           end
 
           def __index_factors__

data/lib/rggen/systemverilog/common/utility/local_scope.rb

@@ -17,13 +17,13 @@ module RgGen
           private
 
           def header_code(code)
-            code << [:generate, space] if @top_scope
+            code << ['generate', space] if @top_scope
             code << "if (1) begin : #{name}" << nl
           end
 
           def footer_code(code)
-            code << :end
-            code << [space, :endgenerate] if @top_scope
+            code << 'end'
+            code << [space, 'endgenerate'] if @top_scope
           end
 
           def pre_body_code(code)
@@ -58,10 +58,12 @@ module RgGen
           end
 
           def post_body_code(code)
-            (loop_size&.size || 0).times do
-              code.indent -= 2
-              code << :end << nl
-            end
+            loop_size&.size&.times { generate_for_end(code) }
+          end
+
+          def generate_for_end(code)
+            code.indent -= 2
+            code << 'end' << nl
           end
         end
       end

data/lib/rggen/systemverilog/common/utility/module_definition.rb

@@ -23,11 +23,15 @@ module RgGen
           private
 
           def header_code(code)
-            code << [:module, space, name]
+            module_header_begin(code)
             package_import_declaration(code)
             parameter_declarations(code)
             port_declarations(code)
-            code << semicolon
+            module_header_end(code)
+          end
+
+          def module_header_begin(code)
+            code << 'module' << space << name
           end
 
           def package_import_declaration(code)
@@ -41,7 +45,7 @@ module RgGen
           def pacakge_import_items
             Array(@package_imports).map.with_index do |package, i|
               if i.zero?
-                [:import, "#{package}::*"].join(space)
+                ['import', "#{package}::*"].join(space)
               else
                 [space(6), "#{package}::*"].join(space)
               end
@@ -62,12 +66,16 @@ module RgGen
             end
           end
 
+          def module_header_end(code)
+            code << semicolon
+          end
+
           def pre_body_code(code)
             add_declarations_to_body(code, Array(variables))
           end
 
           def footer_code
-            :endmodule
+            'endmodule'
           end
         end
       end

data/lib/rggen/systemverilog/common/utility/package_definition.rb

@@ -30,7 +30,7 @@ module RgGen
           private
 
           def header_code(code)
-            code << [:package, space, name, semicolon]
+            code << ['package', space, name, semicolon]
           end
 
           def pre_body_code(code)
@@ -41,18 +41,18 @@ module RgGen
           def package_import_declaration(code)
             declarations =
               Array(@package_imports)
-                .map { |package| [:import, space, package, '::*'] }
+                .map { |package| ['import', space, package, '::*'] }
             add_declarations_to_body(code, declarations)
           end
 
           def file_include_directives(code)
             Array(@include_files).each do |file|
-              code << [:'`include', space, string(file), nl]
+              code << ['`include', space, string(file), nl]
             end
           end
 
           def footer_code
-            :endpackage
+            'endpackage'
           end
         end
       end

data/lib/rggen/systemverilog/ral.rb

@@ -19,7 +19,7 @@ module RgGen
 
         plugin.files [
           'ral/bit_field/type',
-          'ral/bit_field/type/reserved_rof',
+          'ral/bit_field/type/rof',
           'ral/bit_field/type/rwc_rws',
           'ral/bit_field/type/rwe_rwl',
           'ral/bit_field/type/w0trg_w1trg',

data/lib/rggen/systemverilog/ral/bit_field/type.rb

@@ -29,12 +29,12 @@ RgGen.define_list_feature(:bit_field, :type) do
 
       def model_name
         name = helper.model_name
-        name.is_a?(Proc) && instance_eval(&name) || name || :rggen_ral_field
+        name.is_a?(Proc) && instance_eval(&name) || name || 'rggen_ral_field'
       end
 
       def constructors
         (bit_field.sequence_size&.times || [nil]).map do |index|
-          macro_call(:rggen_ral_create_field, arguments(index))
+          macro_call('rggen_ral_create_field', arguments(index))
         end
       end
 

data/lib/rggen/systemverilog/ral/bit_field/type/rof.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rof) do
+  sv_ral { access 'RO' }
+end

data/lib/rggen/systemverilog/rtl.rb

@@ -25,14 +25,12 @@ module RgGen
           'rtl/bit_field/sv_rtl_top',
           'rtl/bit_field/type',
           'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
-          'rtl/bit_field/type/reserved',
           'rtl/bit_field/type/ro',
           'rtl/bit_field/type/rof',
           'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
           'rtl/bit_field/type/rw_w1_wo_wo1',
           'rtl/bit_field/type/rwc',
-          'rtl/bit_field/type/rwe',
-          'rtl/bit_field/type/rwl',
+          'rtl/bit_field/type/rwe_rwl',
           'rtl/bit_field/type/rws',
           'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
           'rtl/bit_field/type/w0t_w1t',

data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb

@@ -116,7 +116,7 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
 
     def bit_field_if_connection
       macro_call(
-        :rggen_connect_bit_field_if,
+        'rggen_connect_bit_field_if',
         [
           register.bit_field_if,
           bit_field.bit_field_sub_if,

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb

@@ -4,16 +4,16 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc])
   sv_rtl do
     build do
       input :set, {
-        name: "i_#{full_name}_set", data_type: :logic, width: width,
+        name: "i_#{full_name}_set", width: width,
         array_size: array_size, array_format: array_port_format
       }
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
       if bit_field.reference?
         output :value_unmasked, {
-          name: "o_#{full_name}_unmasked", data_type: :logic, width: width,
+          name: "o_#{full_name}_unmasked", width: width,
           array_size: array_size, array_format: array_port_format
         }
       end

data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb

@@ -5,7 +5,7 @@ RgGen.define_list_item_feature(:bit_field, :type, :ro) do
     build do
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", data_type: :logic, width: width,
+          name: "i_#{full_name}", width: width,
           array_size: array_size, array_format: array_port_format
         }
       end

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb

@@ -4,11 +4,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos])
   sv_rtl do
     build do
       input :clear, {
-        name: "i_#{full_name}_clear", data_type: :logic, width: width,
+        name: "i_#{full_name}_clear", width: width,
         array_size: array_size, array_format: array_port_format
       }
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb

@@ -5,12 +5,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
     build do
       unless bit_field.reference?
         input :clear, {
-          name: "i_#{full_name}_clear", data_type: :logic, width: 1,
+          name: "i_#{full_name}_clear", width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/{rwl.erb → rwe_rwl.erb}

@@ -1,12 +1,12 @@
 rggen_bit_field #(
   .WIDTH                    (<%= width %>),
   .INITIAL_VALUE            (<%= initial_value %>),
-  .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_LOW)
+  .SW_WRITE_ENABLE_POLARITY (<%= polarity %>)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
-  .i_sw_write_enable  (<%= lock_signal %>),
+  .i_sw_write_enable  (<%= control_signal %>),
   .i_hw_write_enable  ('0),
   .i_hw_write_data    ('0),
   .i_hw_set           ('0),

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb

@@ -0,0 +1,34 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
+  sv_rtl do
+    build do
+      unless bit_field.reference?
+        input :control, {
+          name: "i_#{full_name}_#{enable_or_lock}", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def enable_or_lock
+      { rwe: :enable, rwl: :lock }[bit_field.type]
+    end
+
+    def control_signal
+      reference_bit_field || control[loop_variables]
+    end
+
+    def polarity
+      { rwe: 'RGGEN_ACTIVE_HIGH', rwl: 'RGGEN_ACTIVE_LOW' }[bit_field.type]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb

@@ -5,16 +5,16 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
     build do
       unless bit_field.reference?
         input :set, {
-          name: "i_#{full_name}_set", data_type: :logic, width: 1,
+          name: "i_#{full_name}_set", width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
       input :value_in, {
-        name: "i_#{full_name}", data_type: :logic, width: width,
+        name: "i_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb

@@ -6,7 +6,7 @@ RgGen.define_list_item_feature(
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
   sv_rtl do
     build do
       output :trigger, {
-        name: "o_#{full_name}_trigger", data_type: :logic, width: width,
+        name: "o_#{full_name}_trigger", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end

data/lib/rggen/systemverilog/rtl/bit_field_index.rb

@@ -15,8 +15,7 @@ module RgGen
         end
 
         def local_index
-          index_name = local_index_name
-          index_name && create_identifier(index_name)
+          create_identifier(local_index_name)
         end
 
         def local_indices

data/lib/rggen/systemverilog/rtl/feature.rb

@@ -16,10 +16,12 @@ module RgGen
           InterfaceInstance.new(attributes, &block)
         end
 
-        def create_argument(direction, attributes, &block)
-          DataObject.new(
-            :argument, attributes.merge(direction: direction), &block
-          )
+        def create_port(direction, attributes, &block)
+          attributes =
+            { data_type: 'logic' }
+              .merge(attributes)
+              .merge(direction: direction)
+          DataObject.new(:argument, attributes, &block)
         end
 
         def create_if_port(_, attributes, &block)
@@ -34,8 +36,8 @@ module RgGen
 
         define_entity :logic, :create_variable, :variable, -> { component }
         define_entity :interface, :create_if_instance, :variable, -> { component }
-        define_entity :input, :create_argument, :port, -> { register_block }
-        define_entity :output, :create_argument, :port, -> { register_block }
+        define_entity :input, :create_port, :port, -> { register_block }
+        define_entity :output, :create_port, :port, -> { register_block }
         define_entity :interface_port, :create_if_port, :port, -> { register_block }
         define_entity :parameter, :create_parameter, :parameter, -> { register_block }
         define_entity :localparam, :create_parameter, :parameter, -> { component }

data/lib/rggen/systemverilog/rtl/partial_sum.rb

@@ -7,12 +7,11 @@ module RgGen
         private
 
         def partial_sums(operands)
-          sums =
-            operands
-              .chunk(&method(:integer?))
-              .flat_map(&method(:calc_partial_sum))
-              .reject { |value| integer?(value) && value.zero? }
-          sums.empty? && [0] || sums
+          operands
+            .chunk(&method(:integer?))
+            .flat_map(&method(:calc_partial_sum))
+            .reject { |value| integer?(value) && value.zero? }
+            .tap { |sums| sums.empty? && (sums << 0) }
         end
 
         def calc_partial_sum(kind_ans_values)

data/lib/rggen/systemverilog/rtl/register/type/external.rb

@@ -11,36 +11,28 @@ RgGen.define_list_item_feature(:register, :type, :external) do
         }
       else
         output :valid, {
-          name: "o_#{register.name}_valid",
-          data_type: :logic, width: 1
+          name: "o_#{register.name}_valid", width: 1
         }
         output :access, {
-          name: "o_#{register.name}_access",
-          data_type: :logic, width: '$bits(rggen_access)'
+          name: "o_#{register.name}_access", width: '$bits(rggen_access)'
         }
         output :address, {
-          name: "o_#{register.name}_address",
-          data_type: :logic, width: address_width
+          name: "o_#{register.name}_address", width: address_width
         }
         output :write_data, {
-          name: "o_#{register.name}_data",
-          data_type: :logic, width: bus_width
+          name: "o_#{register.name}_data", width: bus_width
         }
         output :strobe, {
-          name: "o_#{register.name}_strobe",
-          data_type: :logic, width: byte_width
+          name: "o_#{register.name}_strobe", width: byte_width
         }
         input :ready, {
-          name: "i_#{register.name}_ready",
-          data_type: :logic, width: 1
+          name: "i_#{register.name}_ready", width: 1
         }
         input :status, {
-          name: "i_#{register.name}_status",
-          data_type: :logic, width: 2
+          name: "i_#{register.name}_status", width: 2
         }
         input :read_data, {
-          name: "i_#{register.name}_data",
-          data_type: :logic, width: bus_width
+          name: "i_#{register.name}_data", width: bus_width
         }
         interface :bus_if, {
           name: 'bus_if', interface_type: 'rggen_bus_if',

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb

@@ -27,34 +27,34 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
         }
       else
         input :psel, {
-          name: 'i_psel', data_type: :logic, width: 1
+          name: 'i_psel', width: 1
         }
         input :penable, {
-          name: 'i_penable', data_type: :logic, width: 1
+          name: 'i_penable', width: 1
         }
         input :paddr, {
-          name: 'i_paddr', data_type: :logic, width: address_width
+          name: 'i_paddr', width: address_width
         }
         input :pprot, {
-          name: 'i_pprot', data_type: :logic, width: 3
+          name: 'i_pprot', width: 3
         }
         input :pwrite, {
-          name: 'i_pwrite', data_type: :logic, width: 1
+          name: 'i_pwrite', width: 1
         }
         input :pstrb, {
-          name: 'i_pstrb', data_type: :logic, width: byte_width
+          name: 'i_pstrb', width: byte_width
         }
         input :pwdata, {
-          name: 'i_pwdata', data_type: :logic, width: bus_width
+          name: 'i_pwdata', width: bus_width
         }
         output :pready, {
-          name: 'o_pready', data_type: :logic, width: 1
+          name: 'o_pready', width: 1
         }
         output :prdata, {
-          name: 'o_prdata', data_type: :logic, width: bus_width
+          name: 'o_prdata', width: bus_width
         }
         output :pslverr, {
-          name: 'o_pslverr', data_type: :logic, width: 1
+          name: 'o_pslverr', width: 1
         }
         interface :apb_if, {
           name: 'apb_if', interface_type: 'rggen_apb_if',

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb

@@ -26,73 +26,73 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         }
       else
         input :awvalid, {
-          name: 'i_awvalid', data_type: :logic, width: 1
+          name: 'i_awvalid', width: 1
         }
         output :awready, {
-          name: 'o_awready', data_type: :logic, width: 1
+          name: 'o_awready', width: 1
         }
         input :awid, {
-          name: 'i_awid', data_type: :logic, width: id_port_width
+          name: 'i_awid', width: id_port_width
         }
         input :awaddr, {
-          name: 'i_awaddr', data_type: :logic, width: address_width
+          name: 'i_awaddr', width: address_width
         }
         input :awprot, {
-          name: 'i_awprot', data_type: :logic, width: 3
+          name: 'i_awprot', width: 3
         }
         input :wvalid, {
-          name: 'i_wvalid', data_type: :logic, width: 1
+          name: 'i_wvalid', width: 1
         }
         output :wready, {
-          name: 'o_wready', data_type: :logic, width: 1
+          name: 'o_wready', width: 1
         }
         input :wdata, {
-          name: 'i_wdata', data_type: :logic, width: bus_width
+          name: 'i_wdata', width: bus_width
         }
         input :wstrb, {
-          name: 'i_wstrb', data_type: :logic, width: byte_width
+          name: 'i_wstrb', width: byte_width
         }
         output :bvalid, {
-          name: 'o_bvalid', data_type: :logic, width: 1
+          name: 'o_bvalid', width: 1
         }
         output :bid, {
-          name: 'o_bid', data_type: :logic, width: id_port_width
+          name: 'o_bid', width: id_port_width
         }
         input :bready, {
-          name: 'i_bready', data_type: :logic, width: 1
+          name: 'i_bready', width: 1
         }
         output :bresp, {
-          name: 'o_bresp', data_type: :logic, width: 2
+          name: 'o_bresp', width: 2
         }
         input :arvalid, {
-          name: 'i_arvalid', data_type: :logic, width: 1
+          name: 'i_arvalid', width: 1
         }
         output :arready, {
-          name: 'o_arready', data_type: :logic, width: 1
+          name: 'o_arready', width: 1
         }
         input :arid, {
-          name: 'i_arid', data_type: :logic, width: id_port_width
+          name: 'i_arid', width: id_port_width
         }
         input :araddr, {
-          name: 'i_araddr', data_type: :logic, width: address_width
+          name: 'i_araddr', width: address_width
         }
         input :arprot, {
-          name: 'i_arprot', data_type: :logic, width: 3
+          name: 'i_arprot', width: 3
         }
         output :rvalid, {
-          name: 'o_rvalid', data_type: :logic, width: 1
+          name: 'o_rvalid', width: 1
         }
         input :rready, {
-          name: 'i_rready', data_type: :logic, width: 1
+          name: 'i_rready', width: 1
         }
         output :rid, {
-          name: 'o_rid', data_type: :logic, width: id_port_width
+          name: 'o_rid', width: id_port_width
         }
         output :rdata, {
-          name: 'o_rdata', data_type: :logic, width: bus_width
+          name: 'o_rdata', width: bus_width
         }
         output :rresp, {
-          name: 'o_rresp', data_type: :logic, width: 2
+          name: 'o_rresp', width: 2
         }
         interface :axi4lite_if, {
           name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb

@@ -5,12 +5,8 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
     export :total_registers
 
     build do
-      input :clock, {
-        name: 'i_clk', data_type: :logic, width: 1
-      }
-      input :reset, {
-        name: 'i_rst_n', data_type: :logic, width: 1
-      }
+      input :clock, { name: 'i_clk', width: 1 }
+      input :reset, { name: 'i_rst_n', width: 1 }
       interface :register_if, {
         name: 'register_if', interface_type: 'rggen_register_if',
         parameter_values: [address_width, bus_width, value_width],

data/lib/rggen/systemverilog/rtl/register_index.rb

@@ -50,13 +50,10 @@ module RgGen
         end
 
         def index(offset_or_offsets = nil)
-          operands = index_operands(offset_or_offsets)
-          partial_indices = partial_sums(operands)
-          if partial_indices.empty? || partial_indices.all?(&method(:integer?))
-            partial_indices.sum
-          else
-            partial_indices.join('+')
-          end
+          offset_or_offsets
+            .yield_self(&method(:index_operands))
+            .yield_self(&method(:partial_sums))
+            .yield_self(&method(:reduce_indices))
         end
 
         def inside_loop?
@@ -87,12 +84,17 @@ module RgGen
           ]
         end
 
+        def reduce_indices(indices)
+          if indices.empty? || indices.all?(&method(:integer?))
+            indices.sum
+          else
+            indices.join('+')
+          end
+        end
+
         def local_register_index(offset)
           (component.array? || nil) &&
-            begin
-              operands = [component.count(false), offset || local_index]
-              product(operands, true)
-            end
+            product([component.count(false), offset || local_index], true)
         end
 
         def product(operands, need_bracket)

data/lib/rggen/systemverilog/rtl/register_type.rb

@@ -25,9 +25,10 @@ module RgGen
         end
 
         def offset_address
-          offsets = [*register_files, register].flat_map(&method(:collect_offsets))
-          offsets = partial_sums(offsets)
-          format_offsets(offsets)
+          [*register_files, register]
+            .flat_map(&method(:collect_offsets))
+            .yield_self(&method(:partial_sums))
+            .yield_self(&method(:format_offsets))
         end
 
         def collect_offsets(component)

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.24.0'
+    VERSION = '0.25.0'
   end
 end

metadata

@@ -1,29 +1,15 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.24.0
+  version: 0.25.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2021-01-20 00:00:00.000000000 Z
+date: 2021-02-28 00:00:00.000000000 Z
 dependencies:
-- !ruby/object:Gem::Dependency
-  name: facets
-  requirement: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: '3.0'
-  type: :runtime
-  prerelease: false
-  version_requirements: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: '3.0'
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -69,7 +55,7 @@ files:
 - lib/rggen/systemverilog/common/utility/structure_definition.rb
 - lib/rggen/systemverilog/ral.rb
 - lib/rggen/systemverilog/ral/bit_field/type.rb
-- lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb
+- lib/rggen/systemverilog/ral/bit_field/type/rof.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb
 - lib/rggen/systemverilog/ral/bit_field/type/w0trg_w1trg.rb
@@ -91,8 +77,6 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/ro.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/ro.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
@@ -103,10 +87,8 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rwl.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
@@ -158,7 +140,7 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '2.4'
+      version: '2.5'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
@@ -168,5 +150,5 @@ requirements: []
 rubygems_version: 3.2.3
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.24.0
+summary: rggen-systemverilog-0.25.0
 test_files: []

data/lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb

@@ -1,5 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:reserved, :rof]) do
-  sv_ral { access 'RO' }
-end

data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb

@@ -1,18 +0,0 @@
-rggen_bit_field #(
-  .WIDTH          (<%= width %>),
-  .SW_READ_ACTION (RGGEN_READ_NONE),
-  .STORAGE        (0)
-) u_bit_field (
-  .i_clk              ('0),
-  .i_rst_n            ('0),
-  .bit_field_if       (<%= bit_field_if %>),
-  .i_sw_write_enable  ('0),
-  .i_hw_write_enable  ('0),
-  .i_hw_write_data    ('0),
-  .i_hw_set           ('0),
-  .i_hw_clear         ('0),
-  .i_value            ('0),
-  .i_mask             ('0),
-  .o_value            (),
-  .o_value_unmasked   ()
-);

data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb

@@ -1,7 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :reserved) do
-  sv_rtl do
-    main_code :bit_field, from_template: true
-  end
-end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb

@@ -1,18 +0,0 @@
-rggen_bit_field #(
-  .WIDTH                    (<%= width %>),
-  .INITIAL_VALUE            (<%= initial_value %>),
-  .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_HIGH)
-) u_bit_field (
-  .i_clk              (<%= clock %>),
-  .i_rst_n            (<%= reset %>),
-  .bit_field_if       (<%= bit_field_if %>),
-  .i_sw_write_enable  (<%= enable_signal %>),
-  .i_hw_write_enable  ('0),
-  .i_hw_write_data    ('0),
-  .i_hw_set           ('0),
-  .i_hw_clear         ('0),
-  .i_value            ('0),
-  .i_mask             ('1),
-  .o_value            (<%= value_out[loop_variables] %>),
-  .o_value_unmasked   ()
-);

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb

@@ -1,26 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :rwe) do
-  sv_rtl do
-    build do
-      unless bit_field.reference?
-        input :enable, {
-          name: "i_#{full_name}_enable", data_type: :logic, width: 1,
-          array_size: array_size, array_format: array_port_format
-        }
-      end
-      output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def enable_signal
-      reference_bit_field || enable[loop_variables]
-    end
-  end
-end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb

@@ -1,26 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :rwl) do
-  sv_rtl do
-    build do
-      unless bit_field.reference?
-        input :lock, {
-          name: "i_#{full_name}_lock", data_type: :logic, width: 1,
-          array_size: array_size, array_format: array_port_format
-        }
-      end
-      output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def lock_signal
-      reference_bit_field || lock[loop_variables]
-    end
-  end
-end