rggen-systemverilog 0.23.0 → 0.23.1

checksums.yaml

@@ -1,7 +1,7 @@
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+  data.tar.gz: e8afca21a640eff2ce8f6cfc8058b9b96e87bba16351335c610e01e78a28fe91
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data/README.md

@@ -7,7 +7,7 @@
 
 # RgGen::SystemVerilog
 
-RgGen::SystemVerilog privides SystemVerilog RTL generator and UVM RAL model generator for RgGen.
+RgGen::SystemVerilog provides SystemVerilog RTL and UVM register model (UVM RAL) generators for RgGen.
 
 ## Installation
 

data/lib/rggen/systemverilog/common/utility/identifier.rb

@@ -35,9 +35,9 @@ module RgGen
             @name.to_s
           end
 
-          def [](array_index_or_lsb, width = nil)
+          def [](array_index_or_lsb, lsb_or_width = nil, width = nil)
             if array_index_or_lsb
-              __create_new_identifier__(array_index_or_lsb, width)
+              __create_new_identifier__(array_index_or_lsb, lsb_or_width, width)
             else
               self
             end
@@ -45,35 +45,38 @@ module RgGen
 
           private
 
-          def __create_new_identifier__(array_index_or_lsb, width)
-            select = __create_select__(array_index_or_lsb, width)
+          def __create_new_identifier__(array_index_or_lsb, lsb_or_width, width)
+            select = __create_select__(array_index_or_lsb, lsb_or_width, width)
             Identifier.new("#{@name}#{select}") do |identifier|
               identifier.__sub_identifiers__(@sub_identifiers)
             end
           end
 
-          def __create_select__(array_index_or_lsb, width)
+          def __create_select__(array_index_or_lsb, lsb_or_width, width)
             if array_index_or_lsb.is_a?(::Array)
-              __array_select__(array_index_or_lsb)
-            elsif width
-              "[#{array_index_or_lsb}+:#{width}]"
+              __array_select__(array_index_or_lsb, lsb_or_width, width)
+            elsif lsb_or_width
+              "[#{array_index_or_lsb}+:#{lsb_or_width}]"
             else
               "[#{array_index_or_lsb}]"
             end
           end
 
-          def __array_select__(array_index)
+          def __array_select__(array_index, lsb, width)
             if @array_format == :serialized
-              "[#{__serialized_lsb__(array_index)}+:#{@width}]"
+              "[#{__serialized_lsb__(array_index, lsb)}+:#{width || @width}]"
             else
-              array_index
-                .map { |index| "[#{index}]" }
-                .join
+              [
+                *array_index.map { |index| "[#{index}]" },
+                lsb && __create_select__(lsb, width, nil)
+              ].compact.join
             end
           end
 
-          def __serialized_lsb__(array_index)
-            __reduce_array__([@width, __serialized_index__(array_index)], :*, 1)
+          def __serialized_lsb__(array_index, lsb)
+            serialized_index = __serialized_index__(array_index)
+            array_lsb = __reduce_array__([@width, serialized_index], :*, 1)
+            __reduce_array__([array_lsb, lsb], :+, 0)
           end
 
           def __serialized_index__(array_index)
@@ -97,6 +100,7 @@ module RgGen
           end
 
           def __reduce_array__(array, operator, initial_value)
+            array = array.compact
             if array.all?(&method(:integer?))
               array.reduce(initial_value, &operator)
             else

data/lib/rggen/systemverilog/rtl.rb

@@ -4,6 +4,9 @@ require_relative 'common'
 require_relative 'rtl/feature'
 require_relative 'rtl/partial_sum'
 require_relative 'rtl/register_index'
+require_relative 'rtl/register_type'
+require_relative 'rtl/indirect_index'
+require_relative 'rtl/bit_field_index'
 
 module RgGen
   module SystemVerilog

data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb

@@ -2,10 +2,8 @@
 
 RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
   sv_rtl do
-    export :local_index
-    export :local_indices
-    export :loop_variables
-    export :array_size
+    include RgGen::SystemVerilog::RTL::BitFieldIndex
+
     export :value
 
     build do
@@ -13,13 +11,13 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
         localparam :initial_value, {
           name: initial_value_name, data_type: :bit, width: bit_field.width,
           array_size: initial_value_size, array_format: initial_value_format,
-          default: initial_value_lhs
+          default: initial_value_rhs
         }
       elsif initial_value?
         parameter :initial_value, {
           name: initial_value_name, data_type: :bit, width: bit_field.width,
           array_size: initial_value_size, array_format: initial_value_format,
-          default: initial_value_lhs
+          default: initial_value_rhs
         }
       end
       interface :bit_field_sub_if, {
@@ -42,31 +40,8 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
       code << bit_field_if_connection << nl
     end
 
-    def local_index
-      (index_name = local_index_name) &&
-        create_identifier(index_name)
-    end
-
-    def local_indices
-      [*register.local_indices, local_index_name]
-    end
-
-    def loop_variables
-      (inside_loop? || nil) &&
-        [*register.loop_variables, local_index].compact
-    end
-
-    def array_size
-      (inside_loop? || nil) &&
-        [
-          *register_files.flat_map(&:array_size),
-          *register.array_size,
-          *bit_field.sequence_size
-        ].compact
-    end
-
     def value(offsets = nil, width = nil)
-      value_lsb = bit_field.lsb(offsets&.last || local_index_name)
+      value_lsb = bit_field.lsb(offsets&.last || local_index)
       value_width = width || bit_field.width
       register_if(offsets&.slice(0..-2)).value[value_lsb, value_width]
     end
@@ -77,14 +52,6 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
       define_method(m) { bit_field.__send__(__method__) }
     end
 
-    def local_index_name
-      (bit_field.sequential? || nil) &&
-        begin
-          depth = (register.loop_variables&.size || 0) + 1
-          loop_index(depth)
-        end
-    end
-
     def register_if(offsets)
       index = register.index(offsets || register.local_indices)
       register_block.register_if[index]
@@ -106,11 +73,11 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
         configuration.array_port_format
     end
 
-    def initial_value_lhs
-      initial_value_array? && initial_value_array_lhs || sized_initial_value
+    def initial_value_rhs
+      initial_value_array? && initial_value_array_rhs || sized_initial_value
     end
 
-    def initial_value_array_lhs
+    def initial_value_array_rhs
       if fixed_initial_value?
         array(sized_initial_values)
       elsif initial_value_format == :unpacked
@@ -129,12 +96,9 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
       bit_field.initial_values&.map { |v| hex(v, bit_field.width) }
     end
 
-    def inside_loop?
-      register.array? || bit_field.sequential?
-    end
-
     def loop_size
-      (loop_variable = local_index_name) &&
+      loop_variable = local_index
+      loop_variable &&
         { loop_variable => bit_field.sequence_size }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field_index.rb

@@ -0,0 +1,53 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module BitFieldIndex
+        EXPORTED_METHODS = [
+          :local_index, :local_indices, :loop_variables, :array_size
+        ].freeze
+
+        def self.included(feature)
+          feature.module_eval do
+            EXPORTED_METHODS.each { |m| export m }
+          end
+        end
+
+        def local_index
+          index_name = local_index_name
+          index_name && create_identifier(index_name)
+        end
+
+        def local_indices
+          [*register.local_indices, local_index_name]
+        end
+
+        def loop_variables
+          (inside_loop? || nil) &&
+            [*register.loop_variables, local_index].compact
+        end
+
+        def array_size
+          (inside_loop? || nil) &&
+            [
+              *register_files.flat_map(&:array_size),
+              *register.array_size,
+              *bit_field.sequence_size
+            ].compact
+        end
+
+        private
+
+        def local_index_name
+          (bit_field.sequential? || nil) &&
+            loop_index((register.loop_variables&.size || 0) + 1)
+        end
+
+        def inside_loop?
+          register.inside_loop? || bit_field.sequential?
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/indirect_index.rb

@@ -0,0 +1,35 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module IndirectIndex
+        private
+
+        def index_fields
+          @index_fields ||=
+            register.collect_index_fields(register_block.bit_fields)
+        end
+
+        def index_width
+          @index_width ||= index_fields.sum(&:width)
+        end
+
+        def index_values
+          loop_variables = register.local_loop_variables
+          register.index_entries.zip(index_fields).map do |entry, field|
+            if entry.array_index?
+              loop_variables.shift[0, field.width]
+            else
+              hex(entry.value, field.width)
+            end
+          end
+        end
+
+        def indirect_index_assignment
+          assign(indirect_index, concat(index_fields.map(&:value)))
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/register/type.rb

@@ -3,65 +3,10 @@
 RgGen.define_list_feature(:register, :type) do
   sv_rtl do
     base_feature do
-      include RgGen::SystemVerilog::RTL::PartialSum
+      include RgGen::SystemVerilog::RTL::RegisterType
 
       private
 
-      def readable
-        register.readable? && 1 || 0
-      end
-
-      def writable
-        register.writable? && 1 || 0
-      end
-
-      def bus_width
-        configuration.bus_width
-      end
-
-      def address_width
-        register_block.local_address_width
-      end
-
-      def offset_address
-        offsets = [*register_files, register].flat_map(&method(:collect_offsets))
-        offsets = partial_sums(offsets)
-        format_offsets(offsets)
-      end
-
-      def collect_offsets(component)
-        if component.register_file? && component.array?
-          [component.offset_address, byte_offset(component)]
-        else
-          component.offset_address
-        end
-      end
-
-      def byte_offset(component)
-        "#{component.byte_size(false)}*(#{component.local_index})"
-      end
-
-      def format_offsets(offsets)
-        offsets.map(&method(:format_offset)).join('+')
-      end
-
-      def format_offset(offset)
-        offset.is_a?(Integer) ? hex(offset, address_width) : offset
-      end
-
-      def width
-        register.width
-      end
-
-      def valid_bits
-        bits = register.bit_fields.map(&:bit_map).inject(:|)
-        hex(bits, register.width)
-      end
-
-      def register_index
-        register.local_index || 0
-      end
-
       def register_if
         register_block.register_if[register.index]
       end

data/lib/rggen/systemverilog/rtl/register/type/external.rb

@@ -71,10 +71,6 @@ RgGen.define_list_item_feature(:register, :type, :external) do
 
     private
 
-    def address_width
-      register_block.local_address_width
-    end
-
     def byte_width
       configuration.byte_width
     end

data/lib/rggen/systemverilog/rtl/register/type/indirect.rb

@@ -2,6 +2,8 @@
 
 RgGen.define_list_item_feature(:register, :type, :indirect) do
   sv_rtl do
+    include RgGen::SystemVerilog::RTL::IndirectIndex
+
     build do
       logic :indirect_index, { width: index_width }
     end
@@ -10,31 +12,5 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
       code << indirect_index_assignment << nl
       code << process_template
     end
-
-    private
-
-    def index_fields
-      @index_fields ||=
-        register.collect_index_fields(register_block.bit_fields)
-    end
-
-    def index_width
-      @index_width ||= index_fields.sum(&:width)
-    end
-
-    def index_values
-      loop_variables = register.local_loop_variables
-      register.index_entries.zip(index_fields).map do |entry, field|
-        if entry.array_index?
-          loop_variables.shift[0, field.width]
-        else
-          hex(entry.value, field.width)
-        end
-      end
-    end
-
-    def indirect_index_assignment
-      assign(indirect_index, concat(index_fields.map(&:value)))
-    end
   end
 end

data/lib/rggen/systemverilog/rtl/register_block/protocol.rb

@@ -2,19 +2,25 @@
 
 RgGen.define_list_feature(:register_block, :protocol) do
   shared_context do
-    def feature_registry(registry = nil)
-      @registry = registry if registry
-      @registry
+    def feature_registry(registry)
+      feature_registries << registry
     end
 
     def available_protocols
-      feature_registry
-        .enabled_features(:protocol)
-        .select(&method(:valid_protocol?))
+      feature_registries
+        .map(&method(:collect_available_protocols)).inject(:&)
     end
 
-    def valid_protocol?(protocol)
-      feature_registry.feature?(:protocol, protocol)
+    private
+
+    def feature_registries
+      @feature_registries ||= []
+    end
+
+    def collect_available_protocols(registry)
+      registry
+        .enabled_features(:protocol)
+        .select { |protocol| registry.feature?(:protocol, protocol) }
     end
   end
 

data/lib/rggen/systemverilog/rtl/register_index.rb

@@ -9,7 +9,7 @@ module RgGen
         EXPORTED_METHODS = [
           :loop_variables, :local_loop_variables,
           :local_index, :local_indices,
-          :index, :inside_roop?
+          :index, :inside_loop?
         ].freeze
 
         def self.included(feature)
@@ -23,7 +23,7 @@ module RgGen
         end
 
         def loop_variables
-          (inside_roop? || nil) &&
+          (inside_loop? || nil) &&
             [*upper_register_file&.loop_variables, *local_loop_variables]
         end
 
@@ -59,8 +59,8 @@ module RgGen
           end
         end
 
-        def inside_roop?
-          component.array? || upper_register_file&.inside_roop? || false
+        def inside_loop?
+          component.array? || upper_register_file&.inside_loop? || false
         end
 
         private

data/lib/rggen/systemverilog/rtl/register_type.rb

@@ -0,0 +1,68 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module RegisterType
+        include PartialSum
+
+        private
+
+        def readable
+          register.readable? && 1 || 0
+        end
+
+        def writable
+          register.writable? && 1 || 0
+        end
+
+        def bus_width
+          configuration.bus_width
+        end
+
+        def address_width
+          register_block.local_address_width
+        end
+
+        def offset_address
+          offsets = [*register_files, register].flat_map(&method(:collect_offsets))
+          offsets = partial_sums(offsets)
+          format_offsets(offsets)
+        end
+
+        def collect_offsets(component)
+          if component.register_file? && component.array?
+            [component.offset_address, byte_offset(component)]
+          else
+            component.offset_address
+          end
+        end
+
+        def byte_offset(component)
+          "#{component.byte_size(false)}*(#{component.local_index})"
+        end
+
+        def format_offsets(offsets)
+          offsets.map(&method(:format_offset)).join('+')
+        end
+
+        def format_offset(offset)
+          offset.is_a?(Integer) ? hex(offset, address_width) : offset
+        end
+
+        def width
+          register.width
+        end
+
+        def valid_bits
+          bits = register.bit_fields.map(&:bit_map).inject(:|)
+          hex(bits, register.width)
+        end
+
+        def register_index
+          register.local_index || 0
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.23.0'
+    VERSION = '0.23.1'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.23.0
+  version: 0.23.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2020-08-25 00:00:00.000000000 Z
+date: 2020-10-24 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: docile
@@ -133,9 +133,11 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb
+- lib/rggen/systemverilog/rtl/bit_field_index.rb
 - lib/rggen/systemverilog/rtl/feature.rb
 - lib/rggen/systemverilog/rtl/global/array_port_format.rb
 - lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
+- lib/rggen/systemverilog/rtl/indirect_index.rb
 - lib/rggen/systemverilog/rtl/partial_sum.rb
 - lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register/type.rb
@@ -153,6 +155,7 @@ files:
 - lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register_index.rb
+- lib/rggen/systemverilog/rtl/register_type.rb
 - lib/rggen/systemverilog/rtl/setup.rb
 - lib/rggen/systemverilog/version.rb
 homepage: https://github.com/rggen/rggen-systemverilog
@@ -181,5 +184,5 @@ requirements: []
 rubygems_version: 3.1.2
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.23.0
+summary: rggen-systemverilog-0.23.1
 test_files: []