rggen-systemverilog 0.20.0 → 0.23.1

checksums.yaml

@@ -1,7 +1,7 @@
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data/README.md

@@ -7,7 +7,7 @@
 
 # RgGen::SystemVerilog
 
-RgGen::SystemVerilog privides SystemVerilog RTL generator and UVM RAL model generator for RgGen.
+RgGen::SystemVerilog provides SystemVerilog RTL and UVM register model (UVM RAL) generators for RgGen.
 
 ## Installation
 

data/lib/rggen/systemverilog/common/utility.rb

@@ -45,6 +45,10 @@ module RgGen
           end
         end
 
+        def all_bits_0
+          "'0"
+        end
+
         def bin(value, width = nil)
           if width
             width = bit_width(value, width)

data/lib/rggen/systemverilog/common/utility/identifier.rb

@@ -35,9 +35,9 @@ module RgGen
             @name.to_s
           end
 
-          def [](array_index_or_lsb, width = nil)
+          def [](array_index_or_lsb, lsb_or_width = nil, width = nil)
             if array_index_or_lsb
-              __create_new_identifier__(array_index_or_lsb, width)
+              __create_new_identifier__(array_index_or_lsb, lsb_or_width, width)
             else
               self
             end
@@ -45,35 +45,38 @@ module RgGen
 
           private
 
-          def __create_new_identifier__(array_index_or_lsb, width)
-            select = __create_select__(array_index_or_lsb, width)
+          def __create_new_identifier__(array_index_or_lsb, lsb_or_width, width)
+            select = __create_select__(array_index_or_lsb, lsb_or_width, width)
             Identifier.new("#{@name}#{select}") do |identifier|
               identifier.__sub_identifiers__(@sub_identifiers)
             end
           end
 
-          def __create_select__(array_index_or_lsb, width)
+          def __create_select__(array_index_or_lsb, lsb_or_width, width)
             if array_index_or_lsb.is_a?(::Array)
-              __array_select__(array_index_or_lsb)
-            elsif width
-              "[#{array_index_or_lsb}+:#{width}]"
+              __array_select__(array_index_or_lsb, lsb_or_width, width)
+            elsif lsb_or_width
+              "[#{array_index_or_lsb}+:#{lsb_or_width}]"
             else
               "[#{array_index_or_lsb}]"
             end
           end
 
-          def __array_select__(array_index)
+          def __array_select__(array_index, lsb, width)
             if @array_format == :serialized
-              "[#{__serialized_lsb__(array_index)}+:#{@width}]"
+              "[#{__serialized_lsb__(array_index, lsb)}+:#{width || @width}]"
             else
-              array_index
-                .map { |index| "[#{index}]" }
-                .join
+              [
+                *array_index.map { |index| "[#{index}]" },
+                lsb && __create_select__(lsb, width, nil)
+              ].compact.join
             end
           end
 
-          def __serialized_lsb__(array_index)
-            __reduce_array__([@width, __serialized_index__(array_index)], :*, 1)
+          def __serialized_lsb__(array_index, lsb)
+            serialized_index = __serialized_index__(array_index)
+            array_lsb = __reduce_array__([@width, serialized_index], :*, 1)
+            __reduce_array__([array_lsb, lsb], :+, 0)
           end
 
           def __serialized_index__(array_index)
@@ -97,6 +100,7 @@ module RgGen
           end
 
           def __reduce_array__(array, operator, initial_value)
+            array = array.compact
             if array.all?(&method(:integer?))
               array.reduce(initial_value, &operator)
             else

data/lib/rggen/systemverilog/ral.rb

@@ -7,6 +7,8 @@ require_relative 'ral/register_common'
 module RgGen
   module SystemVerilog
     module RAL
+      PLUGIN_NAME = :'rggen-sv-ral'
+
       FEATURES = [
         'ral/bit_field/type',
         'ral/bit_field/type/reserved_rof',

data/lib/rggen/systemverilog/ral/setup.rb

@@ -2,7 +2,7 @@
 
 require 'rggen/systemverilog/ral'
 
-RgGen.setup :'rggen-sv-ral', RgGen::SystemVerilog::RAL do |builder|
+RgGen.setup RgGen::SystemVerilog::RAL do |builder|
   builder.enable :register_block, [:sv_ral_model, :sv_ral_package]
   builder.enable :register_file, [:sv_ral_model]
 end

data/lib/rggen/systemverilog/rtl.rb

@@ -4,26 +4,33 @@ require_relative 'common'
 require_relative 'rtl/feature'
 require_relative 'rtl/partial_sum'
 require_relative 'rtl/register_index'
+require_relative 'rtl/register_type'
+require_relative 'rtl/indirect_index'
+require_relative 'rtl/bit_field_index'
 
 module RgGen
   module SystemVerilog
     module RTL
+      PLUGIN_NAME = :'rggen-sv-rtl'
+
       FEATURES = [
         'rtl/bit_field/sv_rtl_top',
         'rtl/bit_field/type',
-        'rtl/bit_field/type/rc_w0c_w1c',
+        'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
         'rtl/bit_field/type/reserved',
         'rtl/bit_field/type/ro',
         'rtl/bit_field/type/rof',
-        'rtl/bit_field/type/rs_w0s_w1s',
+        'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
         'rtl/bit_field/type/rw_w1_wo_wo1',
         'rtl/bit_field/type/rwc',
         'rtl/bit_field/type/rwe',
         'rtl/bit_field/type/rwl',
         'rtl/bit_field/type/rws',
-        'rtl/bit_field/type/w0crs_w1crs',
-        'rtl/bit_field/type/w0src_w1src',
+        'rtl/bit_field/type/w0crs_w1crs_wcrs',
+        'rtl/bit_field/type/w0src_w1src_wsrc',
+        'rtl/bit_field/type/w0t_w1t',
         'rtl/bit_field/type/w0trg_w1trg',
+        'rtl/bit_field/type/wrc_wrs',
         'rtl/global/array_port_format',
         'rtl/global/fold_sv_interface_port',
         'rtl/register/sv_rtl_top',

data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb

@@ -2,10 +2,8 @@
 
 RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
   sv_rtl do
-    export :local_index
-    export :local_indices
-    export :loop_variables
-    export :array_size
+    include RgGen::SystemVerilog::RTL::BitFieldIndex
+
     export :value
 
     build do
@@ -13,13 +11,13 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
         localparam :initial_value, {
           name: initial_value_name, data_type: :bit, width: bit_field.width,
           array_size: initial_value_size, array_format: initial_value_format,
-          default: initial_value_lhs
+          default: initial_value_rhs
         }
       elsif initial_value?
         parameter :initial_value, {
           name: initial_value_name, data_type: :bit, width: bit_field.width,
           array_size: initial_value_size, array_format: initial_value_format,
-          default: initial_value_lhs
+          default: initial_value_rhs
         }
       end
       interface :bit_field_sub_if, {
@@ -42,31 +40,8 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
       code << bit_field_if_connection << nl
     end
 
-    def local_index
-      (index_name = local_index_name) &&
-        create_identifier(index_name)
-    end
-
-    def local_indices
-      [*register.local_indices, local_index_name]
-    end
-
-    def loop_variables
-      (inside_loop? || nil) &&
-        [*register.loop_variables, local_index].compact
-    end
-
-    def array_size
-      (inside_loop? || nil) &&
-        [
-          *register_files.flat_map(&:array_size),
-          *register.array_size,
-          *bit_field.sequence_size
-        ].compact
-    end
-
     def value(offsets = nil, width = nil)
-      value_lsb = bit_field.lsb(offsets&.last || local_index_name)
+      value_lsb = bit_field.lsb(offsets&.last || local_index)
       value_width = width || bit_field.width
       register_if(offsets&.slice(0..-2)).value[value_lsb, value_width]
     end
@@ -77,14 +52,6 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
       define_method(m) { bit_field.__send__(__method__) }
     end
 
-    def local_index_name
-      (bit_field.sequential? || nil) &&
-        begin
-          depth = (register.loop_variables&.size || 0) + 1
-          loop_index(depth)
-        end
-    end
-
     def register_if(offsets)
       index = register.index(offsets || register.local_indices)
       register_block.register_if[index]
@@ -106,11 +73,11 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
         configuration.array_port_format
     end
 
-    def initial_value_lhs
-      initial_value_array? && initial_value_array_lhs || sized_initial_value
+    def initial_value_rhs
+      initial_value_array? && initial_value_array_rhs || sized_initial_value
     end
 
-    def initial_value_array_lhs
+    def initial_value_array_rhs
       if fixed_initial_value?
         array(sized_initial_values)
       elsif initial_value_format == :unpacked
@@ -129,12 +96,9 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
       bit_field.initial_values&.map { |v| hex(v, bit_field.width) }
     end
 
-    def inside_loop?
-      register.array? || bit_field.sequential?
-    end
-
     def loop_size
-      (loop_variable = local_index_name) &&
+      loop_variable = local_index
+      loop_variable &&
         { loop_variable => bit_field.sequence_size }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/{rc_w0c_w1c.erb → rc_w0c_w1c_wc_woc.erb}

@@ -1,6 +1,7 @@
 <%= module_name %> #(
-<% if [:w0c, :w1c].include?(bit_field.type) %>
+<% if bit_field.type != :rc %>
   .CLEAR_VALUE    (<%= clear_value %>),
+  .WRITE_ONLY     (<%= write_only %>),
 <% end %>
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)

data/lib/rggen/systemverilog/rtl/bit_field/type/{rc_w0c_w1c.rb → rc_w0c_w1c_wc_woc.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc]) do
   sv_rtl do
     build do
       input :set, {
@@ -24,15 +24,16 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
     private
 
     def module_name
-      if bit_field.type == :rc
-        'rggen_bit_field_rc'
-      else
-        'rggen_bit_field_w01c'
-      end
+      bit_field.type == :rc && 'rggen_bit_field_rc' || 'rggen_bit_field_w01c_wc_woc'
     end
 
     def clear_value
-      bin({ w0c: 0, w1c: 1 }[bit_field.type], 1)
+      value = { w0c: 0b00, w1c: 0b01, wc: 0b10, woc: 0b10 }[bit_field.type]
+      bin(value, 2)
+    end
+
+    def write_only
+      bit_field.write_only? && 1 || 0
     end
 
     def value_out_unmasked

data/lib/rggen/systemverilog/rtl/bit_field/type/{rs_w0s_w1s.erb → rs_w0s_w1s_ws_wos.erb}

@@ -1,6 +1,7 @@
 <%= module_name %> #(
-<% if [:w0s, :w1s].include?(bit_field.type) %>
+<% if bit_field.type != :rs %>
   .SET_VALUE      (<%= set_value %>),
+  .WRITE_ONLY     (<%= write_only %>),
 <% end %>
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)

data/lib/rggen/systemverilog/rtl/bit_field/type/{rs_w0s_w1s.rb → rs_w0s_w1s_ws_wos.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos]) do
   sv_rtl do
     build do
       input :clear, {
@@ -18,15 +18,16 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
     private
 
     def module_name
-      if bit_field.type == :rs
-        'rggen_bit_field_rs'
-      else
-        'rggen_bit_field_w01s'
-      end
+      bit_field.type == :rs && 'rggen_bit_field_rs' || 'rggen_bit_field_w01s_ws_wos'
     end
 
     def set_value
-      bin({ w0s: 0, w1s: 1 }[bit_field.type], 1)
+      value = { w0s: 0b00, w1s: 0b01, ws: 0b10, wos: 0b10 }[bit_field.type]
+      bin(value, 2)
+    end
+
+    def write_only
+      bit_field.write_only? && 1 || 0
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/{w0crs_w1crs.erb → w0crs_w1crs_wcrs.erb}

@@ -1,4 +1,4 @@
-rggen_bit_field_w01crs #(
+rggen_bit_field_w01crs_wcrs #(
   .CLEAR_VALUE    (<%= clear_value %>),
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)

data/lib/rggen/systemverilog/rtl/bit_field/type/{w0crs_w1crs.rb → w0crs_w1crs_wcrs.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs, :wcrs]) do
   sv_rtl do
     build do
       output :value_out, {
@@ -14,8 +14,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
     private
 
     def clear_value
-      value = (bit_field.type == :w0crs && 0) || 1
-      bin(value, 1)
+      value = { w0crs: 0b00, w1crs: 0b01, wcrs: 0b10 }[bit_field.type]
+      bin(value, 2)
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/{w0src_w1src.erb → w0src_w1src_wsrc.erb}

@@ -1,4 +1,4 @@
-rggen_bit_field_w01src #(
+rggen_bit_field_w01src_wsrc #(
   .SET_VALUE      (<%= set_value %>),
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)

data/lib/rggen/systemverilog/rtl/bit_field/type/{w0src_w1src.rb → w0src_w1src_wsrc.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src, :wsrc]) do
   sv_rtl do
     build do
       output :value_out, {
@@ -14,8 +14,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
     private
 
     def set_value
-      value = (bit_field.type == :w0src && 0) || 1
-      bin(value, 1)
+      value = { w0src: 0b00, w1src: 0b01, wsrc: 0b10 }[bit_field.type]
+      bin(value, 2)
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb

@@ -0,0 +1,10 @@
+rggen_bit_field_w01t #(
+  .TOGGLE_VALUE   (<%= toggle_value %>),
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .o_value      (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb

@@ -0,0 +1,20 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def toggle_value
+      bin({ w0t: 0, w1t: 1 }[bit_field.type], 1)
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb

@@ -0,0 +1,9 @@
+rggen_bit_field_<%= bit_field.type %> #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .o_value      (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb

@@ -0,0 +1,14 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field_index.rb

@@ -0,0 +1,53 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module BitFieldIndex
+        EXPORTED_METHODS = [
+          :local_index, :local_indices, :loop_variables, :array_size
+        ].freeze
+
+        def self.included(feature)
+          feature.module_eval do
+            EXPORTED_METHODS.each { |m| export m }
+          end
+        end
+
+        def local_index
+          index_name = local_index_name
+          index_name && create_identifier(index_name)
+        end
+
+        def local_indices
+          [*register.local_indices, local_index_name]
+        end
+
+        def loop_variables
+          (inside_loop? || nil) &&
+            [*register.loop_variables, local_index].compact
+        end
+
+        def array_size
+          (inside_loop? || nil) &&
+            [
+              *register_files.flat_map(&:array_size),
+              *register.array_size,
+              *bit_field.sequence_size
+            ].compact
+        end
+
+        private
+
+        def local_index_name
+          (bit_field.sequential? || nil) &&
+            loop_index((register.loop_variables&.size || 0) + 1)
+        end
+
+        def inside_loop?
+          register.inside_loop? || bit_field.sequential?
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/indirect_index.rb

@@ -0,0 +1,35 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module IndirectIndex
+        private
+
+        def index_fields
+          @index_fields ||=
+            register.collect_index_fields(register_block.bit_fields)
+        end
+
+        def index_width
+          @index_width ||= index_fields.sum(&:width)
+        end
+
+        def index_values
+          loop_variables = register.local_loop_variables
+          register.index_entries.zip(index_fields).map do |entry, field|
+            if entry.array_index?
+              loop_variables.shift[0, field.width]
+            else
+              hex(entry.value, field.width)
+            end
+          end
+        end
+
+        def indirect_index_assignment
+          assign(indirect_index, concat(index_fields.map(&:value)))
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/register/type.rb

@@ -3,65 +3,10 @@
 RgGen.define_list_feature(:register, :type) do
   sv_rtl do
     base_feature do
-      include RgGen::SystemVerilog::RTL::PartialSum
+      include RgGen::SystemVerilog::RTL::RegisterType
 
       private
 
-      def readable
-        register.readable? && 1 || 0
-      end
-
-      def writable
-        register.writable? && 1 || 0
-      end
-
-      def bus_width
-        configuration.bus_width
-      end
-
-      def address_width
-        register_block.local_address_width
-      end
-
-      def offset_address
-        offsets = [*register_files, register].flat_map(&method(:collect_offsets))
-        offsets = partial_sums(offsets)
-        format_offsets(offsets)
-      end
-
-      def collect_offsets(component)
-        if component.register_file? && component.array?
-          [component.offset_address, byte_offset(component)]
-        else
-          component.offset_address
-        end
-      end
-
-      def byte_offset(component)
-        "#{component.byte_size(false)}*(#{component.local_index})"
-      end
-
-      def format_offsets(offsets)
-        offsets.map(&method(:format_offset)).join('+')
-      end
-
-      def format_offset(offset)
-        offset.is_a?(Integer) ? hex(offset, address_width) : offset
-      end
-
-      def width
-        register.width
-      end
-
-      def valid_bits
-        bits = register.bit_fields.map(&:bit_map).inject(:|)
-        hex(bits, register.width)
-      end
-
-      def register_index
-        register.local_index || 0
-      end
-
       def register_if
         register_block.register_if[register.index]
       end

data/lib/rggen/systemverilog/rtl/register/type/external.rb

@@ -71,10 +71,6 @@ RgGen.define_list_item_feature(:register, :type, :external) do
 
     private
 
-    def address_width
-      register_block.local_address_width
-    end
-
     def byte_width
       configuration.byte_width
     end

data/lib/rggen/systemverilog/rtl/register/type/indirect.rb

@@ -2,6 +2,8 @@
 
 RgGen.define_list_item_feature(:register, :type, :indirect) do
   sv_rtl do
+    include RgGen::SystemVerilog::RTL::IndirectIndex
+
     build do
       logic :indirect_index, { width: index_width }
     end
@@ -10,31 +12,5 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
       code << indirect_index_assignment << nl
       code << process_template
     end
-
-    private
-
-    def index_fields
-      @index_fields ||=
-        register.collect_index_fields(register_block.bit_fields)
-    end
-
-    def index_width
-      @index_width ||= index_fields.map(&:width).sum
-    end
-
-    def index_values
-      loop_variables = register.local_loop_variables
-      register.index_entries.zip(index_fields).map do |entry, field|
-        if entry.array_index?
-          loop_variables.shift[0, field.width]
-        else
-          hex(entry.value, field.width)
-        end
-      end
-    end
-
-    def indirect_index_assignment
-      assign(indirect_index, concat(index_fields.map(&:value)))
-    end
   end
 end

data/lib/rggen/systemverilog/rtl/register_block/protocol.rb

@@ -2,19 +2,25 @@
 
 RgGen.define_list_feature(:register_block, :protocol) do
   shared_context do
-    def feature_registry(registry = nil)
-      @registry = registry if registry
-      @registry
+    def feature_registry(registry)
+      feature_registries << registry
     end
 
     def available_protocols
-      feature_registry
-        .enabled_features(:protocol)
-        .select(&method(:valid_protocol?))
+      feature_registries
+        .map(&method(:collect_available_protocols)).inject(:&)
+    end
+
+    private
+
+    def feature_registries
+      @feature_registries ||= []
     end
 
-    def valid_protocol?(protocol)
-      feature_registry.feature?(:protocol, protocol)
+    def collect_available_protocols(registry)
+      registry
+        .enabled_features(:protocol)
+        .select { |protocol| registry.feature?(:protocol, protocol) }
     end
   end
 
@@ -65,21 +71,27 @@ RgGen.define_list_feature(:register_block, :protocol) do
 
     base_feature do
       build do
+        parameter :address_width, {
+          name: 'ADDRESS_WIDTH', data_type: :int, default: local_address_width
+        }
+        parameter :pre_decode, {
+          name: 'PRE_DECODE', data_type: :bit, width: 1, default: 0
+        }
+        parameter :base_address, {
+          name: 'BASE_ADDRESS', data_type: :bit, width: address_width,
+          default: all_bits_0
+        }
         parameter :error_status, {
           name: 'ERROR_STATUS', data_type: :bit, width: 1, default: 0
         }
         parameter :default_read_data, {
           name: 'DEFAULT_READ_DATA', data_type: :bit, width: bus_width,
-          default: hex(0, bus_width)
+          default: all_bits_0
         }
       end
 
       private
 
-      def address_width
-        configuration.address_width
-      end
-
       def bus_width
         configuration.bus_width
       end
@@ -96,6 +108,10 @@ RgGen.define_list_feature(:register_block, :protocol) do
         register_block.total_registers
       end
 
+      def byte_size
+        register_block.byte_size
+      end
+
       def clock
         register_block.clock
       end

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb

@@ -1,9 +1,13 @@
 rggen_apb_adapter #(
-  .ADDRESS_WIDTH      (<%= local_address_width %>),
-  .BUS_WIDTH          (<%= bus_width %>),
-  .REGISTERS          (<%= total_registers %>),
-  .ERROR_STATUS       (<%= error_status %>),
-  .DEFAULT_READ_DATA  (<%= default_read_data %>)
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .REGISTERS            (<%= total_registers %>),
+  .PRE_DECODE           (<%= pre_decode %>),
+  .BASE_ADDRESS         (<%= base_address %>),
+  .BYTE_SIZE            (<%= byte_size %>),
+  .ERROR_STATUS         (<%= error_status %>),
+  .DEFAULT_READ_DATA    (<%= default_read_data %>)
 ) u_adapter (
   .i_clk        (<%= clock %>),
   .i_rst_n      (<%= reset %>),

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb

@@ -1,10 +1,15 @@
 rggen_axi4lite_adapter #(
-  .ADDRESS_WIDTH      (<%= local_address_width %>),
-  .BUS_WIDTH          (<%= bus_width %>),
-  .REGISTERS          (<%= total_registers %>),
-  .ERROR_STATUS       (<%= error_status %>),
-  .DEFAULT_READ_DATA  (<%= default_read_data %>),
-  .WRITE_FIRST        (<%= write_first %>)
+  .ID_WIDTH             (<%= id_width %>),
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .REGISTERS            (<%= total_registers %>),
+  .PRE_DECODE           (<%= pre_decode %>),
+  .BASE_ADDRESS         (<%= base_address %>),
+  .BYTE_SIZE            (<%= byte_size %>),
+  .ERROR_STATUS         (<%= error_status %>),
+  .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .WRITE_FIRST          (<%= write_first %>)
 ) u_adapter (
   .i_clk        (<%= clock %>),
   .i_rst_n      (<%= reset %>),

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb

@@ -13,6 +13,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
 
   sv_rtl do
     build do
+      parameter :id_width, {
+        name: 'ID_WIDTH', data_type: :int, default: 0
+      }
       parameter :write_first, {
         name: 'WRITE_FIRST', data_type: :bit, default: 1
       }
@@ -28,6 +31,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         output :awready, {
           name: 'o_awready', data_type: :logic, width: 1
         }
+        input :awid, {
+          name: 'i_awid', data_type: :logic, width: id_port_width
+        }
         input :awaddr, {
           name: 'i_awaddr', data_type: :logic, width: address_width
         }
@@ -49,6 +55,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         output :bvalid, {
           name: 'o_bvalid', data_type: :logic, width: 1
         }
+        output :bid, {
+          name: 'o_bid', data_type: :logic, width: id_port_width
+        }
         input :bready, {
           name: 'i_bready', data_type: :logic, width: 1
         }
@@ -61,6 +70,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         output :arready, {
           name: 'o_arready', data_type: :logic, width: 1
         }
+        input :arid, {
+          name: 'i_arid', data_type: :logic, width: id_port_width
+        }
         input :araddr, {
           name: 'i_araddr', data_type: :logic, width: address_width
         }
@@ -73,6 +85,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         input :rready, {
           name: 'i_rready', data_type: :logic, width: 1
         }
+        output :rid, {
+          name: 'o_rid', data_type: :logic, width: id_port_width
+        }
         output :rdata, {
           name: 'o_rdata', data_type: :logic, width: bus_width
         }
@@ -81,13 +96,13 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         }
         interface :axi4lite_if, {
           name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',
-          parameter_values: [address_width, bus_width],
+          parameter_values: [id_width, address_width, bus_width],
           variables: [
-            'awvalid', 'awready', 'awaddr', 'awprot',
+            'awvalid', 'awready', 'awid', 'awaddr', 'awprot',
             'wvalid', 'wready', 'wdata', 'wstrb',
-            'bvalid', 'bready', 'bresp',
-            'arvalid', 'arready', 'araddr', 'arprot',
-            'rvalid', 'rready', 'rdata', 'rresp'
+            'bvalid', 'bready', 'bid', 'bresp',
+            'arvalid', 'arready', 'arid', 'araddr', 'arprot',
+            'rvalid', 'rready', 'rid', 'rdata', 'rresp'
           ]
         }
       end
@@ -99,6 +114,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         [
           [axi4lite_if.awvalid, awvalid],
           [awready, axi4lite_if.awready],
+          [axi4lite_if.awid, awid],
           [axi4lite_if.awaddr, awaddr],
           [axi4lite_if.awprot, awprot],
           [axi4lite_if.wvalid, wvalid],
@@ -107,17 +123,26 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
           [axi4lite_if.wstrb, wstrb],
           [bvalid, axi4lite_if.bvalid],
           [axi4lite_if.bready, bready],
+          [bid, axi4lite_if.bid],
           [bresp, axi4lite_if.bresp],
           [axi4lite_if.arvalid, arvalid],
           [arready, axi4lite_if.arready],
+          [axi4lite_if.arid, arid],
           [axi4lite_if.araddr, araddr],
           [axi4lite_if.arprot, arprot],
           [rvalid, axi4lite_if.rvalid],
           [axi4lite_if.rready, rready],
+          [rid, axi4lite_if.rid],
           [rdata, axi4lite_if.rdata],
           [rresp, axi4lite_if.rresp]
         ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
       end
     end
+
+    private
+
+    def id_port_width
+      "((#{id_width}>0)?#{id_width}:1)"
+    end
   end
 end

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb

@@ -23,7 +23,7 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
     end
 
     def total_registers
-      register_block.files_and_registers.map(&:count).sum
+      register_block.files_and_registers.sum(&:count)
     end
 
     private

data/lib/rggen/systemverilog/rtl/register_index.rb

@@ -9,7 +9,7 @@ module RgGen
         EXPORTED_METHODS = [
           :loop_variables, :local_loop_variables,
           :local_index, :local_indices,
-          :index, :inside_roop?
+          :index, :inside_loop?
         ].freeze
 
         def self.included(feature)
@@ -23,7 +23,7 @@ module RgGen
         end
 
         def loop_variables
-          (inside_roop? || nil) &&
+          (inside_loop? || nil) &&
             [*upper_register_file&.loop_variables, *local_loop_variables]
         end
 
@@ -59,8 +59,8 @@ module RgGen
           end
         end
 
-        def inside_roop?
-          component.array? || upper_register_file&.inside_roop? || false
+        def inside_loop?
+          component.array? || upper_register_file&.inside_loop? || false
         end
 
         private

data/lib/rggen/systemverilog/rtl/register_type.rb

@@ -0,0 +1,68 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module RegisterType
+        include PartialSum
+
+        private
+
+        def readable
+          register.readable? && 1 || 0
+        end
+
+        def writable
+          register.writable? && 1 || 0
+        end
+
+        def bus_width
+          configuration.bus_width
+        end
+
+        def address_width
+          register_block.local_address_width
+        end
+
+        def offset_address
+          offsets = [*register_files, register].flat_map(&method(:collect_offsets))
+          offsets = partial_sums(offsets)
+          format_offsets(offsets)
+        end
+
+        def collect_offsets(component)
+          if component.register_file? && component.array?
+            [component.offset_address, byte_offset(component)]
+          else
+            component.offset_address
+          end
+        end
+
+        def byte_offset(component)
+          "#{component.byte_size(false)}*(#{component.local_index})"
+        end
+
+        def format_offsets(offsets)
+          offsets.map(&method(:format_offset)).join('+')
+        end
+
+        def format_offset(offset)
+          offset.is_a?(Integer) ? hex(offset, address_width) : offset
+        end
+
+        def width
+          register.width
+        end
+
+        def valid_bits
+          bits = register.bit_fields.map(&:bit_map).inject(:|)
+          hex(bits, register.width)
+        end
+
+        def register_index
+          register.local_index || 0
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/setup.rb

@@ -2,7 +2,7 @@
 
 require 'rggen/systemverilog/rtl'
 
-RgGen.setup :'rggen-sv-rtl', RgGen::SystemVerilog::RTL do |builder|
+RgGen.setup RgGen::SystemVerilog::RTL do |builder|
   builder.enable :global, [
     :array_port_format, :fold_sv_interface_port
   ]

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.20.0'
+    VERSION = '0.23.1'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.20.0
+  version: 0.23.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2020-07-06 00:00:00.000000000 Z
+date: 2020-10-24 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: docile
@@ -103,16 +103,16 @@ files:
 - lib/rggen/systemverilog/rtl.rb
 - lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/bit_field/type.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/ro.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/ro.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb
@@ -123,15 +123,21 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs_wcrs.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs_wcrs.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src_wsrc.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src_wsrc.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb
+- lib/rggen/systemverilog/rtl/bit_field_index.rb
 - lib/rggen/systemverilog/rtl/feature.rb
 - lib/rggen/systemverilog/rtl/global/array_port_format.rb
 - lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
+- lib/rggen/systemverilog/rtl/indirect_index.rb
 - lib/rggen/systemverilog/rtl/partial_sum.rb
 - lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register/type.rb
@@ -149,6 +155,7 @@ files:
 - lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register_index.rb
+- lib/rggen/systemverilog/rtl/register_type.rb
 - lib/rggen/systemverilog/rtl/setup.rb
 - lib/rggen/systemverilog/version.rb
 homepage: https://github.com/rggen/rggen-systemverilog
@@ -177,5 +184,5 @@ requirements: []
 rubygems_version: 3.1.2
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.20.0
+summary: rggen-systemverilog-0.23.1
 test_files: []