rggen-systemverilog 0.20.0 → 0.23.1

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Files changed (35) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +1 -1
  3. data/lib/rggen/systemverilog/common/utility.rb +4 -0
  4. data/lib/rggen/systemverilog/common/utility/identifier.rb +19 -15
  5. data/lib/rggen/systemverilog/ral.rb +2 -0
  6. data/lib/rggen/systemverilog/ral/setup.rb +1 -1
  7. data/lib/rggen/systemverilog/rtl.rb +11 -4
  8. data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +10 -46
  9. data/lib/rggen/systemverilog/rtl/bit_field/type/{rc_w0c_w1c.erb → rc_w0c_w1c_wc_woc.erb} +2 -1
  10. data/lib/rggen/systemverilog/rtl/bit_field/type/{rc_w0c_w1c.rb → rc_w0c_w1c_wc_woc.rb} +8 -7
  11. data/lib/rggen/systemverilog/rtl/bit_field/type/{rs_w0s_w1s.erb → rs_w0s_w1s_ws_wos.erb} +2 -1
  12. data/lib/rggen/systemverilog/rtl/bit_field/type/{rs_w0s_w1s.rb → rs_w0s_w1s_ws_wos.rb} +8 -7
  13. data/lib/rggen/systemverilog/rtl/bit_field/type/{w0crs_w1crs.erb → w0crs_w1crs_wcrs.erb} +1 -1
  14. data/lib/rggen/systemverilog/rtl/bit_field/type/{w0crs_w1crs.rb → w0crs_w1crs_wcrs.rb} +3 -3
  15. data/lib/rggen/systemverilog/rtl/bit_field/type/{w0src_w1src.erb → w0src_w1src_wsrc.erb} +1 -1
  16. data/lib/rggen/systemverilog/rtl/bit_field/type/{w0src_w1src.rb → w0src_w1src_wsrc.rb} +3 -3
  17. data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb +10 -0
  18. data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb +20 -0
  19. data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb +9 -0
  20. data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb +14 -0
  21. data/lib/rggen/systemverilog/rtl/bit_field_index.rb +53 -0
  22. data/lib/rggen/systemverilog/rtl/indirect_index.rb +35 -0
  23. data/lib/rggen/systemverilog/rtl/register/type.rb +1 -56
  24. data/lib/rggen/systemverilog/rtl/register/type/external.rb +0 -4
  25. data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +2 -26
  26. data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +29 -13
  27. data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb +9 -5
  28. data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +11 -6
  29. data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +30 -5
  30. data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +1 -1
  31. data/lib/rggen/systemverilog/rtl/register_index.rb +4 -4
  32. data/lib/rggen/systemverilog/rtl/register_type.rb +68 -0
  33. data/lib/rggen/systemverilog/rtl/setup.rb +1 -1
  34. data/lib/rggen/systemverilog/version.rb +1 -1
  35. metadata +18 -11
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data/README.md CHANGED
@@ -7,7 +7,7 @@
7
7
 
8
8
  # RgGen::SystemVerilog
9
9
 
10
- RgGen::SystemVerilog privides SystemVerilog RTL generator and UVM RAL model generator for RgGen.
10
+ RgGen::SystemVerilog provides SystemVerilog RTL and UVM register model (UVM RAL) generators for RgGen.
11
11
 
12
12
  ## Installation
13
13
 
@@ -45,6 +45,10 @@ module RgGen
45
45
  end
46
46
  end
47
47
 
48
+ def all_bits_0
49
+ "'0"
50
+ end
51
+
48
52
  def bin(value, width = nil)
49
53
  if width
50
54
  width = bit_width(value, width)
@@ -35,9 +35,9 @@ module RgGen
35
35
  @name.to_s
36
36
  end
37
37
 
38
- def [](array_index_or_lsb, width = nil)
38
+ def [](array_index_or_lsb, lsb_or_width = nil, width = nil)
39
39
  if array_index_or_lsb
40
- __create_new_identifier__(array_index_or_lsb, width)
40
+ __create_new_identifier__(array_index_or_lsb, lsb_or_width, width)
41
41
  else
42
42
  self
43
43
  end
@@ -45,35 +45,38 @@ module RgGen
45
45
 
46
46
  private
47
47
 
48
- def __create_new_identifier__(array_index_or_lsb, width)
49
- select = __create_select__(array_index_or_lsb, width)
48
+ def __create_new_identifier__(array_index_or_lsb, lsb_or_width, width)
49
+ select = __create_select__(array_index_or_lsb, lsb_or_width, width)
50
50
  Identifier.new("#{@name}#{select}") do |identifier|
51
51
  identifier.__sub_identifiers__(@sub_identifiers)
52
52
  end
53
53
  end
54
54
 
55
- def __create_select__(array_index_or_lsb, width)
55
+ def __create_select__(array_index_or_lsb, lsb_or_width, width)
56
56
  if array_index_or_lsb.is_a?(::Array)
57
- __array_select__(array_index_or_lsb)
58
- elsif width
59
- "[#{array_index_or_lsb}+:#{width}]"
57
+ __array_select__(array_index_or_lsb, lsb_or_width, width)
58
+ elsif lsb_or_width
59
+ "[#{array_index_or_lsb}+:#{lsb_or_width}]"
60
60
  else
61
61
  "[#{array_index_or_lsb}]"
62
62
  end
63
63
  end
64
64
 
65
- def __array_select__(array_index)
65
+ def __array_select__(array_index, lsb, width)
66
66
  if @array_format == :serialized
67
- "[#{__serialized_lsb__(array_index)}+:#{@width}]"
67
+ "[#{__serialized_lsb__(array_index, lsb)}+:#{width || @width}]"
68
68
  else
69
- array_index
70
- .map { |index| "[#{index}]" }
71
- .join
69
+ [
70
+ *array_index.map { |index| "[#{index}]" },
71
+ lsb && __create_select__(lsb, width, nil)
72
+ ].compact.join
72
73
  end
73
74
  end
74
75
 
75
- def __serialized_lsb__(array_index)
76
- __reduce_array__([@width, __serialized_index__(array_index)], :*, 1)
76
+ def __serialized_lsb__(array_index, lsb)
77
+ serialized_index = __serialized_index__(array_index)
78
+ array_lsb = __reduce_array__([@width, serialized_index], :*, 1)
79
+ __reduce_array__([array_lsb, lsb], :+, 0)
77
80
  end
78
81
 
79
82
  def __serialized_index__(array_index)
@@ -97,6 +100,7 @@ module RgGen
97
100
  end
98
101
 
99
102
  def __reduce_array__(array, operator, initial_value)
103
+ array = array.compact
100
104
  if array.all?(&method(:integer?))
101
105
  array.reduce(initial_value, &operator)
102
106
  else
@@ -7,6 +7,8 @@ require_relative 'ral/register_common'
7
7
  module RgGen
8
8
  module SystemVerilog
9
9
  module RAL
10
+ PLUGIN_NAME = :'rggen-sv-ral'
11
+
10
12
  FEATURES = [
11
13
  'ral/bit_field/type',
12
14
  'ral/bit_field/type/reserved_rof',
@@ -2,7 +2,7 @@
2
2
 
3
3
  require 'rggen/systemverilog/ral'
4
4
 
5
- RgGen.setup :'rggen-sv-ral', RgGen::SystemVerilog::RAL do |builder|
5
+ RgGen.setup RgGen::SystemVerilog::RAL do |builder|
6
6
  builder.enable :register_block, [:sv_ral_model, :sv_ral_package]
7
7
  builder.enable :register_file, [:sv_ral_model]
8
8
  end
@@ -4,26 +4,33 @@ require_relative 'common'
4
4
  require_relative 'rtl/feature'
5
5
  require_relative 'rtl/partial_sum'
6
6
  require_relative 'rtl/register_index'
7
+ require_relative 'rtl/register_type'
8
+ require_relative 'rtl/indirect_index'
9
+ require_relative 'rtl/bit_field_index'
7
10
 
8
11
  module RgGen
9
12
  module SystemVerilog
10
13
  module RTL
14
+ PLUGIN_NAME = :'rggen-sv-rtl'
15
+
11
16
  FEATURES = [
12
17
  'rtl/bit_field/sv_rtl_top',
13
18
  'rtl/bit_field/type',
14
- 'rtl/bit_field/type/rc_w0c_w1c',
19
+ 'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
15
20
  'rtl/bit_field/type/reserved',
16
21
  'rtl/bit_field/type/ro',
17
22
  'rtl/bit_field/type/rof',
18
- 'rtl/bit_field/type/rs_w0s_w1s',
23
+ 'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
19
24
  'rtl/bit_field/type/rw_w1_wo_wo1',
20
25
  'rtl/bit_field/type/rwc',
21
26
  'rtl/bit_field/type/rwe',
22
27
  'rtl/bit_field/type/rwl',
23
28
  'rtl/bit_field/type/rws',
24
- 'rtl/bit_field/type/w0crs_w1crs',
25
- 'rtl/bit_field/type/w0src_w1src',
29
+ 'rtl/bit_field/type/w0crs_w1crs_wcrs',
30
+ 'rtl/bit_field/type/w0src_w1src_wsrc',
31
+ 'rtl/bit_field/type/w0t_w1t',
26
32
  'rtl/bit_field/type/w0trg_w1trg',
33
+ 'rtl/bit_field/type/wrc_wrs',
27
34
  'rtl/global/array_port_format',
28
35
  'rtl/global/fold_sv_interface_port',
29
36
  'rtl/register/sv_rtl_top',
@@ -2,10 +2,8 @@
2
2
 
3
3
  RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
4
4
  sv_rtl do
5
- export :local_index
6
- export :local_indices
7
- export :loop_variables
8
- export :array_size
5
+ include RgGen::SystemVerilog::RTL::BitFieldIndex
6
+
9
7
  export :value
10
8
 
11
9
  build do
@@ -13,13 +11,13 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
13
11
  localparam :initial_value, {
14
12
  name: initial_value_name, data_type: :bit, width: bit_field.width,
15
13
  array_size: initial_value_size, array_format: initial_value_format,
16
- default: initial_value_lhs
14
+ default: initial_value_rhs
17
15
  }
18
16
  elsif initial_value?
19
17
  parameter :initial_value, {
20
18
  name: initial_value_name, data_type: :bit, width: bit_field.width,
21
19
  array_size: initial_value_size, array_format: initial_value_format,
22
- default: initial_value_lhs
20
+ default: initial_value_rhs
23
21
  }
24
22
  end
25
23
  interface :bit_field_sub_if, {
@@ -42,31 +40,8 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
42
40
  code << bit_field_if_connection << nl
43
41
  end
44
42
 
45
- def local_index
46
- (index_name = local_index_name) &&
47
- create_identifier(index_name)
48
- end
49
-
50
- def local_indices
51
- [*register.local_indices, local_index_name]
52
- end
53
-
54
- def loop_variables
55
- (inside_loop? || nil) &&
56
- [*register.loop_variables, local_index].compact
57
- end
58
-
59
- def array_size
60
- (inside_loop? || nil) &&
61
- [
62
- *register_files.flat_map(&:array_size),
63
- *register.array_size,
64
- *bit_field.sequence_size
65
- ].compact
66
- end
67
-
68
43
  def value(offsets = nil, width = nil)
69
- value_lsb = bit_field.lsb(offsets&.last || local_index_name)
44
+ value_lsb = bit_field.lsb(offsets&.last || local_index)
70
45
  value_width = width || bit_field.width
71
46
  register_if(offsets&.slice(0..-2)).value[value_lsb, value_width]
72
47
  end
@@ -77,14 +52,6 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
77
52
  define_method(m) { bit_field.__send__(__method__) }
78
53
  end
79
54
 
80
- def local_index_name
81
- (bit_field.sequential? || nil) &&
82
- begin
83
- depth = (register.loop_variables&.size || 0) + 1
84
- loop_index(depth)
85
- end
86
- end
87
-
88
55
  def register_if(offsets)
89
56
  index = register.index(offsets || register.local_indices)
90
57
  register_block.register_if[index]
@@ -106,11 +73,11 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
106
73
  configuration.array_port_format
107
74
  end
108
75
 
109
- def initial_value_lhs
110
- initial_value_array? && initial_value_array_lhs || sized_initial_value
76
+ def initial_value_rhs
77
+ initial_value_array? && initial_value_array_rhs || sized_initial_value
111
78
  end
112
79
 
113
- def initial_value_array_lhs
80
+ def initial_value_array_rhs
114
81
  if fixed_initial_value?
115
82
  array(sized_initial_values)
116
83
  elsif initial_value_format == :unpacked
@@ -129,12 +96,9 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
129
96
  bit_field.initial_values&.map { |v| hex(v, bit_field.width) }
130
97
  end
131
98
 
132
- def inside_loop?
133
- register.array? || bit_field.sequential?
134
- end
135
-
136
99
  def loop_size
137
- (loop_variable = local_index_name) &&
100
+ loop_variable = local_index
101
+ loop_variable &&
138
102
  { loop_variable => bit_field.sequence_size }
139
103
  end
140
104
 
@@ -1,6 +1,7 @@
1
1
  <%= module_name %> #(
2
- <% if [:w0c, :w1c].include?(bit_field.type) %>
2
+ <% if bit_field.type != :rc %>
3
3
  .CLEAR_VALUE (<%= clear_value %>),
4
+ .WRITE_ONLY (<%= write_only %>),
4
5
  <% end %>
5
6
  .WIDTH (<%= width %>),
6
7
  .INITIAL_VALUE (<%= initial_value %>)
@@ -1,6 +1,6 @@
1
1
  # frozen_string_literal: true
2
2
 
3
- RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
3
+ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc]) do
4
4
  sv_rtl do
5
5
  build do
6
6
  input :set, {
@@ -24,15 +24,16 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
24
24
  private
25
25
 
26
26
  def module_name
27
- if bit_field.type == :rc
28
- 'rggen_bit_field_rc'
29
- else
30
- 'rggen_bit_field_w01c'
31
- end
27
+ bit_field.type == :rc && 'rggen_bit_field_rc' || 'rggen_bit_field_w01c_wc_woc'
32
28
  end
33
29
 
34
30
  def clear_value
35
- bin({ w0c: 0, w1c: 1 }[bit_field.type], 1)
31
+ value = { w0c: 0b00, w1c: 0b01, wc: 0b10, woc: 0b10 }[bit_field.type]
32
+ bin(value, 2)
33
+ end
34
+
35
+ def write_only
36
+ bit_field.write_only? && 1 || 0
36
37
  end
37
38
 
38
39
  def value_out_unmasked
@@ -1,6 +1,7 @@
1
1
  <%= module_name %> #(
2
- <% if [:w0s, :w1s].include?(bit_field.type) %>
2
+ <% if bit_field.type != :rs %>
3
3
  .SET_VALUE (<%= set_value %>),
4
+ .WRITE_ONLY (<%= write_only %>),
4
5
  <% end %>
5
6
  .WIDTH (<%= width %>),
6
7
  .INITIAL_VALUE (<%= initial_value %>)
@@ -1,6 +1,6 @@
1
1
  # frozen_string_literal: true
2
2
 
3
- RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
3
+ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos]) do
4
4
  sv_rtl do
5
5
  build do
6
6
  input :clear, {
@@ -18,15 +18,16 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
18
18
  private
19
19
 
20
20
  def module_name
21
- if bit_field.type == :rs
22
- 'rggen_bit_field_rs'
23
- else
24
- 'rggen_bit_field_w01s'
25
- end
21
+ bit_field.type == :rs && 'rggen_bit_field_rs' || 'rggen_bit_field_w01s_ws_wos'
26
22
  end
27
23
 
28
24
  def set_value
29
- bin({ w0s: 0, w1s: 1 }[bit_field.type], 1)
25
+ value = { w0s: 0b00, w1s: 0b01, ws: 0b10, wos: 0b10 }[bit_field.type]
26
+ bin(value, 2)
27
+ end
28
+
29
+ def write_only
30
+ bit_field.write_only? && 1 || 0
30
31
  end
31
32
  end
32
33
  end
@@ -1,4 +1,4 @@
1
- rggen_bit_field_w01crs #(
1
+ rggen_bit_field_w01crs_wcrs #(
2
2
  .CLEAR_VALUE (<%= clear_value %>),
3
3
  .WIDTH (<%= width %>),
4
4
  .INITIAL_VALUE (<%= initial_value %>)
@@ -1,6 +1,6 @@
1
1
  # frozen_string_literal: true
2
2
 
3
- RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
3
+ RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs, :wcrs]) do
4
4
  sv_rtl do
5
5
  build do
6
6
  output :value_out, {
@@ -14,8 +14,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
14
14
  private
15
15
 
16
16
  def clear_value
17
- value = (bit_field.type == :w0crs && 0) || 1
18
- bin(value, 1)
17
+ value = { w0crs: 0b00, w1crs: 0b01, wcrs: 0b10 }[bit_field.type]
18
+ bin(value, 2)
19
19
  end
20
20
  end
21
21
  end
@@ -1,4 +1,4 @@
1
- rggen_bit_field_w01src #(
1
+ rggen_bit_field_w01src_wsrc #(
2
2
  .SET_VALUE (<%= set_value %>),
3
3
  .WIDTH (<%= width %>),
4
4
  .INITIAL_VALUE (<%= initial_value %>)
@@ -1,6 +1,6 @@
1
1
  # frozen_string_literal: true
2
2
 
3
- RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
3
+ RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src, :wsrc]) do
4
4
  sv_rtl do
5
5
  build do
6
6
  output :value_out, {
@@ -14,8 +14,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
14
14
  private
15
15
 
16
16
  def set_value
17
- value = (bit_field.type == :w0src && 0) || 1
18
- bin(value, 1)
17
+ value = { w0src: 0b00, w1src: 0b01, wsrc: 0b10 }[bit_field.type]
18
+ bin(value, 2)
19
19
  end
20
20
  end
21
21
  end
@@ -0,0 +1,10 @@
1
+ rggen_bit_field_w01t #(
2
+ .TOGGLE_VALUE (<%= toggle_value %>),
3
+ .WIDTH (<%= width %>),
4
+ .INITIAL_VALUE (<%= initial_value %>)
5
+ ) u_bit_field (
6
+ .i_clk (<%= clock %>),
7
+ .i_rst_n (<%= reset %>),
8
+ .bit_field_if (<%= bit_field_if %>),
9
+ .o_value (<%= value_out[loop_variables] %>)
10
+ );
@@ -0,0 +1,20 @@
1
+ # frozen_string_literal: true
2
+
3
+ RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
4
+ sv_rtl do
5
+ build do
6
+ output :value_out, {
7
+ name: "o_#{full_name}", data_type: :logic, width: width,
8
+ array_size: array_size, array_format: array_port_format
9
+ }
10
+ end
11
+
12
+ main_code :bit_field, from_template: true
13
+
14
+ private
15
+
16
+ def toggle_value
17
+ bin({ w0t: 0, w1t: 1 }[bit_field.type], 1)
18
+ end
19
+ end
20
+ end
@@ -0,0 +1,9 @@
1
+ rggen_bit_field_<%= bit_field.type %> #(
2
+ .WIDTH (<%= width %>),
3
+ .INITIAL_VALUE (<%= initial_value %>)
4
+ ) u_bit_field (
5
+ .i_clk (<%= clock %>),
6
+ .i_rst_n (<%= reset %>),
7
+ .bit_field_if (<%= bit_field_if %>),
8
+ .o_value (<%= value_out[loop_variables] %>)
9
+ );
@@ -0,0 +1,14 @@
1
+ # frozen_string_literal: true
2
+
3
+ RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
4
+ sv_rtl do
5
+ build do
6
+ output :value_out, {
7
+ name: "o_#{full_name}", data_type: :logic, width: width,
8
+ array_size: array_size, array_format: array_port_format
9
+ }
10
+ end
11
+
12
+ main_code :bit_field, from_template: true
13
+ end
14
+ end
@@ -0,0 +1,53 @@
1
+ # frozen_string_literal: true
2
+
3
+ module RgGen
4
+ module SystemVerilog
5
+ module RTL
6
+ module BitFieldIndex
7
+ EXPORTED_METHODS = [
8
+ :local_index, :local_indices, :loop_variables, :array_size
9
+ ].freeze
10
+
11
+ def self.included(feature)
12
+ feature.module_eval do
13
+ EXPORTED_METHODS.each { |m| export m }
14
+ end
15
+ end
16
+
17
+ def local_index
18
+ index_name = local_index_name
19
+ index_name && create_identifier(index_name)
20
+ end
21
+
22
+ def local_indices
23
+ [*register.local_indices, local_index_name]
24
+ end
25
+
26
+ def loop_variables
27
+ (inside_loop? || nil) &&
28
+ [*register.loop_variables, local_index].compact
29
+ end
30
+
31
+ def array_size
32
+ (inside_loop? || nil) &&
33
+ [
34
+ *register_files.flat_map(&:array_size),
35
+ *register.array_size,
36
+ *bit_field.sequence_size
37
+ ].compact
38
+ end
39
+
40
+ private
41
+
42
+ def local_index_name
43
+ (bit_field.sequential? || nil) &&
44
+ loop_index((register.loop_variables&.size || 0) + 1)
45
+ end
46
+
47
+ def inside_loop?
48
+ register.inside_loop? || bit_field.sequential?
49
+ end
50
+ end
51
+ end
52
+ end
53
+ end
@@ -0,0 +1,35 @@
1
+ # frozen_string_literal: true
2
+
3
+ module RgGen
4
+ module SystemVerilog
5
+ module RTL
6
+ module IndirectIndex
7
+ private
8
+
9
+ def index_fields
10
+ @index_fields ||=
11
+ register.collect_index_fields(register_block.bit_fields)
12
+ end
13
+
14
+ def index_width
15
+ @index_width ||= index_fields.sum(&:width)
16
+ end
17
+
18
+ def index_values
19
+ loop_variables = register.local_loop_variables
20
+ register.index_entries.zip(index_fields).map do |entry, field|
21
+ if entry.array_index?
22
+ loop_variables.shift[0, field.width]
23
+ else
24
+ hex(entry.value, field.width)
25
+ end
26
+ end
27
+ end
28
+
29
+ def indirect_index_assignment
30
+ assign(indirect_index, concat(index_fields.map(&:value)))
31
+ end
32
+ end
33
+ end
34
+ end
35
+ end
@@ -3,65 +3,10 @@
3
3
  RgGen.define_list_feature(:register, :type) do
4
4
  sv_rtl do
5
5
  base_feature do
6
- include RgGen::SystemVerilog::RTL::PartialSum
6
+ include RgGen::SystemVerilog::RTL::RegisterType
7
7
 
8
8
  private
9
9
 
10
- def readable
11
- register.readable? && 1 || 0
12
- end
13
-
14
- def writable
15
- register.writable? && 1 || 0
16
- end
17
-
18
- def bus_width
19
- configuration.bus_width
20
- end
21
-
22
- def address_width
23
- register_block.local_address_width
24
- end
25
-
26
- def offset_address
27
- offsets = [*register_files, register].flat_map(&method(:collect_offsets))
28
- offsets = partial_sums(offsets)
29
- format_offsets(offsets)
30
- end
31
-
32
- def collect_offsets(component)
33
- if component.register_file? && component.array?
34
- [component.offset_address, byte_offset(component)]
35
- else
36
- component.offset_address
37
- end
38
- end
39
-
40
- def byte_offset(component)
41
- "#{component.byte_size(false)}*(#{component.local_index})"
42
- end
43
-
44
- def format_offsets(offsets)
45
- offsets.map(&method(:format_offset)).join('+')
46
- end
47
-
48
- def format_offset(offset)
49
- offset.is_a?(Integer) ? hex(offset, address_width) : offset
50
- end
51
-
52
- def width
53
- register.width
54
- end
55
-
56
- def valid_bits
57
- bits = register.bit_fields.map(&:bit_map).inject(:|)
58
- hex(bits, register.width)
59
- end
60
-
61
- def register_index
62
- register.local_index || 0
63
- end
64
-
65
10
  def register_if
66
11
  register_block.register_if[register.index]
67
12
  end
@@ -71,10 +71,6 @@ RgGen.define_list_item_feature(:register, :type, :external) do
71
71
 
72
72
  private
73
73
 
74
- def address_width
75
- register_block.local_address_width
76
- end
77
-
78
74
  def byte_width
79
75
  configuration.byte_width
80
76
  end
@@ -2,6 +2,8 @@
2
2
 
3
3
  RgGen.define_list_item_feature(:register, :type, :indirect) do
4
4
  sv_rtl do
5
+ include RgGen::SystemVerilog::RTL::IndirectIndex
6
+
5
7
  build do
6
8
  logic :indirect_index, { width: index_width }
7
9
  end
@@ -10,31 +12,5 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
10
12
  code << indirect_index_assignment << nl
11
13
  code << process_template
12
14
  end
13
-
14
- private
15
-
16
- def index_fields
17
- @index_fields ||=
18
- register.collect_index_fields(register_block.bit_fields)
19
- end
20
-
21
- def index_width
22
- @index_width ||= index_fields.map(&:width).sum
23
- end
24
-
25
- def index_values
26
- loop_variables = register.local_loop_variables
27
- register.index_entries.zip(index_fields).map do |entry, field|
28
- if entry.array_index?
29
- loop_variables.shift[0, field.width]
30
- else
31
- hex(entry.value, field.width)
32
- end
33
- end
34
- end
35
-
36
- def indirect_index_assignment
37
- assign(indirect_index, concat(index_fields.map(&:value)))
38
- end
39
15
  end
40
16
  end
@@ -2,19 +2,25 @@
2
2
 
3
3
  RgGen.define_list_feature(:register_block, :protocol) do
4
4
  shared_context do
5
- def feature_registry(registry = nil)
6
- @registry = registry if registry
7
- @registry
5
+ def feature_registry(registry)
6
+ feature_registries << registry
8
7
  end
9
8
 
10
9
  def available_protocols
11
- feature_registry
12
- .enabled_features(:protocol)
13
- .select(&method(:valid_protocol?))
10
+ feature_registries
11
+ .map(&method(:collect_available_protocols)).inject(:&)
12
+ end
13
+
14
+ private
15
+
16
+ def feature_registries
17
+ @feature_registries ||= []
14
18
  end
15
19
 
16
- def valid_protocol?(protocol)
17
- feature_registry.feature?(:protocol, protocol)
20
+ def collect_available_protocols(registry)
21
+ registry
22
+ .enabled_features(:protocol)
23
+ .select { |protocol| registry.feature?(:protocol, protocol) }
18
24
  end
19
25
  end
20
26
 
@@ -65,21 +71,27 @@ RgGen.define_list_feature(:register_block, :protocol) do
65
71
 
66
72
  base_feature do
67
73
  build do
74
+ parameter :address_width, {
75
+ name: 'ADDRESS_WIDTH', data_type: :int, default: local_address_width
76
+ }
77
+ parameter :pre_decode, {
78
+ name: 'PRE_DECODE', data_type: :bit, width: 1, default: 0
79
+ }
80
+ parameter :base_address, {
81
+ name: 'BASE_ADDRESS', data_type: :bit, width: address_width,
82
+ default: all_bits_0
83
+ }
68
84
  parameter :error_status, {
69
85
  name: 'ERROR_STATUS', data_type: :bit, width: 1, default: 0
70
86
  }
71
87
  parameter :default_read_data, {
72
88
  name: 'DEFAULT_READ_DATA', data_type: :bit, width: bus_width,
73
- default: hex(0, bus_width)
89
+ default: all_bits_0
74
90
  }
75
91
  end
76
92
 
77
93
  private
78
94
 
79
- def address_width
80
- configuration.address_width
81
- end
82
-
83
95
  def bus_width
84
96
  configuration.bus_width
85
97
  end
@@ -96,6 +108,10 @@ RgGen.define_list_feature(:register_block, :protocol) do
96
108
  register_block.total_registers
97
109
  end
98
110
 
111
+ def byte_size
112
+ register_block.byte_size
113
+ end
114
+
99
115
  def clock
100
116
  register_block.clock
101
117
  end
@@ -1,9 +1,13 @@
1
1
  rggen_apb_adapter #(
2
- .ADDRESS_WIDTH (<%= local_address_width %>),
3
- .BUS_WIDTH (<%= bus_width %>),
4
- .REGISTERS (<%= total_registers %>),
5
- .ERROR_STATUS (<%= error_status %>),
6
- .DEFAULT_READ_DATA (<%= default_read_data %>)
2
+ .ADDRESS_WIDTH (<%= address_width %>),
3
+ .LOCAL_ADDRESS_WIDTH (<%= local_address_width %>),
4
+ .BUS_WIDTH (<%= bus_width %>),
5
+ .REGISTERS (<%= total_registers %>),
6
+ .PRE_DECODE (<%= pre_decode %>),
7
+ .BASE_ADDRESS (<%= base_address %>),
8
+ .BYTE_SIZE (<%= byte_size %>),
9
+ .ERROR_STATUS (<%= error_status %>),
10
+ .DEFAULT_READ_DATA (<%= default_read_data %>)
7
11
  ) u_adapter (
8
12
  .i_clk (<%= clock %>),
9
13
  .i_rst_n (<%= reset %>),
@@ -1,10 +1,15 @@
1
1
  rggen_axi4lite_adapter #(
2
- .ADDRESS_WIDTH (<%= local_address_width %>),
3
- .BUS_WIDTH (<%= bus_width %>),
4
- .REGISTERS (<%= total_registers %>),
5
- .ERROR_STATUS (<%= error_status %>),
6
- .DEFAULT_READ_DATA (<%= default_read_data %>),
7
- .WRITE_FIRST (<%= write_first %>)
2
+ .ID_WIDTH (<%= id_width %>),
3
+ .ADDRESS_WIDTH (<%= address_width %>),
4
+ .LOCAL_ADDRESS_WIDTH (<%= local_address_width %>),
5
+ .BUS_WIDTH (<%= bus_width %>),
6
+ .REGISTERS (<%= total_registers %>),
7
+ .PRE_DECODE (<%= pre_decode %>),
8
+ .BASE_ADDRESS (<%= base_address %>),
9
+ .BYTE_SIZE (<%= byte_size %>),
10
+ .ERROR_STATUS (<%= error_status %>),
11
+ .DEFAULT_READ_DATA (<%= default_read_data %>),
12
+ .WRITE_FIRST (<%= write_first %>)
8
13
  ) u_adapter (
9
14
  .i_clk (<%= clock %>),
10
15
  .i_rst_n (<%= reset %>),
@@ -13,6 +13,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
13
13
 
14
14
  sv_rtl do
15
15
  build do
16
+ parameter :id_width, {
17
+ name: 'ID_WIDTH', data_type: :int, default: 0
18
+ }
16
19
  parameter :write_first, {
17
20
  name: 'WRITE_FIRST', data_type: :bit, default: 1
18
21
  }
@@ -28,6 +31,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
28
31
  output :awready, {
29
32
  name: 'o_awready', data_type: :logic, width: 1
30
33
  }
34
+ input :awid, {
35
+ name: 'i_awid', data_type: :logic, width: id_port_width
36
+ }
31
37
  input :awaddr, {
32
38
  name: 'i_awaddr', data_type: :logic, width: address_width
33
39
  }
@@ -49,6 +55,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
49
55
  output :bvalid, {
50
56
  name: 'o_bvalid', data_type: :logic, width: 1
51
57
  }
58
+ output :bid, {
59
+ name: 'o_bid', data_type: :logic, width: id_port_width
60
+ }
52
61
  input :bready, {
53
62
  name: 'i_bready', data_type: :logic, width: 1
54
63
  }
@@ -61,6 +70,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
61
70
  output :arready, {
62
71
  name: 'o_arready', data_type: :logic, width: 1
63
72
  }
73
+ input :arid, {
74
+ name: 'i_arid', data_type: :logic, width: id_port_width
75
+ }
64
76
  input :araddr, {
65
77
  name: 'i_araddr', data_type: :logic, width: address_width
66
78
  }
@@ -73,6 +85,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
73
85
  input :rready, {
74
86
  name: 'i_rready', data_type: :logic, width: 1
75
87
  }
88
+ output :rid, {
89
+ name: 'o_rid', data_type: :logic, width: id_port_width
90
+ }
76
91
  output :rdata, {
77
92
  name: 'o_rdata', data_type: :logic, width: bus_width
78
93
  }
@@ -81,13 +96,13 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
81
96
  }
82
97
  interface :axi4lite_if, {
83
98
  name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',
84
- parameter_values: [address_width, bus_width],
99
+ parameter_values: [id_width, address_width, bus_width],
85
100
  variables: [
86
- 'awvalid', 'awready', 'awaddr', 'awprot',
101
+ 'awvalid', 'awready', 'awid', 'awaddr', 'awprot',
87
102
  'wvalid', 'wready', 'wdata', 'wstrb',
88
- 'bvalid', 'bready', 'bresp',
89
- 'arvalid', 'arready', 'araddr', 'arprot',
90
- 'rvalid', 'rready', 'rdata', 'rresp'
103
+ 'bvalid', 'bready', 'bid', 'bresp',
104
+ 'arvalid', 'arready', 'arid', 'araddr', 'arprot',
105
+ 'rvalid', 'rready', 'rid', 'rdata', 'rresp'
91
106
  ]
92
107
  }
93
108
  end
@@ -99,6 +114,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
99
114
  [
100
115
  [axi4lite_if.awvalid, awvalid],
101
116
  [awready, axi4lite_if.awready],
117
+ [axi4lite_if.awid, awid],
102
118
  [axi4lite_if.awaddr, awaddr],
103
119
  [axi4lite_if.awprot, awprot],
104
120
  [axi4lite_if.wvalid, wvalid],
@@ -107,17 +123,26 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
107
123
  [axi4lite_if.wstrb, wstrb],
108
124
  [bvalid, axi4lite_if.bvalid],
109
125
  [axi4lite_if.bready, bready],
126
+ [bid, axi4lite_if.bid],
110
127
  [bresp, axi4lite_if.bresp],
111
128
  [axi4lite_if.arvalid, arvalid],
112
129
  [arready, axi4lite_if.arready],
130
+ [axi4lite_if.arid, arid],
113
131
  [axi4lite_if.araddr, araddr],
114
132
  [axi4lite_if.arprot, arprot],
115
133
  [rvalid, axi4lite_if.rvalid],
116
134
  [axi4lite_if.rready, rready],
135
+ [rid, axi4lite_if.rid],
117
136
  [rdata, axi4lite_if.rdata],
118
137
  [rresp, axi4lite_if.rresp]
119
138
  ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
120
139
  end
121
140
  end
141
+
142
+ private
143
+
144
+ def id_port_width
145
+ "((#{id_width}>0)?#{id_width}:1)"
146
+ end
122
147
  end
123
148
  end
@@ -23,7 +23,7 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
23
23
  end
24
24
 
25
25
  def total_registers
26
- register_block.files_and_registers.map(&:count).sum
26
+ register_block.files_and_registers.sum(&:count)
27
27
  end
28
28
 
29
29
  private
@@ -9,7 +9,7 @@ module RgGen
9
9
  EXPORTED_METHODS = [
10
10
  :loop_variables, :local_loop_variables,
11
11
  :local_index, :local_indices,
12
- :index, :inside_roop?
12
+ :index, :inside_loop?
13
13
  ].freeze
14
14
 
15
15
  def self.included(feature)
@@ -23,7 +23,7 @@ module RgGen
23
23
  end
24
24
 
25
25
  def loop_variables
26
- (inside_roop? || nil) &&
26
+ (inside_loop? || nil) &&
27
27
  [*upper_register_file&.loop_variables, *local_loop_variables]
28
28
  end
29
29
 
@@ -59,8 +59,8 @@ module RgGen
59
59
  end
60
60
  end
61
61
 
62
- def inside_roop?
63
- component.array? || upper_register_file&.inside_roop? || false
62
+ def inside_loop?
63
+ component.array? || upper_register_file&.inside_loop? || false
64
64
  end
65
65
 
66
66
  private
@@ -0,0 +1,68 @@
1
+ # frozen_string_literal: true
2
+
3
+ module RgGen
4
+ module SystemVerilog
5
+ module RTL
6
+ module RegisterType
7
+ include PartialSum
8
+
9
+ private
10
+
11
+ def readable
12
+ register.readable? && 1 || 0
13
+ end
14
+
15
+ def writable
16
+ register.writable? && 1 || 0
17
+ end
18
+
19
+ def bus_width
20
+ configuration.bus_width
21
+ end
22
+
23
+ def address_width
24
+ register_block.local_address_width
25
+ end
26
+
27
+ def offset_address
28
+ offsets = [*register_files, register].flat_map(&method(:collect_offsets))
29
+ offsets = partial_sums(offsets)
30
+ format_offsets(offsets)
31
+ end
32
+
33
+ def collect_offsets(component)
34
+ if component.register_file? && component.array?
35
+ [component.offset_address, byte_offset(component)]
36
+ else
37
+ component.offset_address
38
+ end
39
+ end
40
+
41
+ def byte_offset(component)
42
+ "#{component.byte_size(false)}*(#{component.local_index})"
43
+ end
44
+
45
+ def format_offsets(offsets)
46
+ offsets.map(&method(:format_offset)).join('+')
47
+ end
48
+
49
+ def format_offset(offset)
50
+ offset.is_a?(Integer) ? hex(offset, address_width) : offset
51
+ end
52
+
53
+ def width
54
+ register.width
55
+ end
56
+
57
+ def valid_bits
58
+ bits = register.bit_fields.map(&:bit_map).inject(:|)
59
+ hex(bits, register.width)
60
+ end
61
+
62
+ def register_index
63
+ register.local_index || 0
64
+ end
65
+ end
66
+ end
67
+ end
68
+ end
@@ -2,7 +2,7 @@
2
2
 
3
3
  require 'rggen/systemverilog/rtl'
4
4
 
5
- RgGen.setup :'rggen-sv-rtl', RgGen::SystemVerilog::RTL do |builder|
5
+ RgGen.setup RgGen::SystemVerilog::RTL do |builder|
6
6
  builder.enable :global, [
7
7
  :array_port_format, :fold_sv_interface_port
8
8
  ]
@@ -2,6 +2,6 @@
2
2
 
3
3
  module RgGen
4
4
  module SystemVerilog
5
- VERSION = '0.20.0'
5
+ VERSION = '0.23.1'
6
6
  end
7
7
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: rggen-systemverilog
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.20.0
4
+ version: 0.23.1
5
5
  platform: ruby
6
6
  authors:
7
7
  - Taichi Ishitani
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2020-07-06 00:00:00.000000000 Z
11
+ date: 2020-10-24 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: docile
@@ -103,16 +103,16 @@ files:
103
103
  - lib/rggen/systemverilog/rtl.rb
104
104
  - lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
105
105
  - lib/rggen/systemverilog/rtl/bit_field/type.rb
106
- - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb
107
- - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb
106
+ - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
107
+ - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
108
108
  - lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb
109
109
  - lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb
110
110
  - lib/rggen/systemverilog/rtl/bit_field/type/ro.erb
111
111
  - lib/rggen/systemverilog/rtl/bit_field/type/ro.rb
112
112
  - lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
113
113
  - lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
114
- - lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb
115
- - lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb
114
+ - lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb
115
+ - lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb
116
116
  - lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb
117
117
  - lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb
118
118
  - lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb
@@ -123,15 +123,21 @@ files:
123
123
  - lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb
124
124
  - lib/rggen/systemverilog/rtl/bit_field/type/rws.erb
125
125
  - lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
126
- - lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb
127
- - lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb
128
- - lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb
129
- - lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb
126
+ - lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs_wcrs.erb
127
+ - lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs_wcrs.rb
128
+ - lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src_wsrc.erb
129
+ - lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src_wsrc.rb
130
+ - lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb
131
+ - lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb
130
132
  - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
131
133
  - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
134
+ - lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb
135
+ - lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb
136
+ - lib/rggen/systemverilog/rtl/bit_field_index.rb
132
137
  - lib/rggen/systemverilog/rtl/feature.rb
133
138
  - lib/rggen/systemverilog/rtl/global/array_port_format.rb
134
139
  - lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
140
+ - lib/rggen/systemverilog/rtl/indirect_index.rb
135
141
  - lib/rggen/systemverilog/rtl/partial_sum.rb
136
142
  - lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
137
143
  - lib/rggen/systemverilog/rtl/register/type.rb
@@ -149,6 +155,7 @@ files:
149
155
  - lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb
150
156
  - lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
151
157
  - lib/rggen/systemverilog/rtl/register_index.rb
158
+ - lib/rggen/systemverilog/rtl/register_type.rb
152
159
  - lib/rggen/systemverilog/rtl/setup.rb
153
160
  - lib/rggen/systemverilog/version.rb
154
161
  homepage: https://github.com/rggen/rggen-systemverilog
@@ -177,5 +184,5 @@ requirements: []
177
184
  rubygems_version: 3.1.2
178
185
  signing_key:
179
186
  specification_version: 4
180
- summary: rggen-systemverilog-0.20.0
187
+ summary: rggen-systemverilog-0.23.1
181
188
  test_files: []