rggen-systemverilog 0.17.0 → 0.18.0
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checksums.yaml
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@@ -1,7 +1,7 @@
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metadata.gz: 47c585c5655ade6c0873ea2a1ca091d3df75a64d7d8cf4a5250feb4689395828
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data.tar.gz: 2c43249b487d8684988d74bed9ee8566aa4199cb53fb4cff97310195b3237b4e
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SHA512:
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metadata.gz: 71b81632625b3a9d2315eaa00e067987fc4301a27d0fe0974f896be532ffbca6594b1b7679c124e0ea5dde71643435e3462b18c57eaa31fc7fa36d292c69167f
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data.tar.gz: 5e2aa49b5deab5873b42b8d41e1d3290f5d42f85126d69921cf2f07f9e9312573fd344aebb9f6585194c6060a8add44dfddcd862c3fe173cfdf94381f468b417
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@@ -14,7 +14,7 @@ module RgGen
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'rtl/bit_field/type/ro',
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'rtl/bit_field/type/rof',
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'rtl/bit_field/type/rs_w0s_w1s',
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'rtl/bit_field/type/
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'rtl/bit_field/type/rw_w1_wo_wo1',
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'rtl/bit_field/type/rwc',
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'rtl/bit_field/type/rwe',
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'rtl/bit_field/type/rwl',
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@@ -1,6 +1,8 @@
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-
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rggen_bit_field_rw_wo #(
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.WIDTH (<%= width %>),
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.INITIAL_VALUE (<%= initial_value %>)
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.INITIAL_VALUE (<%= initial_value %>),
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.WRITE_ONLY (<%= write_only %>),
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.WRITE_ONCE (<%= write_once %>)
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) u_bit_field (
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.i_clk (<%= clock %>),
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.i_rst_n (<%= reset %>),
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@@ -1,6 +1,6 @@
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# frozen_string_literal: true
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RgGen.define_list_item_feature(:bit_field, :type, [:rw, :wo]) do
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RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
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sv_rtl do
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build do
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output :register_block, :value_out, {
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@@ -10,5 +10,15 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :wo]) do
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end
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main_code :bit_field, from_template: true
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private
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def write_only
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bit_field.write_only? && 1 || 0
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end
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def write_once
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[:w1, :wo1].include?(bit_field.type) && 1 || 0
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end
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end
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end
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metadata
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@@ -1,14 +1,14 @@
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--- !ruby/object:Gem::Specification
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name: rggen-systemverilog
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version: !ruby/object:Gem::Version
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version: 0.
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version: 0.18.0
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platform: ruby
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authors:
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- Taichi Ishitani
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autorequire:
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bindir: bin
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cert_chain: []
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date: 2019-11-
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date: 2019-11-19 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: docile
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@@ -109,8 +109,8 @@ files:
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- lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
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- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb
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- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb
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-
- lib/rggen/systemverilog/rtl/bit_field/type/
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-
- lib/rggen/systemverilog/rtl/bit_field/type/
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- lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb
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- lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb
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- lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb
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- lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
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- lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb
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@@ -170,5 +170,5 @@ requirements: []
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rubygems_version: 3.0.3
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signing_key:
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specification_version: 4
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summary: rggen-systemverilog-0.
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summary: rggen-systemverilog-0.18.0
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test_files: []
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