rggen-systemverilog 0.13.0 → 0.14.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 8a3623823355599396aefd51ff1e23199edeadb01ec6a9c5a41e4c96795bd415
-  data.tar.gz: 9d64e7ed55d00af43bec20af3277fbc4236bb8c3a4839291de9c2e4ded5657ba
+  metadata.gz: 19dd7072e4a6d974adff622812b8687a3f9d4124b28fed40ca2f4e6f4c7c0a60
+  data.tar.gz: e36c2c9907a4da9c7ff5cf38bbdbc76427a3a409be7b430d54064ffd51ae610f
 SHA512:
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-  data.tar.gz: aab9d80c62650db7bbae7ffe799aa3330cae974be7adecad9615e400576d472aa9e89ba043c653baa5c1d4aceb4d38b5677d8f996adbd6d1b191956f282ede6c
+  metadata.gz: 1b0585c58678e7e2826d8a8d933a8d74167d9118c969134057f61cd018035875d83df3e6a709e58c32f9df8ceb8b3474c022a2674d01a5aa3225e13c82ca6e71
+  data.tar.gz: 31fc31da516047f204f385e7fbb22316ad7edeb4252eebba47d0c571df77e5ec5078af1b9729248f784297a8f3bea1e5d654ce582b05c03535441f649ad713ec

data/lib/rggen/systemverilog/ral.rb

@@ -9,7 +9,8 @@ module RgGen
       FEATURES = [
         'ral/bit_field/type',
         'ral/bit_field/type/reserved_rof',
-        'ral/bit_field/type/rwc_rwe_rwl',
+        'ral/bit_field/type/rwc_rws',
+        'ral/bit_field/type/rwe_rwl',
         'ral/bit_field/type/w0trg_w1trg',
         'ral/register/type',
         'ral/register/type/external',

data/lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rws]) do
+  sv_ral { access 'RW' }
+end

data/lib/rggen/systemverilog/ral/bit_field/type/{rwc_rwe_rwl.rb → rwe_rwl.rb}

@@ -1,9 +1,5 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
-  sv_ral { access 'RW' }
-end
-
 RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
   sv_ral do
     model_name do

data/lib/rggen/systemverilog/rtl.rb

@@ -15,7 +15,10 @@ module RgGen
         'rtl/bit_field/type/rof',
         'rtl/bit_field/type/rs_w0s_w1s',
         'rtl/bit_field/type/rw_wo',
-        'rtl/bit_field/type/rwc_rwe_rwl',
+        'rtl/bit_field/type/rwc',
+        'rtl/bit_field/type/rwe',
+        'rtl/bit_field/type/rwl',
+        'rtl/bit_field/type/rws',
         'rtl/bit_field/type/w0trg_w1trg',
         'rtl/global/array_port_format',
         'rtl/global/fold_sv_interface_port',

data/lib/rggen/systemverilog/rtl/bit_field/type.rb

@@ -17,6 +17,14 @@ RgGen.define_list_feature(:bit_field, :type) do
         bit_field.width
       end
 
+      def clock
+        register_block.clock
+      end
+
+      def reset
+        register_block.reset
+      end
+
       def array_size
         bit_field.array_size
       end

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb

@@ -5,8 +5,8 @@
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)
 ) u_bit_field (
-  .i_clk            (<%= register_block.clock %>),
-  .i_rst_n          (<%= register_block.reset%>),
+  .i_clk            (<%= clock %>),
+  .i_rst_n          (<%= reset%>),
   .bit_field_if     (<%= bit_field_if %>),
   .i_set            (<%= set[loop_variables] %>),
   .i_mask           (<%= mask %>),

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb

@@ -1,21 +1,5 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, :rc) do
-  register_map do
-    read_only
-    reference use: true
-    initial_value require: true
-  end
-end
-
-RgGen.define_list_item_feature(:bit_field, :type, [:w0c, :w1c]) do
-  register_map do
-    read_write
-    reference use: true
-    initial_value require: true
-  end
-end
-
 RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
   sv_rtl do
     build do

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb

@@ -5,8 +5,8 @@
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)
 ) u_bit_field (
-  .i_clk        (<%= register_block.clock %>),
-  .i_rst_n      (<%= register_block.reset %>),
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
   .bit_field_if (<%= bit_field_if %>),
   .i_clear      (<%= clear[loop_variables] %>),
   .o_value      (<%= value_out[loop_variables] %>)

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.erb

@@ -2,8 +2,8 @@ rggen_bit_field_<%= bit_field.type %> #(
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)
 ) u_bit_field (
-  .i_clk        (<%= register_block.clock %>),
-  .i_rst_n      (<%= register_block.reset %>),
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
   .bit_field_if (<%= bit_field_if %>),
   .o_value      (<%= value_out[loop_variables] %>)
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb

@@ -0,0 +1,10 @@
+rggen_bit_field_rwc #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .i_clear      (<%= clear_signal %>),
+  .o_value      (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb

@@ -0,0 +1,26 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
+  sv_rtl do
+    build do
+      unless bit_field.reference?
+        input :register_block, :clear, {
+          name: "i_#{full_name}_clear", data_type: :logic, width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      output :register_block, :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def clear_signal
+      reference_bit_field || clear[loop_variables]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb

@@ -0,0 +1,10 @@
+rggen_bit_field_rwe #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .i_enable     (<%= enable_signal %>),
+  .o_value      (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb

@@ -0,0 +1,26 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rwe) do
+  sv_rtl do
+    build do
+      unless bit_field.reference?
+        input :register_block, :enable, {
+          name: "i_#{full_name}_enable", data_type: :logic, width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      output :register_block, :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def enable_signal
+      reference_bit_field || enable[loop_variables]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.erb

@@ -0,0 +1,10 @@
+rggen_bit_field_rwl #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .i_lock       (<%= lock_signal %>),
+  .o_value      (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb

@@ -0,0 +1,26 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rwl) do
+  sv_rtl do
+    build do
+      unless bit_field.reference?
+        input :register_block, :lock, {
+          name: "i_#{full_name}_lock", data_type: :logic, width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      output :register_block, :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def lock_signal
+      reference_bit_field || lock[loop_variables]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb

@@ -0,0 +1,11 @@
+rggen_bit_field_rws #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .i_set        (<%= set_signal %>),
+  .i_value      (<%= value_in[loop_variables] %>),
+  .o_value      (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb

@@ -0,0 +1,30 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rws) do
+  sv_rtl do
+    build do
+      unless bit_field.reference?
+        input :register_block, :set, {
+          name: "i_#{full_name}_set", data_type: :logic, width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      input :register_block, :value_in, {
+        name: "i_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      output :register_block, :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def set_signal
+      reference_bit_field || set[loop_variables]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb

@@ -2,8 +2,8 @@ rggen_bit_field_w01trg #(
   .TRIGGER_VALUE  (<%= trigger_value %>),
   .WIDTH          (<%= width %>)
 ) u_bit_field (
-  .i_clk        (<%= register_block.clock %>),
-  .i_rst_n      (<%= register_block.reset %>),
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
   .bit_field_if (<%= bit_field_if %>),
   .o_trigger    (<%= trigger[loop_variables] %>)
 );

data/lib/rggen/systemverilog/rtl/register_block/protocol.rb

@@ -86,6 +86,14 @@ RgGen.define_list_feature(:register_block, :protocol) do
         register_block.total_registers
       end
 
+      def clock
+        register_block.clock
+      end
+
+      def reset
+        register_block.reset
+      end
+
       def register_if
         register_block.register_if
       end

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb

@@ -3,8 +3,8 @@ rggen_apb_adapter #(
   .BUS_WIDTH      (<%= bus_width %>),
   .REGISTERS      (<%= total_registers %>)
 ) u_adapter (
-  .i_clk        (<%= register_block.clock %>),
-  .i_rst_n      (<%= register_block.reset %>),
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
   .apb_if       (<%= apb_if %>),
   .register_if  (<%= register_if %>)
 );

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb

@@ -4,8 +4,8 @@ rggen_axi4lite_adapter #(
   .REGISTERS      (<%= total_registers %>),
   .WRITE_FIRST    (<%= write_first %>)
 ) u_adapter (
-  .i_clk        (<%= register_block.clock %>),
-  .i_rst_n      (<%= register_block.reset %>),
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
   .axi4lite_if  (<%= axi4lite_if %>),
   .register_if  (<%= register_if %>)
 );

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.13.0'
+    VERSION = '0.14.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.13.0
+  version: 0.14.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2019-08-28 00:00:00.000000000 Z
+date: 2019-09-03 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: docile
@@ -52,7 +52,7 @@ dependencies:
     - - ">="
       - !ruby/object:Gem::Version
         version: '0'
-description: 'Structure of SystemVerilog RTL and UVM RAL model writers for Rggen.
+description: 'SystemVerilog RTL and UVM RAL model generators for RgGen.
 
 '
 email:
@@ -84,7 +84,8 @@ files:
 - lib/rggen/systemverilog/ral.rb
 - lib/rggen/systemverilog/ral/bit_field/type.rb
 - lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb
-- lib/rggen/systemverilog/ral/bit_field/type/rwc_rwe_rwl.rb
+- lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb
+- lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb
 - lib/rggen/systemverilog/ral/bit_field/type/w0trg_w1trg.rb
 - lib/rggen/systemverilog/ral/feature.rb
 - lib/rggen/systemverilog/ral/register/type.rb
@@ -110,8 +111,14 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rwl.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rws.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
 - lib/rggen/systemverilog/rtl/feature.rb
@@ -159,5 +166,5 @@ requirements: []
 rubygems_version: 3.0.3
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.13.0
+summary: rggen-systemverilog-0.14.0
 test_files: []

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.erb

@@ -1,16 +0,0 @@
-rggen_bit_field_<%= bit_field.type %> #(
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .i_clk        (<%= register_block.clock %>),
-  .i_rst_n      (<%= register_block.reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-<% if bit_field.type == :rwc %>
-  .i_clear      (<%= control_signal %>),
-<% elsif bit_field.type == :rwe %>
-  .i_enable     (<%= control_signal %>),
-<% else %>
-  .i_lock       (<%= control_signal %>),
-<% end %>
-  .o_value      (<%= value_out[loop_variables] %>)
-);

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc_rwe_rwl.rb

@@ -1,61 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rwe, :rwl]) do
-  sv_rtl do
-    build do
-      if clear_port?
-        input :register_block, :clear, {
-          name: "i_#{full_name}_clear", data_type: :logic, width: 1,
-          array_size: array_size, array_format: array_port_format
-        }
-      end
-      if enable_port?
-        input :register_block, :enable, {
-          name: "i_#{full_name}_enable", data_type: :logic, width: 1,
-          array_size: array_size, array_format: array_port_format
-        }
-      end
-      if lock_port?
-        input :register_block, :lock, {
-          name: "i_#{full_name}_lock", data_type: :logic, width: 1,
-          array_size: array_size, array_format: array_port_format
-        }
-      end
-      output :register_block, :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def clear_port?
-      bit_field.type == :rwc && !bit_field.reference?
-    end
-
-    def enable_port?
-      bit_field.type == :rwe && !bit_field.reference?
-    end
-
-    def lock_port?
-      bit_field.type == :rwl && !bit_field.reference?
-    end
-
-    def control_signal
-      reference_bit_field || control_port[loop_variables]
-    end
-
-    def control_port
-      case bit_field.type
-      when :rwc
-        clear
-      when :rwe
-        enable
-      when :rwl
-        lock
-      end
-    end
-  end
-end