rggen-default-register-map 0.33.0 → 0.34.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019-2024 Taichi Ishitani
+Copyright (c) 2019-2025 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -38,7 +38,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 
 ## Copyright & License
 
-Copyright © 2019-2024 Taichi Ishitani. RgGen::DefaultRegisterMap is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2019-2025 Taichi Ishitani. RgGen::DefaultRegisterMap is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/default_register_map/bit_field/bit_assignment.rb

@@ -85,10 +85,10 @@ RgGen.define_simple_feature(:bit_field, :bit_assignment) do
     end
 
     def preprocess(value)
-      if hash?(value)
-        value
-      elsif match_bit_assignment?(value)
-        split_match_data(match_data)
+      case value
+      when method(:hash?) then value
+      when method(:integer?) then { variable_key(0) => value }
+      when method(:match_bit_assignment?) then split_match_data(match_data)
       else
         error "illegal input value for bit assignment: #{value.inspect}"
       end
@@ -99,14 +99,14 @@ RgGen.define_simple_feature(:bit_field, :bit_assignment) do
     # * https://bugs.ruby-lang.org/issues/19273
     # * https://github.com/rggen/rggen/issues/129#issuecomment-1366666885
     def match_bit_assignment?(value)
-      match_pattern(value) && value.count(':') <= 3
+      string?(value) && match_pattern(value) && value.count(':') <= 3
     end
 
     def split_match_data(match_data)
       match_data
         .to_s
         .split(':')
-        .map.with_index { |value, i| [variable_key(i), value] }
+        .map.with_index { |v, i| [variable_key(i), v] }
         .to_h
     end
 
@@ -134,7 +134,11 @@ RgGen.define_simple_feature(:bit_field, :bit_assignment) do
 
     def lsb_base
       @lsb_base ||=
-        ((bit_field.component_index.zero? && 0) || calc_next_lsb(previous_bit_field))
+        if bit_field.component_index.zero?
+          0
+        else
+          calc_next_lsb(previous_bit_field)
+        end
     end
 
     def previous_bit_field

data/lib/rggen/default_register_map/bit_field/initial_value.rb

@@ -24,8 +24,8 @@ RgGen.define_simple_feature(:bit_field, :initial_value) do
     end
 
     define_helpers do
-      def verify_initial_value(&block)
-        initial_value_verifiers << create_verifier(&block)
+      def verify_initial_value(&)
+        initial_value_verifiers << create_verifier(&)
       end
 
       def initial_value_verifiers

data/lib/rggen/default_register_map/bit_field/labels.rb

@@ -21,8 +21,8 @@ RgGen.define_feature(:bit_field, :labels) do
       end
 
       define_helpers do
-        def verify_label_value(&body)
-          label_value_verifiers << create_verifier(&body)
+        def verify_label_value(&)
+          label_value_verifiers << create_verifier(&)
         end
 
         def label_value_verifiers

data/lib/rggen/default_register_map/bit_field/reference.rb

@@ -43,8 +43,8 @@ RgGen.define_simple_feature(:bit_field, :reference) do
     end
 
     define_helpers do
-      def verify_array(&block)
-        array_verifiers << create_verifier(&block)
+      def verify_array(&)
+        array_verifiers << create_verifier(&)
       end
 
       def array_verifiers

data/lib/rggen/default_register_map/bit_field/type.rb

@@ -115,8 +115,8 @@ RgGen.define_list_feature(:bit_field, :type) do
         types.find(&value.to_sym.method(:casecmp?)) || value
       end
 
-      def target_feature_key(cell)
-        cell
+      def target_feature_key(_configuration, input_value)
+        input_value
       end
     end
   end

data/lib/rggen/default_register_map/comment.rb

@@ -3,16 +3,34 @@
 module RgGen
   module DefaultRegisterMap
     COMMENT = proc do
-      property :comment, initial: -> { '' }
+      property :comment, forward_to: :processed_comment
 
       build do |value|
-        @comment =
+        @raw_comment =
           (array?(value) && value.join("\n") || value.to_s).chomp
       end
 
       printable :comment do
         comment.empty? ? nil : comment
       end
+
+      private
+
+      def processed_comment
+        @processed_comment ||=
+          if erb_template?
+            template = Erubi::Engine.new(@raw_comment)
+            instance_eval(template.src, position.to_s, 1)
+          elsif @raw_comment
+            @raw_comment
+          else
+            ''
+          end
+      end
+
+      def erb_template?
+        /<%.*%>/.match?(@raw_comment)
+      end
     end
   end
 end

data/lib/rggen/default_register_map/global/address_width.rb

@@ -9,22 +9,13 @@ RgGen.define_simple_feature(:global, :address_width) do
         to_int(value) { |v| "cannot convert #{v.inspect} into address width" }
     end
 
-    verify(:component) do
-      error_condition { address_width < min_address_width }
+    verify(:feature) do
+      error_condition { !address_width.positive? }
       message do
-        'input address width is less than minimum address width: ' \
-        "address width #{address_width} " \
-        "minimum address width #{min_address_width}"
+        "non positive value is not allowed for address width: #{address_width}"
       end
     end
 
     printable :address_width
-
-    private
-
-    def min_address_width
-      byte_width = configuration.byte_width
-      byte_width == 1 ? 1 : (byte_width - 1).bit_length
-    end
   end
 end

data/lib/rggen/default_register_map/register/offset_address.rb

@@ -84,11 +84,11 @@ RgGen.define_simple_feature(:register, :offset_address) do
     end
 
     def bus_width
-      configuration.bus_width
+      register_block.bus_width
     end
 
     def byte_width
-      configuration.byte_width
+      register_block.byte_width
     end
 
     def overlap_address_range?(other, shareable)

data/lib/rggen/default_register_map/register/size.rb

@@ -39,7 +39,7 @@ RgGen.define_feature(:register, :size) do
       end
 
       verify(:component) do
-        error_condition { @step && (@step % configuration.byte_width).positive? }
+        error_condition { @step && (@step % register_block.byte_width).positive? }
         message do
           "step size is not multiple of bus width: #{@step}"
         end
@@ -69,7 +69,7 @@ RgGen.define_feature(:register, :size) do
       end
 
       def calc_width
-        bus_width = configuration.bus_width
+        bus_width = register_block.bus_width
         if register.bit_fields.empty?
           bus_width
         else

data/lib/rggen/default_register_map/register/type/indirect.rb

@@ -3,8 +3,8 @@
 RgGen.define_list_item_feature(:register, :type, :indirect) do
   register_map do
     define_helpers do
-      def verify_index(&block)
-        index_verifiers << create_verifier(&block)
+      def verify_index(&)
+        index_verifiers << create_verifier(&)
       end
 
       def index_verifiers

data/lib/rggen/default_register_map/register/type.rb

@@ -90,8 +90,8 @@ RgGen.define_list_feature(:register, :type) do
         find_type(value)
       end
 
-      def target_feature_key(value)
-        (!value.empty_value? && value) || nil
+      def target_feature_key(_configuration, input_value)
+        (!input_value.empty_value? && input_value) || nil
       end
 
       private

data/lib/rggen/default_register_map/register_block/bus_width.rb

@@ -0,0 +1,57 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_block, :bus_width) do
+  [:configuration, :register_map].each do |component_type|
+    component(component_type) do
+      build do |value|
+        @bus_width =
+          to_int(value) { |v| "cannot convert #{v.inspect} into bus width" }
+      end
+
+      verify(:feature) do
+        error_condition { bus_width < 8 }
+        message { "input bus width is less than 8: #{bus_width}" }
+      end
+
+      verify(:feature) do
+        error_condition { !power_of_2?(bus_width) }
+        message { "input bus width is not power of 2: #{bus_width}" }
+      end
+
+      printable :bus_width
+
+      private
+
+      def power_of_2?(value)
+        value.positive? && (value & value.pred).zero?
+      end
+    end
+  end
+
+  configuration do
+    property :bus_width, default: 32
+  end
+
+  register_map do
+    property :bus_width, default: -> { configuration.bus_width }
+    property :byte_width, initial: -> { bus_width / 8 }
+
+    verify(:feature) do
+      error_condition { bus_width > max_bus_width }
+      message do
+        'input bus width is grater than maximum bus width: ' \
+        "bus width #{bus_width} maximum bus width #{max_bus_width}"
+      end
+    end
+
+    def position
+      super || configuration.feature(:bus_width).position
+    end
+
+    private
+
+    def max_bus_width
+      2**(configuration.address_width + 3)
+    end
+  end
+end

data/lib/rggen/default_register_map/register_block/byte_size.rb

@@ -3,12 +3,11 @@
 RgGen.define_simple_feature(:register_block, :byte_size) do
   register_map do
     property :byte_size
-    property :local_address_width
+    property :local_address_width, body: -> { (byte_size - 1).bit_length }
 
     build do |value|
       @byte_size =
         to_int(value) { |v| "cannot convert #{v.inspect} into byte size" }
-      @local_address_width = (@byte_size - 1).bit_length
     end
 
     verify(:feature) do
@@ -31,7 +30,7 @@ RgGen.define_simple_feature(:register_block, :byte_size) do
       end
     end
 
-    verify(:feature) do
+    verify(:component) do
       error_condition { (byte_size % byte_width).positive? }
       message do
         "byte size is not aligned with bus width(#{bus_width}): #{byte_size}"
@@ -47,11 +46,11 @@ RgGen.define_simple_feature(:register_block, :byte_size) do
     end
 
     def byte_width
-      configuration.byte_width
+      register_block.byte_width
     end
 
     def bus_width
-      configuration.bus_width
+      register_block.bus_width
     end
   end
 end

data/lib/rggen/default_register_map/register_file/offset_address.rb

@@ -82,11 +82,11 @@ RgGen.define_simple_feature(:register_file, :offset_address) do
     end
 
     def bus_width
-      configuration.bus_width
+      register_block.bus_width
     end
 
     def byte_width
-      configuration.byte_width
+      register_block.byte_width
     end
 
     def format_address(address)

data/lib/rggen/default_register_map/register_file/size.rb

@@ -30,7 +30,7 @@ RgGen.define_feature(:register_file, :size) do
       end
 
       verify(:component) do
-        error_condition { @step && (@step % configuration.byte_width).positive? }
+        error_condition { @step && (@step % register_block.byte_width).positive? }
         message do
           "step size is not multiple of bus width: #{@step}"
         end

data/lib/rggen/default_register_map/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module DefaultRegisterMap
-    VERSION = '0.33.0'
+    VERSION = '0.34.0'
   end
 end

data/lib/rggen/default_register_map.rb

@@ -1,5 +1,6 @@
 # frozen_string_literal: true
 
+require 'erubi'
 if Gem::Version.new(RUBY_VERSION) < Gem::Version.new('3.3.0')
   require 'facets/range/overlap'
 end
@@ -11,10 +12,10 @@ RgGen.setup_plugin :'rggen-default-register-map' do |plugin|
   plugin.version RgGen::DefaultRegisterMap::VERSION
   plugin.files [
     'default_register_map/global/address_width',
-    'default_register_map/global/bus_width',
     'default_register_map/global/enable_wide_register',
     'default_register_map/register_block/name',
     'default_register_map/register_block/byte_size',
+    'default_register_map/register_block/bus_width',
     'default_register_map/register_block/comment',
     'default_register_map/register_file/name',
     'default_register_map/register_file/offset_address',

metadata

@@ -1,15 +1,28 @@
 --- !ruby/object:Gem::Specification
 name: rggen-default-register-map
 version: !ruby/object:Gem::Version
-  version: 0.33.0
+  version: 0.34.0
 platform: ruby
 authors:
 - Taichi Ishitani
-autorequire: 
 bindir: bin
 cert_chain: []
-date: 2024-01-22 00:00:00.000000000 Z
+date: 2025-01-23 00:00:00.000000000 Z
 dependencies:
+- !ruby/object:Gem::Dependency
+  name: erubi
+  requirement: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: '1.7'
+  type: :runtime
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: '1.7'
 - !ruby/object:Gem::Dependency
   name: facets
   requirement: !ruby/object:Gem::Requirement
@@ -65,7 +78,6 @@ files:
 - lib/rggen/default_register_map/bit_field/type/wos.rb
 - lib/rggen/default_register_map/comment.rb
 - lib/rggen/default_register_map/global/address_width.rb
-- lib/rggen/default_register_map/global/bus_width.rb
 - lib/rggen/default_register_map/global/enable_wide_register.rb
 - lib/rggen/default_register_map/register/comment.rb
 - lib/rggen/default_register_map/register/name.rb
@@ -76,6 +88,7 @@ files:
 - lib/rggen/default_register_map/register/type/indirect.rb
 - lib/rggen/default_register_map/register/type/reserved.rb
 - lib/rggen/default_register_map/register/type/rw.rb
+- lib/rggen/default_register_map/register_block/bus_width.rb
 - lib/rggen/default_register_map/register_block/byte_size.rb
 - lib/rggen/default_register_map/register_block/comment.rb
 - lib/rggen/default_register_map/register_block/name.rb
@@ -93,7 +106,6 @@ metadata:
   rubygems_mfa_required: 'true'
   source_code_uri: https://github.com/rggen/rggen-default-register-map
   wiki_uri: https://github.com/rggen/rggen/wiki
-post_install_message: 
 rdoc_options: []
 require_paths:
 - lib
@@ -101,15 +113,14 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '3.0'
+      version: '3.1'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.5.3
-signing_key: 
+rubygems_version: 3.6.2
 specification_version: 4
-summary: rggen-default-register-map-0.33.0
+summary: rggen-default-register-map-0.34.0
 test_files: []

data/lib/rggen/default_register_map/global/bus_width.rb

@@ -1,31 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_simple_feature(:global, :bus_width) do
-  configuration do
-    property :bus_width, default: 32
-    property :byte_width, initial: -> { bus_width / 8 }
-
-    build do |value|
-      @bus_width =
-        to_int(value) { |v| "cannot convert #{v.inspect} into bus width" }
-    end
-
-    verify(:feature) do
-      error_condition { bus_width < 8 }
-      message { "input bus width is less than 8: #{bus_width}" }
-    end
-
-    verify(:feature) do
-      error_condition { !power_of_2?(bus_width) }
-      message { "input bus width is not power of 2: #{bus_width}" }
-    end
-
-    printable :bus_width
-
-    private
-
-    def power_of_2?(value)
-      value.positive? && (value & value.pred).zero?
-    end
-  end
-end