rggen-default-register-map 0.18.0 → 0.23.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019 Taichi Ishitani
+Copyright (c) 2019-2020 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -1,12 +1,12 @@
 [![Gem Version](https://badge.fury.io/rb/rggen-default-register-map.svg)](https://badge.fury.io/rb/rggen-default-register-map)
-[![Build Status](https://travis-ci.com/rggen/rggen-default-register-map.svg?branch=master)](https://travis-ci.com/rggen/rggen-default-register-map)
+[![CI](https://github.com/rggen/rggen-default-register-map/workflows/CI/badge.svg)](https://github.com/rggen/rggen-default-register-map/actions?query=workflow%3ACI)
 [![Maintainability](https://api.codeclimate.com/v1/badges/73177494e096af47f09e/maintainability)](https://codeclimate.com/github/rggen/rggen-default-register-map/maintainability)
 [![codecov](https://codecov.io/gh/rggen/rggen-default-register-map/branch/master/graph/badge.svg)](https://codecov.io/gh/rggen/rggen-default-register-map)
 [![Quality Gate Status](https://sonarcloud.io/api/project_badges/measure?project=rggen_rggen-default-register-map&metric=alert_status)](https://sonarcloud.io/dashboard?id=rggen_rggen-default-register-map)
 [![Gitter](https://badges.gitter.im/rggen/rggen.svg)](https://gitter.im/rggen/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
 
 
-# Rggen::DefaultRegisterMap
+# RgGen::DefaultRegisterMap
 
 RgGen::DefaultRegisterMap provides following features.
 
@@ -38,7 +38,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 
 ## Copyright & License
 
-Copyright © 2019 Taichi Ishitani. RgGen::DefaultRegisterMap is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2019-2020 Taichi Ishitani. RgGen::DefaultRegisterMap is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/default_register_map.rb

@@ -4,9 +4,10 @@ require_relative 'default_register_map/version'
 
 module RgGen
   module DefaultRegisterMap
+    PLUGIN_NAME = :'rggen-default-register-map'
+
     FEATURES = [
       'default_register_map/bit_field/bit_assignment',
-      'default_register_map/bit_field/comment',
       'default_register_map/bit_field/initial_value',
       'default_register_map/bit_field/name',
       'default_register_map/bit_field/reference',
@@ -16,14 +17,19 @@ module RgGen
       'default_register_map/bit_field/type/ro',
       'default_register_map/bit_field/type/rof',
       'default_register_map/bit_field/type/rs',
-      'default_register_map/bit_field/type/rw_w1',
+      'default_register_map/bit_field/type/rw_w1_wrc_wrs',
       'default_register_map/bit_field/type/rwc_rws',
       'default_register_map/bit_field/type/rwe_rwl',
-      'default_register_map/bit_field/type/w0c_w1c',
-      'default_register_map/bit_field/type/w0crs_w1crs_w0src_w1src',
-      'default_register_map/bit_field/type/w0s_w1s',
+      'default_register_map/bit_field/type/w0c_w1c_wc',
+      'default_register_map/bit_field/type/w0crs_w1crs_wcrs',
+      'default_register_map/bit_field/type/w0s_w1s_ws',
+      'default_register_map/bit_field/type/w0src_w1src_wsrc',
+      'default_register_map/bit_field/type/w0t_w1t',
       'default_register_map/bit_field/type/w0trg_w1trg',
       'default_register_map/bit_field/type/wo_wo1',
+      'default_register_map/bit_field/type/woc',
+      'default_register_map/bit_field/type/wos',
+      'default_register_map/common/comment',
       'default_register_map/global/address_width',
       'default_register_map/global/bus_width',
       'default_register_map/register/name',
@@ -33,7 +39,10 @@ module RgGen
       'default_register_map/register/type/external',
       'default_register_map/register/type/indirect',
       'default_register_map/register_block/byte_size',
-      'default_register_map/register_block/name'
+      'default_register_map/register_block/name',
+      'default_register_map/register_file/name',
+      'default_register_map/register_file/offset_address',
+      'default_register_map/register_file/size'
     ].freeze
 
     def self.load_features

data/lib/rggen/default_register_map/bit_field/bit_assignment.rb

@@ -100,7 +100,7 @@ RgGen.define_simple_feature(:bit_field, :bit_assignment) do
 
     def previous_bit_field
       index = bit_field.component_index - 1
-      register.bit_fields[index]
+      bit_fields[index]
     end
 
     def calc_next_lsb(bit_field)
@@ -138,9 +138,7 @@ RgGen.define_simple_feature(:bit_field, :bit_assignment) do
     end
 
     def overlap?
-      register
-        .bit_fields
-        .any? { |bit_field| (bit_field.bit_map & bit_map).nonzero? }
+      bit_fields.any? { |bit_field| (bit_field.bit_map & bit_map).nonzero? }
     end
   end
 end

data/lib/rggen/default_register_map/bit_field/initial_value.rb

@@ -8,8 +8,8 @@ RgGen.define_simple_feature(:bit_field, :initial_value) do
     property :fixed_initial_value?, forward_to: :fixed?
     property :initial_value_array?, forward_to: :array?
 
-    input_pattern parameterized: /default:(#{integer})/,
-                  array: /#{integer}(?:[,\n]#{integer})+/
+    input_pattern [{ parameterized: /default:(#{integer})/,
+                     array: /#{integer}(?:[,\n]#{integer})+/ }]
 
     build do |value|
       @input_format =

data/lib/rggen/default_register_map/bit_field/name.rb

@@ -2,19 +2,15 @@
 
 RgGen.define_simple_feature(:bit_field, :name) do
   register_map do
-    property :name, initial: -> { register.name }
+    property :name, default: -> { register.name }
     property :full_name, forward_to: :get_full_name
 
     input_pattern variable_name
 
     build do |value|
-      @name =
-        if pattern_matched?
-          match_data.to_s
-        else
-          error "illegal input value for bit field name: #{value.inspect}"
-        end
-      @full_name = [register.name, @name]
+      pattern_matched? ||
+        (error "illegal input value for bit field name: #{value.inspect}")
+      @name = match_data.to_s
     end
 
     verify(:feature) do
@@ -22,16 +18,19 @@ RgGen.define_simple_feature(:bit_field, :name) do
       message { "duplicated bit field name: #{name}" }
     end
 
-    printable :name
+    printable(:name) do
+      RgGen::Core::Utility::CodeUtility
+        .array_name(name, Array(bit_field.sequence_size))
+    end
 
     private
 
     def get_full_name(separator = '.')
-      @full_name&.join(separator) || register.name
+      [register.full_name(separator), *@name].join(separator)
     end
 
     def duplicated_name?
-      register.bit_fields.any? { |bit_field| bit_field.name == name }
+      bit_fields.any? { |bit_field| bit_field.name == name }
     end
   end
 end

data/lib/rggen/default_register_map/bit_field/reference.rb

@@ -7,18 +7,12 @@ RgGen.define_simple_feature(:bit_field, :reference) do
     property :reference_width, forward_to: :required_width
     property :find_reference, forward_to: :find_reference_bit_field
 
-    input_pattern [
-      /(#{variable_name})\.(#{variable_name})/,
-      /(#{variable_name})/
-    ]
+    input_pattern /(#{variable_name}(?:\.#{variable_name})*)/
 
     build do |value|
-      @input_reference =
-        if pattern_matched?
-          match_data[1..2].compact.join('.')
-        else
-          error "illegal input value for reference: #{value.inspect}"
-        end
+      pattern_matched? ||
+        (error "illegal input value for reference: #{value.inspect}")
+      @input_reference = match_data.to_s
     end
 
     verify(:component) do
@@ -38,20 +32,46 @@ RgGen.define_simple_feature(:bit_field, :reference) do
 
     verify(:all) do
       error_condition do
-        reference? && !register.array? && reference_bit_field.register.array?
+        reference? && within_array?(reference_bit_field) &&
+          (bit_field.depth != reference_bit_field.depth)
       end
       message do
-        'bit field of array register is not allowed for ' \
-        "reference bit field: #{@input_reference}"
+        'depth of layer is not matched: ' \
+        "own #{bit_field.depth} " \
+        "reference #{reference_bit_field.depth}"
+      end
+    end
+
+    define_helpers do
+      def verify_array(&block)
+        array_verifiers << create_verifier(&block)
+      end
+
+      def array_verifiers
+        @array_verifiers ||= []
       end
     end
 
     verify(:all) do
-      error_condition { reference? && !match_array_size? }
-      message do
+      check_error do
+        reference? && within_array?(reference_bit_field) &&
+          helper.array_verifiers.each(&method(:verify_array))
+      end
+    end
+
+    verify_array do
+      error_condition { |own, ref| !own.array? && ref.array? }
+      message do |*_, layer|
+        "bit field within array #{layer.to_s.tr('_', ' ')} is not allowed for " \
+        "reference bit field: #{@input_reference}"
+      end
+    end
+
+    verify_array do
+      error_condition { |own, ref| unmatch_array_size?(own, ref) }
+      message do |own, ref|
         'array size is not matched: ' \
-        "own #{register.array_size} " \
-        "reference #{reference_bit_field.register.array_size}"
+        "own #{own.array_size} reference #{ref.array_size}"
       end
     end
 
@@ -66,7 +86,7 @@ RgGen.define_simple_feature(:bit_field, :reference) do
     end
 
     verify(:all) do
-      error_condition { reference? && !match_sequence_size? }
+      error_condition { reference? && unmatch_sequence_size? }
       message do
         'sequence size is not matched: ' \
         "own #{bit_field.sequence_size} " \
@@ -125,14 +145,23 @@ RgGen.define_simple_feature(:bit_field, :reference) do
       find_reference_bit_field(register_block.bit_fields)
     end
 
-    def match_array_size?
-      !(register.array? && reference_bit_field.register.array?) ||
-        register.array_size == reference_bit_field.register.array_size
+    def within_array?(bit_field)
+      bit_field.register_files.any?(&:array?) || bit_field.register.array?
+    end
+
+    def verify_array(verifier)
+      [*register_files, register]
+        .zip([*reference_bit_field.register_files, reference_bit_field.register])
+        .each { |own, ref| verifier.verify(self, own, ref, own.layer) }
+    end
+
+    def unmatch_array_size?(own, ref)
+      own.array? && ref.array? && own.array_size != ref.array_size
     end
 
-    def match_sequence_size?
-      !(bit_field.sequential? && reference_bit_field.sequential?) ||
-        bit_field.sequence_size == reference_bit_field.sequence_size
+    def unmatch_sequence_size?
+      bit_field.sequential? && reference_bit_field.sequential? &&
+        (bit_field.sequence_size != reference_bit_field.sequence_size)
     end
 
     def required_width

data/lib/rggen/default_register_map/bit_field/type/rw_w1_wrc_wrs.rb

@@ -0,0 +1,9 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wrc, :wrs]) do
+  register_map do
+    read_write
+    non_volatile
+    initial_value require: true
+  end
+end

data/lib/rggen/default_register_map/bit_field/type/rwe_rwl.rb

@@ -6,5 +6,22 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
     volatile? { !bit_field.reference? }
     initial_value require: true
     reference use: true, width: 1
+
+    verify(:all) do
+      error_condition do
+        bit_field.reference? &&
+          register.full_name == reference_register.full_name
+      end
+      message do
+        'bit field within the same register is not allowed for ' \
+        "reference bit field: #{bit_field.reference.full_name}"
+      end
+    end
+
+    private
+
+    def reference_register
+      bit_field.reference.register
+    end
   end
 end

data/lib/rggen/default_register_map/bit_field/type/{w0c_w1c.rb → w0c_w1c_wc.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:w0c, :w1c]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:w0c, :w1c, :wc]) do
   register_map do
     read_write
     reference use: true

data/lib/rggen/default_register_map/bit_field/type/{w0crs_w1crs_w0src_w1src.rb → w0crs_w1crs_wcrs.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs, :w0src, :w1src]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs, :wcrs]) do
   register_map do
     read_write
     non_volatile

data/lib/rggen/default_register_map/bit_field/type/{w0s_w1s.rb → w0s_w1s_ws.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:w0s, :w1s]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:w0s, :w1s, :ws]) do
   register_map do
     read_write
     initial_value require: true

data/lib/rggen/default_register_map/bit_field/type/w0src_w1src_wsrc.rb

@@ -0,0 +1,9 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src, :wsrc]) do
+  register_map do
+    read_write
+    non_volatile
+    initial_value require: true
+  end
+end

data/lib/rggen/default_register_map/bit_field/type/{rw_w1.rb → w0t_w1t.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
   register_map do
     read_write
     non_volatile

data/lib/rggen/default_register_map/bit_field/type/woc.rb

@@ -0,0 +1,9 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :woc) do
+  register_map do
+    write_only
+    reference use: true
+    initial_value require: true
+  end
+end

data/lib/rggen/default_register_map/bit_field/type/wos.rb

@@ -0,0 +1,8 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :wos) do
+  register_map do
+    write_only
+    initial_value require: true
+  end
+end

data/lib/rggen/default_register_map/common/comment.rb

@@ -0,0 +1,18 @@
+# frozen_string_literal: true
+
+[:register_block, :register_file, :register, :bit_field].each do |layer|
+  RgGen.define_simple_feature(layer, :comment) do
+    register_map do
+      property :comment, initial: -> { '' }
+
+      build do |value|
+        @comment =
+          (value.is_a?(Array) && value.join("\n") || value.to_s).chomp
+      end
+
+      printable :comment do
+        comment.empty? ? nil : comment
+      end
+    end
+  end
+end

data/lib/rggen/default_register_map/register/name.rb

@@ -3,16 +3,14 @@
 RgGen.define_simple_feature(:register, :name) do
   register_map do
     property :name
+    property :full_name, forward_to: :get_full_name
 
     input_pattern variable_name
 
     build do |value|
-      @name =
-        if pattern_matched?
-          match_data.to_s
-        else
-          error "illegal input value for register name: #{value.inspect}"
-        end
+      pattern_matched? ||
+        (error "illegal input value for register name: #{value.inspect}")
+      @name = match_data.to_s
     end
 
     verify(:feature) do
@@ -25,12 +23,29 @@ RgGen.define_simple_feature(:register, :name) do
       message { "duplicated register name: #{name}" }
     end
 
-    printable :name
+    printable(:name) do
+      array_name
+    end
+
+    printable(:layer_name) do
+      [register_file&.printables&.fetch(:layer_name), array_name]
+        .compact.join('.')
+    end
 
     private
 
+    def get_full_name(separator = '.')
+      [*register_file&.full_name(separator), name].join(separator)
+    end
+
     def duplicated_name?
-      register_block.registers.any? { |register| register.name == name }
+      files_and_registers
+        .any? { |file_or_register| file_or_register.name == name }
+    end
+
+    def array_name
+      RgGen::Core::Utility::CodeUtility
+        .array_name(name, register.array_size)
     end
   end
 end

data/lib/rggen/default_register_map/register/offset_address.rb

@@ -3,6 +3,7 @@
 RgGen.define_simple_feature(:register, :offset_address) do
   register_map do
     property :offset_address, initial: -> { default_offset_address }
+    property :expanded_offset_addresses, forward_to: :expand_addresses
     property :address_range, initial: -> { start_address..end_address }
     property :overlap?, forward_to: :overlap_address_range?
 
@@ -29,7 +30,10 @@ RgGen.define_simple_feature(:register, :offset_address) do
     end
 
     verify(:component) do
-      error_condition { end_address > register_block.byte_size }
+      error_condition do
+        register.parent.register_block? &&
+          end_address > register_block.byte_size
+      end
       message do
         'offset address range exceeds byte size of register block' \
         "(#{register_block.byte_size}): " \
@@ -39,32 +43,49 @@ RgGen.define_simple_feature(:register, :offset_address) do
 
     verify(:component) do
       error_condition do
-        register_block.registers.any? do |register|
-          overlap_address_range?(register) &&
-            support_unique_range_only?(register)
+        files_and_registers.any? do |other|
+          overlap_address_range?(other) && exclusive_range?(other)
         end
       end
       message do
         'offset address range overlaps with other offset address range: ' \
-        "0x#{start_address.to_s(16)}-0x#{end_address.to_s(16)}"
+        "0x#{start_address(true).to_s(16)}-0x#{end_address(true).to_s(16)}"
       end
     end
 
     printable(:offset_address) do
-      [start_address, end_address]
-        .map(&method(:printable_address)).join(' - ')
+      expand_addresses.map(&method(:format_address))
     end
 
     private
 
     def default_offset_address
       register.component_index.zero? && 0 ||
-        (previous_register.offset_address + previous_register.byte_size)
+        (previous_component.offset_address + previous_component.byte_size)
+    end
+
+    def start_address(full = false)
+      full && expand_addresses.first || offset_address
+    end
+
+    def end_address(full = false)
+      start_address(full) + register.byte_size - 1
     end
 
-    def previous_register
+    def expand_addresses
+      upper_offsets = register_file&.expanded_offset_addresses || [0]
+      upper_offsets.product(expand_local_addresses).map(&:sum)
+    end
+
+    def expand_local_addresses
+      Array.new(shared_address? && 1 || register.count) do |i|
+        offset_address + register.byte_width * i
+      end
+    end
+
+    def previous_component
       index = register.component_index - 1
-      register_block.registers[index]
+      files_and_registers[index]
     end
 
     def bus_width
@@ -75,35 +96,30 @@ RgGen.define_simple_feature(:register, :offset_address) do
       configuration.byte_width
     end
 
-    def start_address
-      offset_address
-    end
-
-    def end_address
-      start_address + register.byte_size - 1
+    def overlap_address_range?(other)
+      overlap_range?(other) && competitive_access?(other)
     end
 
-    def overlap_address_range?(other_register)
-      overlap_range?(other_register) && match_access?(other_register)
+    def overlap_range?(other)
+      self_range = address_range
+      othre_range = other.address_range
+      self_range.include?(othre_range.first) || othre_range.include?(self_range.first)
     end
 
-    def overlap_range?(other_register)
-      own = address_range
-      other = other_register.address_range
-      own.include?(other.first) || other.include?(own.first)
+    def competitive_access?(other)
+      other.register_file? ||
+        [:writable?, :readable?].any? { |access| [register, other].all?(&access) }
     end
 
-    def match_access?(other_register)
-      (register.writable? && other_register.writable?) ||
-        (register.readable? && other_register.readable?)
+    def exclusive_range?(other)
+      other.register_file? || !(shared_address? && register.match_type?(other))
     end
 
-    def support_unique_range_only?(other_register)
-      !(register.settings[:support_overlapped_address] &&
-        register.match_type?(other_register))
+    def shared_address?
+      register.settings[:support_shared_address]
     end
 
-    def printable_address(address)
+    def format_address(address)
       print_width = (register_block.local_address_width + 3) / 4
       format('0x%0*x', print_width, address)
     end

data/lib/rggen/default_register_map/register/size.rb

@@ -5,10 +5,10 @@ RgGen.define_simple_feature(:register, :size) do
     property :size
     property :width, initial: -> { calc_width }
     property :byte_width, initial: -> { width / 8 }
-    property :byte_size, initial: -> { calc_byte_size }
+    property :byte_size, forward_to: :calc_byte_size
     property :array?, forward_to: :array_register?
     property :array_size, forward_to: :array_registers
-    property :count, initial: -> { calc_count }
+    property :count, forward_to: :calc_count
 
     input_pattern [
       /(#{integer}(:?,#{integer})*)/,
@@ -26,10 +26,6 @@ RgGen.define_simple_feature(:register, :size) do
       end
     end
 
-    printable(:array_size) do
-      (array_register? || nil) && "[#{array_registers.join(', ')}]"
-    end
-
     private
 
     def parse_values(values)
@@ -72,9 +68,9 @@ RgGen.define_simple_feature(:register, :size) do
         .max
     end
 
-    def calc_byte_size
-      if register.settings[:byte_size]
-        instance_exec(&register.settings[:byte_size])
+    def calc_byte_size(whole_size = true)
+      if !whole_size || register.settings[:support_shared_address]
+        byte_width
       else
         Array(@size).reduce(1, :*) * byte_width
       end
@@ -88,8 +84,8 @@ RgGen.define_simple_feature(:register, :size) do
       array_register? && @size || nil
     end
 
-    def calc_count
-      Array(array_registers).reduce(1, :*)
+    def calc_count(whole_count = true)
+      whole_count ? (@count ||= Array(array_registers).reduce(1, :*)) : 1
     end
   end
 end

data/lib/rggen/default_register_map/register/type.rb

@@ -31,12 +31,8 @@ RgGen.define_list_feature(:register, :type) do
           settings[:support_array] = true
         end
 
-        def byte_size(&block)
-          settings[:byte_size] = block
-        end
-
-        def support_overlapped_address
-          settings[:support_overlapped_address] = true
+        def support_shared_address
+          settings[:support_shared_address] = true
         end
       end
 

data/lib/rggen/default_register_map/register/type/external.rb

@@ -6,11 +6,22 @@ RgGen.define_list_item_feature(:register, :type, :external) do
     readable? { true }
     no_bit_fields
 
+    verify(:feature) do
+      error_condition { register.parent.register_file? }
+      message do
+        'external register type is not allowed to be put within register file'
+      end
+    end
+
     verify(:component) do
       error_condition { register.size && register.size.length > 1 }
       message do
         'external register type supports single size definition only'
       end
     end
+
+    printable(:byte_size) do
+      "#{register.byte_size} bytes"
+    end
   end
 end

data/lib/rggen/default_register_map/register/type/indirect.rb

@@ -40,21 +40,25 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
       index_entries.map { |entry| entry.find_index_field(bit_fields) }
     end
 
-    byte_size { byte_width }
+    support_shared_address
     support_array_register
-    support_overlapped_address
 
     input_pattern [
-      /(#{variable_name}\.#{variable_name})/,
-      /(#{variable_name}\.#{variable_name}):(#{integer})?/,
-      /(#{variable_name})/,
-      /(#{variable_name}):(#{integer})?/
+      /(#{variable_name}(?:\.#{variable_name})*)/,
+      /(#{variable_name}(?:\.#{variable_name})*):(#{integer})/
     ], match_automatically: false
 
     build do
       @index_entries = parse_index_entries
     end
 
+    verify(:component) do
+      error_condition do
+        !(register.array? || array_index_fields.empty?)
+      end
+      message { 'array indices are given to non-array register' }
+    end
+
     verify(:component) do
       error_condition do
         register.array? &&
@@ -95,17 +99,27 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
 
     verify_index do
       error_condition do |index|
-        index_field(index).register.name == register.name
+        index_field(index).register.full_name == register.full_name
       end
       message do |index|
         "own bit field is not allowed for indirect index: #{index.name}"
       end
     end
 
+    verify_index do
+      error_condition do |index|
+        index_field(index).register_files.any?(&:array?)
+      end
+      message do |index|
+        'bit field within array register file is not allowed ' \
+        "for indirect index: #{index.name}"
+      end
+    end
+
     verify_index do
       error_condition { |index| index_field(index).register.array? }
       message do |index|
-        'bit field of array register is not allowed ' \
+        'bit field within array register is not allowed ' \
         "for indirect index: #{index.name}"
       end
     end
@@ -219,8 +233,8 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
     end
 
     def distinguishable?
-      register_block
-        .registers.select { |other| share_same_range?(other) }
+      files_and_registers
+        .select { |other| other.register? && share_same_range?(other) }
         .all? { |other| distinguishable_indices?(other.index_entries) }
     end
 

data/lib/rggen/default_register_map/register_block/name.rb

@@ -7,12 +7,9 @@ RgGen.define_simple_feature(:register_block, :name) do
     input_pattern variable_name
 
     build do |value|
-      @name =
-        if pattern_matched?
-          match_data.to_s
-        else
-          error "illegal input value for register block name: #{value.inspect}"
-        end
+      pattern_matched? ||
+        (error "illegal input value for register block name: #{value.inspect}")
+      @name = match_data.to_s
     end
 
     verify(:feature) do
@@ -30,9 +27,7 @@ RgGen.define_simple_feature(:register_block, :name) do
     private
 
     def duplicated_name?
-      register_map
-        .register_blocks
-        .any? { |register_block| register_block.name == name }
+      register_blocks.any? { |register_block| register_block.name == name }
     end
   end
 end

data/lib/rggen/default_register_map/register_file/name.rb

@@ -0,0 +1,53 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_file, :name) do
+  register_map do
+    property :name
+    property :full_name, forward_to: :get_full_name
+
+    input_pattern variable_name
+
+    build do |value|
+      pattern_matched? ||
+        (error "illegal input value for register file name: #{value.inspect}")
+      @name = match_data.to_s
+    end
+
+    verify(:feature) do
+      error_condition { !name }
+      message { 'no register file name is given' }
+    end
+
+    verify(:feature) do
+      error_condition { duplicated_name? }
+      message { "duplicated register file name: #{name}" }
+    end
+
+    printable(:name) do
+      array_name
+    end
+
+    printable(:layer_name) do
+      [
+        register_file(:upper)&.printables&.fetch(:layer_name),
+        array_name
+      ].compact.join('.')
+    end
+
+    private
+
+    def get_full_name(separator = '.')
+      [*register_file(:upper)&.full_name(separator), name].join(separator)
+    end
+
+    def duplicated_name?
+      files_and_registers
+        .any? { |file_or_register| file_or_register.name == name }
+    end
+
+    def array_name
+      RgGen::Core::Utility::CodeUtility
+        .array_name(name, register_file.array_size)
+    end
+  end
+end

data/lib/rggen/default_register_map/register_file/offset_address.rb

@@ -0,0 +1,107 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_file, :offset_address) do
+  register_map do
+    property :offset_address, initial: -> { defalt_offset_address }
+    property :expanded_offset_addresses, forward_to: :expand_addresses
+    property :address_range, initial: -> { start_address..end_address }
+
+    build do |value|
+      @offset_address =
+        begin
+          Integer(value)
+        rescue ArgumentError, TypeError
+          error "cannot convert #{value.inspect} into offset address"
+        end
+    end
+
+    verify(:feature) do
+      error_condition { offset_address.negative? }
+      message { "offset address is less than 0: #{offset_address}" }
+    end
+
+    verify(:feature) do
+      error_condition { (offset_address % byte_width).nonzero? }
+      message do
+        "offset address is not aligned with bus width(#{bus_width}): " \
+        "0x#{offset_address.to_s(16)}"
+      end
+    end
+
+    verify(:component) do
+      error_condition do
+        register_file.parent.register_block? &&
+          end_address > register_block.byte_size
+      end
+      message do
+        'offset address range exceeds byte size of register block' \
+        "(#{register_block.byte_size}): " \
+        "0x#{start_address.to_s(16)}-0x#{end_address.to_s(16)}"
+      end
+    end
+
+    verify(:component) do
+      error_condition do
+        files_and_registers.any?(&method(:overlap_address_range?))
+      end
+      message do
+        'offset address range overlaps with other offset address range: ' \
+        "0x#{start_address(true).to_s(16)}-0x#{end_address(true).to_s(16)}"
+      end
+    end
+
+    printable(:offset_address) do
+      expand_addresses.map(&method(:format_address))
+    end
+
+    private
+
+    def defalt_offset_address
+      register_file.component_index.zero? && 0 ||
+        (previous_component.offset_address + previous_component.byte_size)
+    end
+
+    def previous_component
+      index = register_file.component_index - 1
+      block_or_file.files_and_registers[index]
+    end
+
+    def start_address(full = false)
+      full && expand_addresses.first || offset_address
+    end
+
+    def end_address(full = false)
+      start_address(full) + register_file.byte_size - 1
+    end
+
+    def expand_addresses
+      uppser_addresses = register_file(:upper)&.expanded_offset_addresses || [0]
+      uppser_addresses.product(expand_local_addresses).map(&:sum)
+    end
+
+    def expand_local_addresses
+      Array.new(register_file.array_size&.inject(:*) || 1) do |i|
+        offset_address + register_file.byte_size(false) * i
+      end
+    end
+
+    def overlap_address_range?(other)
+      self_range = address_range
+      other_range = other.address_range
+      self_range.include?(other_range.first) || other_range.include?(self_range.first)
+    end
+
+    def bus_width
+      configuration.bus_width
+    end
+
+    def byte_width
+      configuration.byte_width
+    end
+
+    def format_address(address)
+      print_width = (register_block.local_address_width.to_f / 4.0).ceil
+      format('0x%0*x', print_width, address)
+    end
+  end
+end

data/lib/rggen/default_register_map/register_file/size.rb

@@ -0,0 +1,60 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_file, :size) do
+  register_map do
+    property :size
+    property :byte_size, forward_to: :calc_byte_size
+    property :array?, body: -> { !@size.nil? }
+    property :array_size, forward_to: :size
+    property :count, forward_to: :calc_count
+
+    input_pattern [
+      /(#{integer}(:?,#{integer})*)/,
+      /\[(#{integer}(:?,#{integer})*)\]/
+    ], match_automatically: false
+
+    build do |values|
+      @size =
+        (values.is_a?(String) && parse_string_value(values) || Array(values))
+          .map(&method(:convert_value))
+    end
+
+    verify(:feature) do
+      error_condition { array? && !size.all?(&:positive?) }
+      message do
+        "non positive value(s) are not allowed for register file size: #{size}"
+      end
+    end
+
+    private
+
+    def parse_string_value(value)
+      match_pattern(value) && match_data.captures.first.split(',') ||
+        (error "illegal input value for register file size: #{value.inspect}")
+    end
+
+    def convert_value(value)
+      Integer(value)
+    rescue ArgumentError, TypeError
+      error "cannot convert #{value.inspect} into register file size"
+    end
+
+    def calc_byte_size(whole_size = true)
+      (whole_size ? total_entries : 1) * entry_byte_size
+    end
+
+    def entry_byte_size
+      register_file.files_and_registers
+        .map { |r| r.offset_address + r.byte_size }.max
+    end
+
+    def calc_count(whole_count = true)
+      (whole_count ? total_entries : 1) *
+        register_file.files_and_registers.sum(&:count)
+    end
+
+    def total_entries
+      size&.inject(:*) || 1
+    end
+  end
+end

data/lib/rggen/default_register_map/setup.rb

@@ -2,10 +2,17 @@
 
 require 'rggen/default_register_map'
 
-RgGen.setup :'rggen-defualt-register-map', RgGen::DefaultRegisterMap do |builder|
+RgGen.setup RgGen::DefaultRegisterMap do |builder|
   builder.enable :global, [:bus_width, :address_width]
-  builder.enable :register_block, [:name, :byte_size]
-  builder.enable :register, [:name, :offset_address, :size, :type]
+  builder.enable :register_block, [
+    :name, :byte_size, :comment
+  ]
+  builder.enable :register_file, [
+    :name, :offset_address, :size, :comment
+  ]
+  builder.enable :register, [
+    :name, :offset_address, :size, :type, :comment
+  ]
   builder.enable :register, :type, [:external, :indirect]
   builder.enable :bit_field, [
     :name, :bit_assignment, :type, :initial_value, :reference, :comment
@@ -13,7 +20,8 @@ RgGen.setup :'rggen-defualt-register-map', RgGen::DefaultRegisterMap do |builder
   builder.enable :bit_field, :type, [
     :rc, :reserved, :ro, :rof, :rs,
     :rw, :rwc, :rwe, :rwl, :rws,
-    :w0c, :w0crs, :w0s, :w0src, :w0trg,
-    :w1, :w1c, :w1crs, :w1s, :w1src, :w1trg, :wo, :wo1
+    :w0c, :w0crs, :w0s, :w0src, :w0t, :w0trg,
+    :w1, :w1c, :w1crs, :w1s, :w1src, :w1t, :w1trg, :wo, :wo1,
+    :woc, :wos, :wc, :wcrs, :wrc, :wrs, :ws, :wsrc
   ]
 end

data/lib/rggen/default_register_map/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module DefaultRegisterMap
-    VERSION = '0.18.0'
+    VERSION = '0.23.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-default-register-map
 version: !ruby/object:Gem::Version
-  version: 0.18.0
+  version: 0.23.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2019-11-19 00:00:00.000000000 Z
+date: 2020-08-25 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -36,7 +36,6 @@ files:
 - README.md
 - lib/rggen/default_register_map.rb
 - lib/rggen/default_register_map/bit_field/bit_assignment.rb
-- lib/rggen/default_register_map/bit_field/comment.rb
 - lib/rggen/default_register_map/bit_field/initial_value.rb
 - lib/rggen/default_register_map/bit_field/name.rb
 - lib/rggen/default_register_map/bit_field/reference.rb
@@ -46,14 +45,19 @@ files:
 - lib/rggen/default_register_map/bit_field/type/ro.rb
 - lib/rggen/default_register_map/bit_field/type/rof.rb
 - lib/rggen/default_register_map/bit_field/type/rs.rb
-- lib/rggen/default_register_map/bit_field/type/rw_w1.rb
+- lib/rggen/default_register_map/bit_field/type/rw_w1_wrc_wrs.rb
 - lib/rggen/default_register_map/bit_field/type/rwc_rws.rb
 - lib/rggen/default_register_map/bit_field/type/rwe_rwl.rb
-- lib/rggen/default_register_map/bit_field/type/w0c_w1c.rb
-- lib/rggen/default_register_map/bit_field/type/w0crs_w1crs_w0src_w1src.rb
-- lib/rggen/default_register_map/bit_field/type/w0s_w1s.rb
+- lib/rggen/default_register_map/bit_field/type/w0c_w1c_wc.rb
+- lib/rggen/default_register_map/bit_field/type/w0crs_w1crs_wcrs.rb
+- lib/rggen/default_register_map/bit_field/type/w0s_w1s_ws.rb
+- lib/rggen/default_register_map/bit_field/type/w0src_w1src_wsrc.rb
+- lib/rggen/default_register_map/bit_field/type/w0t_w1t.rb
 - lib/rggen/default_register_map/bit_field/type/w0trg_w1trg.rb
 - lib/rggen/default_register_map/bit_field/type/wo_wo1.rb
+- lib/rggen/default_register_map/bit_field/type/woc.rb
+- lib/rggen/default_register_map/bit_field/type/wos.rb
+- lib/rggen/default_register_map/common/comment.rb
 - lib/rggen/default_register_map/global/address_width.rb
 - lib/rggen/default_register_map/global/bus_width.rb
 - lib/rggen/default_register_map/register/name.rb
@@ -64,6 +68,9 @@ files:
 - lib/rggen/default_register_map/register/type/indirect.rb
 - lib/rggen/default_register_map/register_block/byte_size.rb
 - lib/rggen/default_register_map/register_block/name.rb
+- lib/rggen/default_register_map/register_file/name.rb
+- lib/rggen/default_register_map/register_file/offset_address.rb
+- lib/rggen/default_register_map/register_file/size.rb
 - lib/rggen/default_register_map/setup.rb
 - lib/rggen/default_register_map/version.rb
 homepage: https://github.com/rggen/rggen-default-register-map
@@ -82,15 +89,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '2.3'
+      version: '2.4'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.0.3
+rubygems_version: 3.1.2
 signing_key: 
 specification_version: 4
-summary: rggen-default-register-map-0.18.0
+summary: rggen-default-register-map-0.23.0
 test_files: []

data/lib/rggen/default_register_map/bit_field/comment.rb

@@ -1,18 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_simple_feature(:bit_field, :comment) do
-  register_map do
-    property :comment, body: -> { @comment ||= '' }
-
-    build do |value|
-      @comment =
-        if value.is_a?(Array)
-          value.join("\n")
-        else
-          value.to_s
-        end
-    end
-
-    printable :comment
-  end
-end