rggen-default-register-map 0.13.0

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Files changed (36) hide show
  1. checksums.yaml +7 -0
  2. data/CODE_OF_CONDUCT.md +74 -0
  3. data/LICENSE +21 -0
  4. data/README.md +45 -0
  5. data/lib/rggen/default_register_map.rb +46 -0
  6. data/lib/rggen/default_register_map/bit_field/bit_assignment.rb +122 -0
  7. data/lib/rggen/default_register_map/bit_field/comment.rb +18 -0
  8. data/lib/rggen/default_register_map/bit_field/initial_value.rb +75 -0
  9. data/lib/rggen/default_register_map/bit_field/name.rb +37 -0
  10. data/lib/rggen/default_register_map/bit_field/reference.rb +142 -0
  11. data/lib/rggen/default_register_map/bit_field/type.rb +117 -0
  12. data/lib/rggen/default_register_map/bit_field/type/rc.rb +9 -0
  13. data/lib/rggen/default_register_map/bit_field/type/reserved.rb +8 -0
  14. data/lib/rggen/default_register_map/bit_field/type/ro.rb +8 -0
  15. data/lib/rggen/default_register_map/bit_field/type/rof.rb +9 -0
  16. data/lib/rggen/default_register_map/bit_field/type/rs.rb +8 -0
  17. data/lib/rggen/default_register_map/bit_field/type/rw.rb +9 -0
  18. data/lib/rggen/default_register_map/bit_field/type/rwc.rb +9 -0
  19. data/lib/rggen/default_register_map/bit_field/type/rwe_rwl.rb +10 -0
  20. data/lib/rggen/default_register_map/bit_field/type/w0c_w1c.rb +9 -0
  21. data/lib/rggen/default_register_map/bit_field/type/w0s_w1s.rb +8 -0
  22. data/lib/rggen/default_register_map/bit_field/type/w0trg_w1trg.rb +8 -0
  23. data/lib/rggen/default_register_map/bit_field/type/wo.rb +9 -0
  24. data/lib/rggen/default_register_map/global/address_width.rb +34 -0
  25. data/lib/rggen/default_register_map/global/bus_width.rb +35 -0
  26. data/lib/rggen/default_register_map/register/name.rb +36 -0
  27. data/lib/rggen/default_register_map/register/offset_address.rb +106 -0
  28. data/lib/rggen/default_register_map/register/size.rb +95 -0
  29. data/lib/rggen/default_register_map/register/type.rb +135 -0
  30. data/lib/rggen/default_register_map/register/type/external.rb +16 -0
  31. data/lib/rggen/default_register_map/register/type/indirect.rb +256 -0
  32. data/lib/rggen/default_register_map/register_block/byte_size.rb +61 -0
  33. data/lib/rggen/default_register_map/register_block/name.rb +38 -0
  34. data/lib/rggen/default_register_map/setup.rb +18 -0
  35. data/lib/rggen/default_register_map/version.rb +7 -0
  36. metadata +95 -0
@@ -0,0 +1,142 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_simple_feature(:bit_field, :reference) do
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+ register_map do
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+ property :reference, initial: -> { reference_bit_field }, verify: :all
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+ property :reference?, body: -> { use_reference? && !no_reference? }
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+ property :reference_width, forward_to: :required_width
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+ property :find_reference, forward_to: :find_reference_bit_field
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+
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+ input_pattern [
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+ /(#{variable_name})\.(#{variable_name})/,
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+ /(#{variable_name})/
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+ ]
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+
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+ build do |value|
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+ @input_reference =
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+ if pattern_matched?
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+ match_data[1..2].compact.join('.')
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+ else
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+ error "illegal input value for reference: #{value.inspect}"
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+ end
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+ end
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+
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+ verify(:component) do
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+ error_condition { require_reference? && no_reference? }
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+ message { 'no reference bit field is given' }
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+ end
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+
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+ verify(:component) do
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+ error_condition { reference? && @input_reference == bit_field.full_name }
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+ message { "self reference: #{@input_reference}" }
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+ end
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+
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+ verify(:all) do
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+ error_condition { reference? && !reference_bit_field }
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+ message { "no such bit field found: #{@input_reference}" }
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+ end
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+
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+ verify(:all) do
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+ error_condition do
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+ reference? && !register.array? && reference_bit_field.register.array?
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+ end
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+ message do
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+ 'bit field of array register is not allowed for ' \
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+ "reference bit field: #{@input_reference}"
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+ end
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+ end
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+
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+ verify(:all) do
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+ error_condition { reference? && !match_array_size? }
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+ message do
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+ 'array size is not matched: ' \
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+ "own #{register.array_size} " \
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+ "reference #{reference_bit_field.register.array_size}"
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+ end
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+ end
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+
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+ verify(:all) do
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+ error_condition do
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+ reference? && !bit_field.sequential? && reference_bit_field.sequential?
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+ end
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+ message do
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+ 'sequential bit field is not allowed for ' \
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+ "reference bit field: #{@input_reference}"
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+ end
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+ end
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+
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+ verify(:all) do
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+ error_condition { reference? && !match_sequence_size? }
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+ message do
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+ 'sequence size is not matched: ' \
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+ "own #{bit_field.sequence_size} " \
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+ "reference #{reference_bit_field.sequence_size}"
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+ end
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+ end
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+
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+ verify(:all) do
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+ error_condition { reference? && reference_bit_field.reserved? }
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+ message { "refer to reserved bit field: #{@input_reference}" }
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+ end
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+
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+ verify(:all) do
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+ error_condition { reference? && !match_width? }
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+ message do
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+ "#{required_width} bits reference bit field is required: " \
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+ "#{reference_bit_field.width} bit(s) width"
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+ end
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+ end
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+
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+ private
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+
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+ def settings
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+ @settings ||=
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+ (bit_field.settings && bit_field.settings[:reference]) || {}
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+ end
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+
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+ def use_reference?
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+ settings.fetch(:use, false)
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+ end
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+
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+ def require_reference?
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+ use_reference? && settings[:require]
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+ end
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+
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+ def no_reference?
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+ @input_reference.nil?
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+ end
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+
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+ def reference_bit_field
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+ (reference? || nil) &&
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+ (@reference_bit_field ||= lookup_reference)
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+ end
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+
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+ def find_reference_bit_field(bit_fields)
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+ (reference? || nil) &&
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+ bit_fields
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+ .find { |bit_field| bit_field.full_name == @input_reference }
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+ end
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+
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+ def lookup_reference
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+ find_reference_bit_field(register_block.bit_fields)
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+ end
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+
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+ def match_array_size?
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+ !(register.array? && reference_bit_field.register.array?) ||
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+ register.array_size == reference_bit_field.register.array_size
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+ end
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+
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+ def match_sequence_size?
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+ !(bit_field.sequential? && reference_bit_field.sequential?) ||
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+ bit_field.sequence_size == reference_bit_field.sequence_size
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+ end
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+
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+ def required_width
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+ settings[:width] || bit_field.width
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+ end
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+
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+ def match_width?
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+ reference_bit_field.width >= required_width
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+ end
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+ end
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+ end
@@ -0,0 +1,117 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_list_feature(:bit_field, :type) do
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+ register_map do
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+ base_feature do
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+ define_helpers do
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+ def read_write
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+ @readable = true
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+ @writable = true
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+ end
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+
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+ def read_only
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+ @readable = true
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+ @writable = false
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+ end
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+
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+ def write_only
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+ @readable = false
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+ @writable = true
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+ end
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+
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+ def reserved
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+ @readable = false
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+ @writable = false
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+ end
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+
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+ def readable?
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+ @readable.nil? || @readable
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+ end
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+
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+ def writable?
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+ @writable.nil? || @writable
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+ end
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+
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+ def read_only?
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+ readable? && !writable?
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+ end
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+
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+ def write_only?
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+ writable? && !readable?
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+ end
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+
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+ def reserved?
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+ !(readable? || writable?)
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+ end
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+
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+ def volatile
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+ @volatility = -> { true }
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+ end
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+
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+ def non_volatile
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+ @volatility = -> { false }
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+ end
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+
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+ def volatile?(&block)
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+ @volatility = block
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+ end
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+
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+ attr_reader :volatility
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+
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+ def settings
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+ @settings ||= {}
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+ end
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+
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+ def initial_value(**setting)
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+ settings[:initial_value] = setting
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+ end
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+
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+ def reference(**setting)
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+ settings[:reference] = setting
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+ end
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+ end
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+
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+ property :type
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+ property :settings, forward_to_helper: true
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+ property :readable?, forward_to_helper: true
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+ property :writable?, forward_to_helper: true
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+ property :read_only?, forward_to_helper: true
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+ property :write_only?, forward_to_helper: true
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+ property :reserved?, forward_to_helper: true
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+ property :volatile?, initial: -> { volatility }
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+
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+ build { |value| @type = value }
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+
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+ printable :type
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+
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+ private
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+
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+ def volatility
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+ helper.volatility.nil? || instance_exec(&helper.volatility)
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+ end
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+ end
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+
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+ default_feature do
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+ verify(:feature) do
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+ error_condition { !type }
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+ message { 'no bit field type is given' }
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+ end
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+
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+ verify(:feature) do
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+ error_condition { type }
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+ message { "unknown bit field type: #{type.inspect}" }
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+ end
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+ end
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+
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+ factory do
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+ convert_value do |value|
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+ types = target_features.keys
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+ types.find(&value.to_sym.method(:casecmp?)) || value
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+ end
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+
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+ def select_feature(cell)
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+ target_features[cell.value]
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+ end
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+ end
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+ end
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+ end
@@ -0,0 +1,9 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_list_item_feature(:bit_field, :type, :rc) do
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+ register_map do
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+ read_only
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+ reference use: true
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+ initial_value require: true
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+ end
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+ end
@@ -0,0 +1,8 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_list_item_feature(:bit_field, :type, :reserved) do
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+ register_map do
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+ reserved
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+ non_volatile
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+ end
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+ end
@@ -0,0 +1,8 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_list_item_feature(:bit_field, :type, :ro) do
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+ register_map do
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+ read_only
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+ reference use: true
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+ end
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+ end
@@ -0,0 +1,9 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_list_item_feature(:bit_field, :type, :rof) do
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+ register_map do
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+ read_only
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+ non_volatile
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+ initial_value require: true
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+ end
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+ end
@@ -0,0 +1,8 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_list_item_feature(:bit_field, :type, :rs) do
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+ register_map do
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+ read_only
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+ initial_value require: true
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+ end
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+ end
@@ -0,0 +1,9 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_list_item_feature(:bit_field, :type, :rw) do
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+ register_map do
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+ read_write
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+ non_volatile
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+ initial_value require: true
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+ end
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+ end
@@ -0,0 +1,9 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
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+ register_map do
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+ read_write
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+ initial_value require: true
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+ reference use: true, width: 1
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+ end
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+ end
@@ -0,0 +1,10 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
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+ register_map do
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+ read_write
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+ volatile? { !bit_field.reference? }
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+ initial_value require: true
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+ reference use: true, width: 1
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+ end
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+ end
@@ -0,0 +1,9 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_list_item_feature(:bit_field, :type, [:w0c, :w1c]) do
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+ register_map do
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+ read_write
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+ reference use: true
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+ initial_value require: true
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+ end
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+ end
@@ -0,0 +1,8 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_list_item_feature(:bit_field, :type, [:w0s, :w1s]) do
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+ register_map do
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+ read_write
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+ initial_value require: true
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+ end
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+ end
@@ -0,0 +1,8 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
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+ register_map do
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+ write_only
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+ non_volatile
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+ end
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+ end
@@ -0,0 +1,9 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_list_item_feature(:bit_field, :type, :wo) do
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+ register_map do
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+ write_only
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+ non_volatile
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+ initial_value require: true
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+ end
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+ end
@@ -0,0 +1,34 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_simple_feature(:global, :address_width) do
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+ configuration do
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+ property :address_width, default: 32
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+
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+ build do |value|
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+ @address_width =
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+ begin
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+ Integer(value)
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+ rescue ArgumentError, TypeError
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+ error "cannot convert #{value.inspect} into address width"
13
+ end
14
+ end
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+
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+ verify(:component) do
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+ error_condition { address_width < min_address_width }
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+ message do
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+ 'input address width is less than minimum address width: ' \
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+ "address width #{address_width} " \
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+ "minimum address width #{min_address_width}"
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+ end
23
+ end
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+
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+ printable :address_width
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+
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+ private
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+
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+ def min_address_width
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+ byte_width = configuration.byte_width
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+ byte_width == 1 ? 1 : (byte_width - 1).bit_length
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+ end
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+ end
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+ end
@@ -0,0 +1,35 @@
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+ # frozen_string_literal: true
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+
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+ RgGen.define_simple_feature(:global, :bus_width) do
4
+ configuration do
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+ property :bus_width, default: 32
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+ property :byte_width, initial: -> { bus_width / 8 }
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+
8
+ build do |value|
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+ @bus_width =
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+ begin
11
+ Integer(value)
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+ rescue ArgumentError, TypeError
13
+ error "cannot convert #{value.inspect} into bus width"
14
+ end
15
+ end
16
+
17
+ verify(:feature) do
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+ error_condition { bus_width < 8 }
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+ message { "input bus width is less than 8: #{bus_width}" }
20
+ end
21
+
22
+ verify(:feature) do
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+ error_condition { !power_of_2?(bus_width) }
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+ message { "input bus width is not power of 2: #{bus_width}" }
25
+ end
26
+
27
+ printable :bus_width
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+
29
+ private
30
+
31
+ def power_of_2?(value)
32
+ value.positive? && (value & value.pred).zero?
33
+ end
34
+ end
35
+ end