patento 0.2.0

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Files changed (26) hide show
  1. data/.document +5 -0
  2. data/.rspec +1 -0
  3. data/Gemfile +18 -0
  4. data/Gemfile.lock +54 -0
  5. data/Guardfile +9 -0
  6. data/LICENSE.txt +20 -0
  7. data/README.mdown +78 -0
  8. data/Rakefile +49 -0
  9. data/VERSION +1 -0
  10. data/lib/patento.rb +30 -0
  11. data/lib/patento/claim.rb +93 -0
  12. data/lib/patento/document.rb +95 -0
  13. data/lib/patento/patent.rb +21 -0
  14. data/lib/patento/publication.rb +7 -0
  15. data/patento.gemspec +79 -0
  16. data/spec/claim_spec.rb +20 -0
  17. data/spec/data/US20100268739.html +52 -0
  18. data/spec/data/US6000000.html +52 -0
  19. data/spec/data/US6000015.html +52 -0
  20. data/spec/data/US7114060.html +52 -0
  21. data/spec/data/US7130991.html +52 -0
  22. data/spec/data/US7143273.html +52 -0
  23. data/spec/patent_spec.rb +169 -0
  24. data/spec/publication_spec.rb +21 -0
  25. data/spec/spec_helper.rb +13 -0
  26. metadata +143 -0
data/lib/patento/patent.rb ADDED
@@ -0,0 +1,21 @@
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+ module Patento
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+
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+ class Patent < Document
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+
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+ def issue_date
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+ @issue_date ||= parse_date(:issue)
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+ end
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+
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+ def intl_classification
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+ # Wow this was a pain
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+ @intl_classification ||= @html.css('#summarytable div.patent_bibdata').children[-7].text.match(/([A-Z0-9]{1,}\s[A-Z0-9]{1,})/)[1]
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+ end
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+
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+ def backward_citations
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+ @backward_citations ||= parse_citations(:backward)
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+ end
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+
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+ end
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+
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+
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+ end
data/lib/patento/publication.rb ADDED
@@ -0,0 +1,7 @@
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+ module Patento
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+
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+ class Publication < Document
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+
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+ end
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+
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+ end
data/patento.gemspec ADDED
@@ -0,0 +1,79 @@
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+ # Generated by jeweler
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+ # DO NOT EDIT THIS FILE DIRECTLY
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+ # Instead, edit Jeweler::Tasks in Rakefile, and run 'rake gemspec'
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+ # -*- encoding: utf-8 -*-
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+
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+ Gem::Specification.new do |s|
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+ s.name = "patento"
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+ s.version = "0.2.0"
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+
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+ s.required_rubygems_version = Gem::Requirement.new(">= 0") if s.respond_to? :required_rubygems_version=
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+ s.authors = ["George Zalepa"]
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+ s.date = "2012-07-12"
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+ s.description = "Patento is a simple gem for scraping Google Patents and formatting the visible data into objects and hashes. See the README for more details"
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+ s.email = "george.zalepa@gmail.com"
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+ s.extra_rdoc_files = [
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+ "LICENSE.txt",
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+ "README.mdown"
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+ ]
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+ s.files = [
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+ ".document",
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+ ".rspec",
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+ "Gemfile",
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+ "Gemfile.lock",
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+ "Guardfile",
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+ "LICENSE.txt",
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+ "README.mdown",
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+ "Rakefile",
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+ "VERSION",
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+ "lib/patento.rb",
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+ "lib/patento/claim.rb",
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+ "lib/patento/document.rb",
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+ "lib/patento/patent.rb",
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+ "lib/patento/publication.rb",
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+ "patento.gemspec",
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+ "spec/claim_spec.rb",
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+ "spec/data/US20100268739.html",
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+ "spec/data/US6000000.html",
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+ "spec/data/US6000015.html",
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+ "spec/data/US7114060.html",
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+ "spec/data/US7130991.html",
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+ "spec/data/US7143273.html",
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+ "spec/patent_spec.rb",
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+ "spec/publication_spec.rb",
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+ "spec/spec_helper.rb"
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+ ]
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+ s.homepage = "http://github.com/aosik/patento"
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+ s.licenses = ["MIT"]
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+ s.require_paths = ["lib"]
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+ s.rubygems_version = "1.8.10"
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+ s.summary = "Patento is a simple gem for scraping Google Patents and formatting the visible data into objects and hashes."
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+
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+ if s.respond_to? :specification_version then
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+ s.specification_version = 3
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+
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+ if Gem::Version.new(Gem::VERSION) >= Gem::Version.new('1.2.0') then
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+ s.add_runtime_dependency(%q<nokogiri>, [">= 0"])
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+ s.add_development_dependency(%q<rspec>, [">= 0"])
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+ s.add_development_dependency(%q<rdoc>, [">= 0"])
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+ s.add_development_dependency(%q<bundler>, [">= 0"])
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+ s.add_development_dependency(%q<jeweler>, [">= 0"])
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+ s.add_development_dependency(%q<rspec>, [">= 0"])
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+ else
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+ s.add_dependency(%q<nokogiri>, [">= 0"])
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+ s.add_dependency(%q<rspec>, [">= 0"])
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+ s.add_dependency(%q<rdoc>, [">= 0"])
66
+ s.add_dependency(%q<bundler>, [">= 0"])
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+ s.add_dependency(%q<jeweler>, [">= 0"])
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+ s.add_dependency(%q<rspec>, [">= 0"])
69
+ end
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+ else
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+ s.add_dependency(%q<nokogiri>, [">= 0"])
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+ s.add_dependency(%q<rspec>, [">= 0"])
73
+ s.add_dependency(%q<rdoc>, [">= 0"])
74
+ s.add_dependency(%q<bundler>, [">= 0"])
75
+ s.add_dependency(%q<jeweler>, [">= 0"])
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+ s.add_dependency(%q<rspec>, [">= 0"])
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+ end
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+ end
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+
data/spec/claim_spec.rb ADDED
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+ require File.expand_path(File.dirname(__FILE__) + '/spec_helper')
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+
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+ describe Claim do
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+ describe "attributes" do
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+ it { should respond_to :number }
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+ it { should respond_to :type }
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+ it { should respond_to :preamble }
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+ it { should respond_to :body }
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+ end
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+
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+ describe "extracting a claim set" do
12
+ let(:claims) { Claim.extract_all(6000015, local_path: "#{$LOAD_PATH[0]}/data/US6000015.html")}
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+ subject { claims }
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+
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+ it { should have(7).items}
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+
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+ end
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+
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+ end
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+
data/spec/data/US20100268739.html ADDED
@@ -0,0 +1,52 @@
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+ <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN""http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd"><html><head><title>Patent US20100268739 - SYSTEMS AND METHODS FOR AUTOMATICALLY DETECTING AND REMOVING REDIRECTED ... - Google Patents</title><script>(function(){var a=function(c){this.t={};this.tick=function(c,i,b){b=void 0!=b?b:(new Date).getTime();this.t[c]=[b,i]};this.tick("start",null,c)},d=new a;window.jstiming={Timer:a,load:d};if(window.performance&&window.performance.timing){var e=window.performance.timing,f=window.jstiming.load,g=e.navigationStart,h=e.responseStart;0<g&&h>=g&&(f.tick("_wtsrt",void 0,g),f.tick("wtsrt_","_wtsrt",h))}
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+ </script><link rel="stylesheet" href="/patents/css/_b9ee852b3231a450c67d122471b67ac7/kl_patents_bundle.css" type="text/css" /><script type="text/javascript"src="/books/atb_b9ee852b3231a450c67d122471b67ac7.js"></script><script type="text/javascript">_OC_addMsgs({19053:"Read this application", 22002:"eBook - %1$s", 22160:"Available on: %1$s", 18108:"You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.", 26365:"Pages %1$s to %2$s are not shown in this preview.", 18464:"Add to my library", 20198:"Web", 18299:"%1$d pages", 22223:"Sample print book", 21845:"This eBook includes scanned pages, so pages appear as they would in a printed book.", 18244:"Learn more", 21861:"Scroll right", 21838:"This Google eBook includes flowing text so you can adjust the font to read comfortably on the small screen of a smartphone.", 18768:"Selection text", 21994:"Available on: \x3cb\x3e%1$s\x3c/b\x3e", 19144:"No preview", 22001:"eBook - FREE", 21990:"Please install the Google Books Chrome application to enable reading offline.", 22161:"Help with pre-orders", 18242:"Loading...", 22226:"Read the book for FREE", 18279:"Snippet view", 19118:"Google eBook", 22084:"Good for:", 21697:"View sample", 18138:"Back Cover", 21713:"Delete forever", 18802:"PDF", 21862:"Scroll left", 21936:"eReader", 21809:"Web", 18955:"Private bookshelf", 19251:"Preview", 21919:"Make available offline", 22085:"Features:", 21832:"This eBook, like all Google eBooks, is formatted to be readable on the web.", 22234:"This book has not completely downloaded for reading offline.", 22036:"Pre-ordered", 18295:"Download", 18042:"Buy this book", 18287:"more \x26raquo;", 18005:"Search in this patent", 22102:"Cancelled - by customer request", 19217:"In \x3ca href\x3d\x22%1$s\x22\x3eMy eBooks\x3c/a\x3e", 22080:"Cancelled", 18764:"Purchased", 21833:"This eBook, like all Google eBooks, is formatted to be readable on tablet devices like Android tablets and the iPad.", 21909:"This book is not available for reading offline.", 26364:"Flowing text", 22011:"Pre-order eBook - %1$s", 18140:"Contents", 21843:"This eBook includes flowing text, so you can adjust the font size and style to read comfortably on any device.", 22087:"Read the first chapter - FREE!", 22249:"Learn more about books on Google Play", 18954:"Public bookshelf", 21841:"This eBook may be hard to read on smartphones like Android and iPhone / iPod touch.", 18891:"Translate", 21835:"This Google eBook includes flowing text, so you can adjust the font to read comfortably on an eReader.", 18632:"Paste link in \x3cb\x3eemail\x3c/b\x3e or \x3cb\x3eIM\x3c/b\x3e", 22206:"Gift Received", 22144:"Added to {$count} shelves", 22000:"preview it", 19253:"Preview page scans", 21663:"Scanned pages", 18849:"No preview available for this page.", 21808:"Help with devices \x26 formats", 22221:"There was an error downloading this volume.", 22170:"The format of this book is currently unknown. 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Please remove this book from other readers, wait a few minutes, and try again.", 22192:"This book is not available offline."});</script><script type="text/javascript">function googleTranslateElementInit() {new google.translate.TranslateElement({pageLanguage: 'en',gaTrack: true,gaId: "UA-27188110-1"});}</script><script type="text/javascript"src="//translate.google.com/translate_a/element.js?cb=googleTranslateElementInit"></script><link rel="canonical" href="http://www.google.com/patents/US20100268739"/><meta property="og:url" content="http://www.google.com/patents/US20100268739"/><meta name="title" content="Patent US20100268739 - SYSTEMS AND METHODS FOR AUTOMATICALLY DETECTING AND REMOVING REDIRECTED UNIFORM RESOURCE LOCATORS"/><meta name="description" content="The present invention is directed towards systems and methods for managing shortened URLs. The method according to one embodiment of the present invention comprises receiving a request for a shortened URL from a submitting user, said request comprising a first URL. The method then generates a unique shortened URL for said first URL and provides said shortened URL to the submitting user. After a period of time, the method receives a request for the shortened URL from a requesting user. The method then deletes the shortened URL and redirects the requesting user to the first URL."/><meta property="og:title" content="Patent US20100268739 - SYSTEMS AND METHODS FOR AUTOMATICALLY DETECTING AND REMOVING REDIRECTED UNIFORM RESOURCE LOCATORS"/><meta property="og:type" content="book"/><meta property="og:site_name" content="Google Books"/><meta property="og:image" content="http://www.google.com/patents?id=Rj7YAAAAEBAJ&amp;printsec=frontcover&amp;img=1&amp;zoom=1"/><link rel="image_src" href="http://www.google.com/patents?id=Rj7YAAAAEBAJ&amp;printsec=frontcover&amp;img=1&amp;zoom=1"/><script>(function(){try{var e=!0,h=!1;var aa=function(a,b,c,d){d=d||{};d._sn=["cfg",b,c].join(".");window.gbar.logger.ml(a,d)};var ba={I:1,K:2,ca:3,C:4,W:5,P:6,v:7,w:8,ga:9,V:10,O:11,A:12,U:13,z:14,S:15,R:16,ea:17,F:18,Q:19,fa:20,da:21,D:22,J:23,ia:24,ja:25,ha:26,G:27,g:28,B:29,u:30,ba:31,Y:32,Z:33,M:34,N:35,aa:36,$:37,X:38,H:39,T:40,L:500};var j=window.gbar=window.gbar||{},m=window.gbar.i=window.gbar.i||{},n;function _tvn(a,b){var c=parseInt(a,10);return isNaN(c)?b:c}function _tvf(a,b){var c=parseFloat(a);return isNaN(c)?b:c}function _tvv(a){return!!a}function p(a,b,c){(c||j)[a]=b}j.bv={n:_tvn("2",0),r:"",f:".5.36.40.",m:_tvn("2",1)};var q=function(a){return function(){return j.bv.m==a}},ca=q(1),da=q(2);p("sb",ca);p("kn",da);m.a=_tvv;m.b=_tvf;m.c=_tvn;
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id="right-toolbar-buttons"></div></div><div id="books-microdata" itemscope=""itemtype="http://schema.org/Book"itemid="http://www.google.com/patents/US20100268739" style="display:none"><span itemprop="description">The present invention is directed towards systems and methods for managing shortened URLs. The method according to one embodiment of the present invention comprises receiving a request for a shortened URL from a submitting user, said request comprising a first URL. The method then generates a unique...</span><span itemprop="url">http://www.google.com/patents/US20100268739?utm_source=gb-gplus-share</span><span class="main-title" itemprop="name">Patent US20100268739 - SYSTEMS AND METHODS FOR AUTOMATICALLY DETECTING AND REMOVING REDIRECTED UNIFORM RESOURCE LOCATORS</span><img itemprop="image" src="http://www.google.com/patents?id=Rj7YAAAAEBAJ&amp;printsec=frontcover&amp;img=1&amp;zoom=1"alt="Patent US20100268739 - SYSTEMS AND METHODS FOR AUTOMATICALLY DETECTING AND REMOVING REDIRECTED UNIFORM RESOURCE LOCATORS" title="Patent US20100268739 - SYSTEMS AND METHODS FOR AUTOMATICALLY DETECTING AND REMOVING REDIRECTED UNIFORM RESOURCE LOCATORS"></div><table id="viewport_table" cellpadding="0" style="clear:both" cellspacing="0"><tr><td id="menu_td" class="menu_td"><div id=menu_container><div class=menu id=menu><div class="menu_content" style="margin-bottom:6px"><div id="volume-info-sidebar"><span class="gb-survey-link"></span><h1 class="gb-volume-title" dir=ltr>SYSTEMS AND METHODS FOR AUTOMATICALLY DETECTING AND REMOVING REDIRECTED ...</h1>&nbsp;<span class="addmd">George David Zalepa</span></div><div style="margin-bottom:4px"><div class=sidebarnav><div class=sidebarcover><a href="http://www.google.com/patents?id=Rj7YAAAAEBAJ&printsec=abstract&zoom=4" ><img src="http://bks9.books.google.com/patents?id=Rj7YAAAAEBAJ&printsec=abstract&img=1&zoom=1&sig=ACfU3U0i0e2GN1WwwT3nIiL-mhPKtYbdkA" alt="Abstract" title="Abstract" width=102 border=1 id=summary-frontcover ></a></div><span class=nolink>&rsaquo;&nbsp;Overview</span><br><a href="/patents/US20100268739?printsec=abstract&dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">Abstract</a><br><a href="/patents/US20100268739?printsec=drawing&dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">Drawings</a><br><a href="/patents/US20100268739?printsec=description&dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">Description</a><br><a href="/patents/US20100268739?printsec=claims&dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">Claims</a><br><span id="gb-atb-patents-plusone-container"></span></div></div></div><div style="clear:both"></div><div style="margin-left:10px"><form action=/patents id=search_form style="margin:0px;padding:0px;" method=get> <input type=hidden name=ei value="EQj-T5-UOYaI0QGdrvHkBg"><input type=hidden name=id value="Rj7YAAAAEBAJ"><input type=hidden name=dq value="george david zalepa"><table cellpadding=0 cellspacing=0 class="swv-table"><tr><td width="100%" class="swv-td-search"><span><input id=search_form_input type=text maxlength=1024 class="text_flat swv-input-search" name=q value="" title="Go" accesskey=i></span></td><td class="swv-td-space">&nbsp;&nbsp;</td><td><input type=submit value="Go"></td></tr></table><script type="text/javascript">if (window['_OC_autoDir']) {_OC_autoDir('search_form_input');}</script></form></div><div id="menu_scroll"><div id=metadata_content class=menu_content><div id=metadata_v><div class=patent_bibdata><p><b>Application number</b>: 12/427,249<br><b>Publication number</b>: <nobr>US 2010/0268739 A1</nobr><br><b>Filing date</b>: Apr 21, 2009<br></p></div></div></div></div></div></div></td><td id="viewport_td"><div class=vertical_module_list_row><div id=overview class=about_content><div id=overview_v><table id="summarytable" cellpadding="0" cellspacing="0" border="0" width="100%"><tr><td valign=top><p class="patent_abstract_text">The present invention is directed towards systems and methods for managing shortened URLs. The method according to one embodiment of the present invention comprises receiving a request for a shortened URL from a submitting user, said request comprising a first URL. The method then generates a unique shortened URL for said first URL and provides said shortened URL to the submitting user. After a period of time, the method receives a request for the shortened URL from a requesting user. The method then deletes the shortened URL and redirects the requesting user to the first URL.</p><div class="patent_bibdata"><b>Inventor</b>:&nbsp;<a href="http://www.google.com/search?tbo=p&amp;tbm=pts&amp;hl=en&amp;q=ininventor:%22George+David+Zalepa%22">George David Zalepa</a><br><b>Current U.S. Classification</b>:&nbsp;<a href="http://www.google.com/url?id=Rj7YAAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc707/defs707.htm&amp;usg=AFQjCNE7Q7Bg2eD2wcE_fXEcdOe7Yesevw#C707S782000">707/782</a>; <a href="http://www.google.com/url?id=Rj7YAAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc707/defs707.htm&amp;usg=AFQjCNE7Q7Bg2eD2wcE_fXEcdOe7Yesevw#C707SE17002">707/E17.002</a>; <a href="http://www.google.com/url?id=Rj7YAAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc707/defs707.htm&amp;usg=AFQjCNE7Q7Bg2eD2wcE_fXEcdOe7Yesevw#C707SE17005">707/E17.005</a><br><br><a href="http://www.google.com/url?id=Rj7YAAAAEBAJ&q=http://appft1.uspto.gov/netacgi/nph-Parser%3FSect1%3DPTO1%26Sect2%3DHITOFF%26d%3DPG01%26p%3D1%26u%3D/netahtml/PTO/srchnum.html%26r%3D1%26f%3DG%26l%3D50%26s1%3D20100268739.PGNR.&usg=AFQjCNG5fVgzcaXjF5kOm4c6rTV-5NVr_A">View patent at USPTO</a><br><a href="http://www.google.com/url?id=Rj7YAAAAEBAJ&q=http://assignments.uspto.gov/assignments/q%3Fdb%3Dpat%26pub%3D20100268739&usg=AFQjCNEl-y9RNGtmYpf2FvMedTIQIz-Zjg">Search USPTO Assignment Database</a><br><a href="http://www.google.com/url?id=Rj7YAAAAEBAJ&q=http://commondatastorage.googleapis.com/uspto-pair/applications/12427249.zip&usg=AFQjCNFsw4bYLESKWcgWEmb9GoEDDovrbQ">Download USPTO Public PAIR data</a><br></div></table></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="patent_claims_anchor"></a>Claims</h3><div id=patent_claims class=about_content><div id=patent_claims_v><p>1. A method for managing shortened URLs, the method comprising:<p><dl><dd style="margin-left:1em;">receiving a request for a shortened URL from a submitting user, said request comprising a first URL;</dd></dl><p><dl><dd style="margin-left:1em;">generating a unique shortened URL for said first URL;</dd></dl><p><dl><dd style="margin-left:1em;">providing said shortened URL to the submitting user;</dd></dl><p><dl><dd style="margin-left:1em;">receiving a request for the shortened URL from a requesting user;</dd><dd style="margin-left:1em;">deleting the shortened URL; and</dd><dd style="margin-left:1em;">redirecting the requesting user to the first URL.</dd></dl><p>2. The method of claim 1 further comprising determining if the requested shortened URL exists.<p>3. The method of claim 2 wherein deleting the shortened URL occurs immediately after determining that the requested shortened URL exists.<p>4. The method of claim 1 wherein deleting the shortened URL comprises removing the shortened URL from a database.<p>5. The method of claim 1 wherein deleting the shortened URL comprises marking the shortened URL as deleted.<p>6. The method of claim 1 wherein deleting the shortened URL comprises determining an expiration period and deleting the shortened URL after the expiration of the expiration period.<p>7. The method of claim 1 wherein receiving a request for a shortened URL further comprises receiving a communication identifier associated with the requesting user.<p>8. The method of claim 7, further comprising alerting the user upon deleting the shortened URL via the communication identifier.<p>9. The method of claim 8 wherein the communication identifier comprises one of an e-mail address, phone number or instant messenger identifier.<p>10. A system for managing shortened URLs, the system comprising:<p><dl><dd style="margin-left:1em;">a plurality of client devices coupled to a network, said client devices operative to transmit a request for a shortened URL from a submitting user, said request comprising a first URL;</dd></dl><p><dl><dd style="margin-left:1em;">a URL database operative to store shortened URLs, said URL database operative to store at least a URL and a URL identifier;</dd></dl><p><dl><dd style="margin-left:1em;">a content server operative to:</dd><dd style="margin-left:1em;"><dl><dd style="margin-left:1em;">generate a unique shortened URL for said first URL;</dd><dd style="margin-left:1em;">provide said shortened URL to the submitting user;</dd><dd style="margin-left:1em;">receive a request for the shortened URL from a requesting user;</dd><dd style="margin-left:1em;">delete the shortened URL; and</dd><dd style="margin-left:1em;">redirect the requesting user to the first URL</dd></dl></dd></dl><p>11. The system of claim 10 wherein the content server is further operative to determine if the requested shortened URL exists.<p>12. The system of claim 11 wherein the content server is further operative to delete the shortened URL immediately after determining that the requested shortened URL exists.<p>13. The system of claim 10 wherein the content server is further operative to delete the shortened URL by removing the shortened URL from a database.<p>14. The system of claim 10 wherein the content server is further operative to delete the shortened URL by marking the shortened URL as deleted.<p>15. The system of claim 10 wherein the content server is further operative to delete the shortened URL by determining an expiration period and deleting the shortened URL after the expiration of the expiration period.<p>16. The system of claim 10 wherein the client devices are further operative to transmit a communication identifier associated with the requesting user.<p>17. The system of claim 16, wherein the content server is further operative to alert the user upon deleting the shortened URL via the communication identifier.<p>18. The system of claim 17 wherein the communication identifier comprises one of an e-mail address, phone number or instant messenger identifier.</div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="selected_pages_anchor"></a>Drawings</h3><div id=selected_pages class=about_content><div id=selected_pages_v><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=Rj7YAAAAEBAJ&pg=PA2&dq=george+david+zalepa&source=gbs_selected_pages&cad=2" ><img src="http://bks9.books.google.com/patents?id=Rj7YAAAAEBAJ&amp;pg=PA2&amp;img=1&amp;zoom=1&amp;sig=ACfU3U1l3w-n6-dJgj_T-kGSdi12lRpkOA" alt="Drawings" title="Drawings" height="160" border="1"></a><br/><a class="primary" href="http://www.google.com/patents?id=Rj7YAAAAEBAJ&pg=PA2&dq=george+david+zalepa&source=gbs_selected_pages&cad=2" >Drawings</a></div><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=Rj7YAAAAEBAJ&pg=PA3&dq=george+david+zalepa&source=gbs_selected_pages&cad=2" ><img src="http://bks9.books.google.com/patents?id=Rj7YAAAAEBAJ&amp;pg=PA3&amp;img=1&amp;zoom=1&amp;sig=ACfU3U1tRsRbKRWlFEfB6XV_mKwVrnjFyw" alt="Drawings" title="Drawings" height="160" border="1"></a><br/><a class="primary" href="http://www.google.com/patents?id=Rj7YAAAAEBAJ&pg=PA3&dq=george+david+zalepa&source=gbs_selected_pages&cad=2" >Drawings</a></div><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=Rj7YAAAAEBAJ&pg=PA4&dq=george+david+zalepa&source=gbs_selected_pages&cad=2" ><img src="http://bks9.books.google.com/patents?id=Rj7YAAAAEBAJ&amp;pg=PA4&amp;img=1&amp;zoom=1&amp;sig=ACfU3U2O6XPLAvgSG9iX4nKKU-V5upi-bA" alt="Drawings" title="Drawings" height="160" border="1"></a><br/><a class="primary" href="http://www.google.com/patents?id=Rj7YAAAAEBAJ&pg=PA4&dq=george+david+zalepa&source=gbs_selected_pages&cad=2" >Drawings</a></div><div style="clear:both;"></div></div></div></div></td></tr></table><script type="text/javascript">_OC_addFlags({LockSrc:"/books/javascript/lock_b9ee852b3231a450c67d122471b67ac7.js", IsWebstoreDisplayCaseEnabled:1, IsObfuscationEnabled:1, IsBrowsingHistoryEnabled:1, IsGeoLayerEnabled:0, IsGiftingEnabled:0, IsOfflineBubbleEnabled:1, IsReaderEnabledForPlayRequests:1, IsUnifiedHovercardEnabled:1, IsFutureOnSaleVolumesEnabled:1, IsBooksUnifiedLeftNavEnabled:1, IsZipitFolderCollectionEnabled:1, IsRatingsOnBookcardsEnabled:1, IsEmbeddedMediaEnabled:1, IsImageModeAnnotationsEnabled:0, IsMyLibraryGooglePlusEnabled:1, IsBookcardListPriceSmall:0, IsBooksShareButtonEnabled:0, IsPreOrdersEnabled:1, IsDisabledRandomBookshelves:0, WebstoreDisplayCasePosition:3});_OC_addMsgs();_OC_Run({"enable_p13n":false,"add_vol_to_collection_base_url":"http://www.google.com/patents?op=add\u0026sig=ACfU3U2NR9gLbaUjBBmf3hRNvlVxNGjPdw\u0026id=Rj7YAAAAEBAJ","remove_vol_from_collection_base_url":"http://www.google.com/patents?op=remove\u0026sig=ACfU3U1ASqT0009jj4tQlE1VzGgKmai3sA\u0026id=Rj7YAAAAEBAJ","logged_in":true,"p13n_save_user_settings_url":"http://www.google.com/patents?op=edit_user_settings\u0026sig=ACfU3U1csLrPRWWF41pcqYdLt6glRm7l_A","is_cobrand":false,"is_play_enabled":true}, {"volume_id":"","is_ebook":true,"volumeresult":{"has_flowing_text":false,"has_scanned_text":true,"can_download_pdf":false,"can_download_epub":false,"is_pdf_drm_enabled":false,"is_epub_drm_enabled":false,"download_pdf_url":"http://www.google.com/patents/download/12_427_249_SYSTEMS_AND_METHODS_FOR_AUTOM.pdf?id=Rj7YAAAAEBAJ\u0026output=pdf\u0026sig=ACfU3U3OO_brlK4KUZ8_y5gUQUmORkwpog"},"sample_url":"http://www.google.com/patents/reader?id=Rj7YAAAAEBAJ\u0026printsec=frontcover\u0026output=reader\u0026source=gbs_atb_hover","is_browsable":true,"is_public_domain":true}, {"uid":"112034765180046512987"});</script><div id="footer_table" style="font-size:83%;text-align:center;position:relative;top:20px;height:4.5em;margin-top:2em"><div style="margin-bottom:8px"><a href=http://www.google.com/><nobr>Google&nbsp;Home</nobr></a> - <a href=http://www.google.com/googlebooks/uspto.html><nobr>USPTO Bulk Downloads</nobr></a> - <a href=https://www.google.com/intl/en/privacy/><nobr>Privacy Policy</nobr></a> - <a href=https://www.google.com/accounts/TOS><nobr>Terms of Service</nobr></a> - <a href=/googlepatents/about.html><nobr>About Google Patents</nobr></a> - <a href=/googlepatents/help.html><nobr><nobr>Google Patents Help</nobr></nobr></a> - <a href="http://www.google.com/tools/feedback/intl/en/error.html" onclick="try{_OC_startFeedback({productId: '72792',locale: 'en'});return false;}catch(e){}"><nobr>Send Feedback</nobr></a></div><span >&copy;2012 Google</span></div> <script type="text/javascript">var gaJsHost = (("https:" == document.location.protocol) ? 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id="appbar-view-ebook-sample-link" href=""></a><a id="appbar-patents-prior-art-finder-link" href=""></a><a id="appbar-read-patent-link" href="/patents/US6000000?printsec=abstract"></a><a id="appbar-download-pdf-link" href="/patents/US6000000.pdf"></a></div><div class="kd-buttonbar right" id="right-toolbar-buttons"></div></div><div id="books-microdata" itemscope=""itemtype="http://schema.org/Book"itemid="http://www.google.com/patents/US6000000" style="display:none"><span itemprop="description">Many users of handheld computer systems maintain databases on the handheld computer systems. To share the information, it is desirable to have a simple method of sharing the information with personal computer systems. An easy to use extendible file synchronization system is introduced for sharing information...</span><span itemprop="url">http://www.google.com/patents/US6000000?utm_source=gb-gplus-share</span><span class="main-title" itemprop="name">Patent US6000000 - Extendible method and apparatus for synchronizing multiple files on two different computer systems</span><img itemprop="image" src="http://www.google.com/patents?id=6ugYAAAAEBAJ&amp;printsec=frontcover&amp;img=1&amp;zoom=1"alt="Patent US6000000 - Extendible method and apparatus for synchronizing multiple files on two different computer systems" title="Patent US6000000 - Extendible method and apparatus for synchronizing multiple files on two different computer systems"></div><table id="viewport_table" cellpadding="0" style="clear:both" cellspacing="0"><tr><td id="menu_td" class="menu_td"><div id=menu_container><div class=menu id=menu><div class="menu_content" style="margin-bottom:6px"><div id="volume-info-sidebar"><span class="gb-survey-link"></span><h1 class="gb-volume-title" dir=ltr>Extendible method and apparatus for synchronizing multiple files on two ...</h1>&nbsp;<span class="addmd">Jeffrey C. Hawkins et al</span></div><div style="margin-bottom:4px"><div class=sidebarnav><div class=sidebarcover><a href="http://www.google.com/patents?id=6ugYAAAAEBAJ&printsec=abstract&zoom=4" ><img src="http://bks2.books.google.com/patents?id=6ugYAAAAEBAJ&printsec=abstract&img=1&zoom=1&sig=ACfU3U1UX9c3hfc8ytu9S7LcGJultO68EA" alt="Abstract" title="Abstract" width=102 border=1 id=summary-frontcover ></a></div><span class=nolink>&rsaquo;&nbsp;Overview</span><br><a href="/patents/US6000000?printsec=abstract">Abstract</a><br><a href="/patents/US6000000?printsec=drawing">Drawings</a><br><a href="/patents/US6000000?printsec=description">Description</a><br><a href="/patents/US6000000?printsec=claims">Claims</a><br><span id="gb-atb-patents-plusone-container"></span></div></div></div><div style="clear:both"></div><div style="margin-left:10px"><form action=/patents id=search_form style="margin:0px;padding:0px;" method=get> <input type=hidden name=id value="6ugYAAAAEBAJ"><table cellpadding=0 cellspacing=0 class="swv-table"><tr><td width="100%" class="swv-td-search"><span><input id=search_form_input type=text maxlength=1024 class="text_flat swv-input-search" name=q value="" title="Go" accesskey=i></span></td><td class="swv-td-space">&nbsp;&nbsp;</td><td><input type=submit value="Go"></td></tr></table><script type="text/javascript">if (window['_OC_autoDir']) {_OC_autoDir('search_form_input');}</script></form></div><div id="menu_scroll"><div id=metadata_content class=menu_content><div id=metadata_v><div class=patent_bibdata><p><b>Patent number</b>: 6000000<br><b>Filing date</b>: May 4, 1998<br><b>Issue date</b>: Dec 7, 1999<br></p></div></div></div></div></div></div></td><td id="viewport_td"><div class=vertical_module_list_row><div id=overview class=about_content><div id=overview_v><table id="summarytable" cellpadding="0" cellspacing="0" border="0" width="100%"><tr><td valign=top><p class="patent_abstract_text">Many users of handheld computer systems maintain databases on the handheld computer systems. To share the information, it is desirable to have a simple method of sharing the information with personal computer systems. An easy to use extendible file synchronization system is introduced for sharing information between a handheld computer system and a personal computer system. The synchronization system is activated by a single button press. The synchronization system proceeds to synchronize data for several different applications that run on the handheld computer system and the personal computer system. If the user gets a new application for the handheld computer system and the personal computer system, then a new library of code is added for synchronizing the databases associate with the new application. The synchronization system automatically recognizes the new library of code and uses it during the next synchronization.</p><div class="patent_bibdata"><b>Inventors</b>:&nbsp;<a href="http://www.google.com/search?tbo=p&amp;tbm=pts&amp;hl=en&amp;q=ininventor:%22Jeffrey+C.+Hawkins%22">Jeffrey C. Hawkins</a>, <a href="http://www.google.com/search?tbo=p&amp;tbm=pts&amp;hl=en&amp;q=ininventor:%22Michael+Albanese%22">Michael Albanese</a><br><b>Original Assignee</b>:&nbsp;<a href="http://www.google.com/search?tbo=p&amp;tbm=pts&amp;hl=en&amp;q=inassignee:%223Com+Corporation%22">3Com Corporation</a><br><b>Current U.S. Classification</b>:&nbsp;<a href="http://www.google.com/url?id=6ugYAAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc707/defs707.htm&amp;usg=AFQjCNE7Q7Bg2eD2wcE_fXEcdOe7Yesevw#C707S610000">707/610</a>; <a href="http://www.google.com/url?id=6ugYAAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc707/defs707.htm&amp;usg=AFQjCNE7Q7Bg2eD2wcE_fXEcdOe7Yesevw#C707S758000">707/758</a>; <a href="http://www.google.com/url?id=6ugYAAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc707/defs707.htm&amp;usg=AFQjCNE7Q7Bg2eD2wcE_fXEcdOe7Yesevw#C707S822000">707/822</a>; <a href="http://www.google.com/url?id=6ugYAAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc707/defs707.htm&amp;usg=AFQjCNE7Q7Bg2eD2wcE_fXEcdOe7Yesevw#C707S922000">707/922</a>; <a href="http://www.google.com/url?id=6ugYAAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc707/defs707.htm&amp;usg=AFQjCNE7Q7Bg2eD2wcE_fXEcdOe7Yesevw#C707S999201">707/999.201</a>; <a href="http://www.google.com/url?id=6ugYAAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc714/defs714.htm&amp;usg=AFQjCNF69HBVWbRkdZeFUtAyhUaqKU35WQ#C714SE11128">714/E11.128</a>; <a href="http://www.google.com/url?id=6ugYAAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc714/defs714.htm&amp;usg=AFQjCNF69HBVWbRkdZeFUtAyhUaqKU35WQ#C714SE11129">714/E11.129</a><br><b>International Classification</b>:&nbsp;G06F 1730<br><br><a href="http://www.google.com/url?id=6ugYAAAAEBAJ&q=http://patft.uspto.gov/netacgi/nph-Parser%3FSect2%3DPTO1%26Sect2%3DHITOFF%26p%3D1%26u%3D/netahtml/PTO/search-bool.html%26r%3D1%26f%3DG%26l%3D50%26d%3DPALL%26RefSrch%3Dyes%26Query%3DPN/6000000&usg=AFQjCNHQe58cLDibgjrHG7uGevnXq32obA">View patent at USPTO</a><br><a href="http://www.google.com/url?id=6ugYAAAAEBAJ&q=http://assignments.uspto.gov/assignments/q%3Fdb%3Dpat%26pat%3D6000000&usg=AFQjCNFUf72o2fuG7JlDHkxOD7Nx6yQd5A">Search USPTO Assignment Database</a><br></div></table></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="patent_citations_anchor"></a>Citations</h3><div id=patent_citations class=about_content><div id=patent_citations_v><table class=rel_patent style="border-spacing:10px 0" cellpadding=4><tr><td class=rel_patent_header><b>Cited Patent</b></td><td class=rel_patent_header><b>Filing date</b></td><td class=rel_patent_header><b>Issue date</b></td><td class=rel_patent_header><b>Original Assignee</b></td><td class="rel_patent_header rel_patent_title"><b>Title</b></td></tr><tr><td valign=top nowrap><a href="/patents/US4432057">US4432057</a></td><td valign=top nowrap>Nov 27, 1981</td><td valign=top nowrap>Feb 14, 1984</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Method for the dynamic replication of data under distributed system control to control utilization of resources in a multiprocessing, distributed data base system</td></tr><tr><td valign=top nowrap><a href="/patents/US4807182">US4807182</a></td><td valign=top nowrap>Mar 12, 1986</td><td valign=top nowrap>Feb 21, 1989</td><td valign=top>Advanced Software, Inc.</td><td class=rel_patent_title valign=top>Apparatus and method for comparing data groups</td></tr><tr><td valign=top nowrap><a href="/patents/US4866611">US4866611</a></td><td valign=top nowrap>Jan 29, 1987</td><td valign=top nowrap>Sep 12, 1989</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Method for automatically reconciling entries on two copies of independently maintained electronic calendars</td></tr><tr><td valign=top nowrap><a href="/patents/US4875159">US4875159</a></td><td valign=top nowrap>Dec 22, 1987</td><td valign=top nowrap>Oct 17, 1989</td><td valign=top>Amdahl Corporation</td><td class=rel_patent_title valign=top>Version management system using plural control fields for synchronizing two versions of files in a multiprocessor system</td></tr><tr><td valign=top nowrap><a href="/patents/US4956809">US4956809</a></td><td valign=top nowrap>Dec 29, 1988</td><td valign=top nowrap>Sep 11, 1990</td><td valign=top>Mark Williams Company</td><td class=rel_patent_title valign=top>Method for canonical ordering of binary data for portable operating systems</td></tr><tr><td valign=top nowrap><a href="/patents/US5001628">US5001628</a></td><td valign=top nowrap>Sep 1, 1989</td><td valign=top nowrap>Mar 19, 1991</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Single system image uniquely defining an environment for each user in a data processing system</td></tr><tr><td valign=top nowrap><a href="/patents/US5065360">US5065360</a></td><td valign=top nowrap>Jan 10, 1989</td><td valign=top nowrap>Nov 12, 1991</td><td valign=top></td><td class=rel_patent_title valign=top>Portable data storage and editing device</td></tr><tr><td valign=top nowrap><a href="/patents/US5124909">US5124909</a></td><td valign=top nowrap>Oct 31, 1988</td><td valign=top nowrap>Jun 23, 1992</td><td valign=top>Hewlett-Packard Company<br>Canon Kabushiki Kaisha</td><td class=rel_patent_title valign=top>Software program for providing cooperative processing between personal computers and a host computer</td></tr><tr><td valign=top nowrap><a href="/patents/US5142619">US5142619</a></td><td valign=top nowrap>Aug 23, 1991</td><td valign=top nowrap>Aug 25, 1992</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Method and apparatus for visually comparing files in a data processing system</td></tr><tr><td valign=top nowrap><a href="/patents/US5159592">US5159592</a></td><td valign=top nowrap>Oct 29, 1990</td><td valign=top nowrap>Oct 27, 1992</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Network address management for a wired network supporting wireless communication to a plurality of mobile users</td></tr><tr><td valign=top nowrap><a href="/patents/US5187787">US5187787</a></td><td valign=top nowrap>Jul 27, 1989</td><td valign=top nowrap>Feb 16, 1993</td><td valign=top>Teknekron Software Systems, Inc.</td><td class=rel_patent_title valign=top>Apparatus and method for providing decoupling of data exchange details for providing high performance communication between software processes</td></tr><tr><td valign=top nowrap><a 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2, 1999</td><td valign=top>Paxton Developments Inc.</td><td class=rel_patent_title valign=top>Method and apparatus for electronically accessing and distributing personal health care information and services in hospitals and homes</td></tr></table></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="patent_referenced_by_anchor"></a>Referenced by</h3><div id=patent_referenced_by class=about_content><div id=patent_referenced_by_v><table class=rel_patent style="border-spacing:10px 0" cellpadding=4><tr><td class=rel_patent_header><b>Citing Patent</b></td><td class=rel_patent_header><b>Filing date</b></td><td class=rel_patent_header><b>Issue date</b></td><td class=rel_patent_header><b>Original Assignee</b></td><td class="rel_patent_header rel_patent_title"><b>Title</b></td></tr><tr><td valign=top nowrap><a href="/patents/US6098100">US6098100</a></td><td valign=top nowrap>Jun 8, 1998</td><td valign=top nowrap>Aug 1, 2000</td><td valign=top>Silicon Integrated Systems Corp.</td><td class=rel_patent_title valign=top>Method and apparatus for detecting a wake packet issued by a network device to a sleeping node</td></tr><tr><td valign=top nowrap><a href="/patents/US6178015">US6178015</a></td><td valign=top nowrap>Jun 5, 1998</td><td valign=top nowrap>Jan 23, 2001</td><td valign=top>Mustek Systems, Inc.</td><td class=rel_patent_title valign=top>Apparatus and method for increasing the scan accuracy and quality of the flatbed scanner by using close loop control</td></tr><tr><td valign=top nowrap><a href="/patents/US6240426">US6240426</a></td><td valign=top nowrap>Nov 18, 1998</td><td valign=top nowrap>May 29, 2001</td><td valign=top>Siemens Information & Communication Networks, Inc.</td><td class=rel_patent_title valign=top>Method and apparatus for synchronizing information between a mobile device and a data collection device through a telephone switching network</td></tr><tr><td valign=top nowrap><a href="/patents/US6249849">US6249849</a></td><td valign=top nowrap>Jun 16, 1999</td><td valign=top nowrap>Jun 19, 2001</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>"Fail-Safe" updating of redundant data in multiple data storage libraries</td></tr><tr><td valign=top nowrap><a href="/patents/US6272545">US6272545</a></td><td valign=top nowrap>Oct 22, 1998</td><td valign=top nowrap>Aug 7, 2001</td><td valign=top>Microsoft Corporation</td><td class=rel_patent_title valign=top>System and method for interaction between one or more desktop computers and one or more mobile devices</td></tr><tr><td valign=top nowrap><a href="/patents/US6301020">US6301020</a></td><td valign=top nowrap>Aug 7, 1998</td><td valign=top nowrap>Oct 9, 2001</td><td valign=top>Hewlett-Packard Company</td><td class=rel_patent_title valign=top>Appliance and method for capturing images having a user error interface</td></tr><tr><td valign=top nowrap><a href="/patents/US6308201">US6308201</a></td><td valign=top nowrap>Apr 8, 1999</td><td valign=top nowrap>Oct 23, 2001</td><td valign=top>Palm, Inc.</td><td class=rel_patent_title valign=top>System and method for sharing data among a plurality of personal digital assistants</td></tr><tr><td valign=top nowrap><a href="/patents/US6324544">US6324544</a></td><td valign=top nowrap>Oct 21, 1998</td><td valign=top nowrap>Nov 27, 2001</td><td valign=top>Microsoft Corporation</td><td class=rel_patent_title valign=top>File object synchronization between a desktop computer and a mobile device</td></tr><tr><td valign=top nowrap><a href="/patents/US6336172">US6336172</a></td><td valign=top nowrap>Apr 1, 1999</td><td valign=top nowrap>Jan 1, 2002</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Storing and tracking multiple copies of data in a data storage library system</td></tr><tr><td valign=top nowrap><a href="/patents/US6336173">US6336173</a></td><td valign=top nowrap>Apr 1, 1999</td><td valign=top nowrap>Jan 1, 2002</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Storing and tracking multiple copies of data in data storage libraries</td></tr><tr><td valign=top nowrap><a href="/patents/US6341316">US6341316</a></td><td valign=top nowrap>Apr 28, 2000</td><td valign=top nowrap>Jan 22, 2002</td><td valign=top>AvantGo, Inc.</td><td class=rel_patent_title valign=top>System, method, and computer program product for synchronizing content between a server and a client based on state information</td></tr><tr><td valign=top nowrap><a href="/patents/US6370389">US6370389</a></td><td valign=top nowrap>Oct 30, 1998</td><td valign=top nowrap>Apr 9, 2002</td><td valign=top>Nokia Mobile Phones, Ltd.</td><td class=rel_patent_title valign=top>Communication network terminal supporting a plurality of applications</td></tr><tr><td valign=top nowrap><a href="/patents/US6389457">US6389457</a></td><td valign=top nowrap>Feb 13, 2001</td><td valign=top nowrap>May 14, 2002</td><td valign=top>Research In Motion Limited</td><td class=rel_patent_title valign=top>System and method for pushing information from a host system to a mobile data communication device</td></tr><tr><td valign=top nowrap><a href="/patents/US6401113">US6401113</a></td><td valign=top nowrap>Feb 13, 2001</td><td valign=top nowrap>Jun 4, 2002</td><td valign=top>Research In Motion Limited</td><td class=rel_patent_title valign=top>System and method for pushing information from a host system to a mobile data communication device</td></tr><tr><td valign=top nowrap><a href="/patents/US6429402">US6429402</a></td><td valign=top nowrap>Jun 2, 2000</td><td valign=top nowrap>Aug 6, 2002</td><td valign=top>The Regents of the University of California</td><td class=rel_patent_title valign=top>Controlled laser production of elongated articles from particulates</td></tr><tr><td valign=top nowrap><a href="/patents/US6438585">US6438585</a></td><td valign=top nowrap>Jan 16, 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valign=top nowrap>Apr 29, 1999</td><td valign=top nowrap>Apr 15, 2003</td><td valign=top>WaveWare Communications, Inc.</td><td class=rel_patent_title valign=top>Synchronization of host computers and handheld remote computers</td></tr><tr><td valign=top nowrap><a href="/patents/US6553037">US6553037</a></td><td valign=top nowrap>Apr 8, 1999</td><td valign=top nowrap>Apr 22, 2003</td><td valign=top>Palm, Inc.</td><td class=rel_patent_title valign=top>System and method for synchronizing data among a plurality of users via an intermittently accessed network</td></tr><tr><td valign=top nowrap><a href="/patents/US6611849">US6611849</a></td><td valign=top nowrap>Sep 29, 2000</td><td valign=top nowrap>Aug 26, 2003</td><td valign=top>Palm Source, Inc.</td><td class=rel_patent_title valign=top>System for synchronizing databases on multiple devices utilizing a home base</td></tr><tr><td valign=top nowrap><a href="/patents/US6621508">US6621508</a></td><td valign=top nowrap>Jan 18, 2000</td><td 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valign=top nowrap>Feb 24, 2009</td><td valign=top>Apple Inc.</td><td class=rel_patent_title valign=top>Touch pad for handheld device</td></tr><tr><td valign=top nowrap><a href="/patents/US7499040">US7499040</a></td><td valign=top nowrap>Aug 18, 2003</td><td valign=top nowrap>Mar 3, 2009</td><td valign=top>Apple Inc.</td><td class=rel_patent_title valign=top>Movable touch pad with added functionality</td></tr><tr><td valign=top nowrap><a href="/patents/US7502752">US7502752</a></td><td valign=top nowrap>Sep 27, 2000</td><td valign=top nowrap>Mar 10, 2009</td><td valign=top>Citicorp Development Center, Inc.</td><td class=rel_patent_title valign=top>System and method for delivering financial services</td></tr><tr><td valign=top nowrap><a href="/patents/US7505762">US7505762</a></td><td valign=top nowrap>Feb 27, 2004</td><td valign=top nowrap>Mar 17, 2009</td><td valign=top>Fusionone, Inc.</td><td class=rel_patent_title valign=top>Wireless telephone data backup system</td></tr><tr><td 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valign=top nowrap>Sep 7, 2007</td><td valign=top nowrap>Mar 27, 2012</td><td valign=top>ManageIQ, Inc.</td><td class=rel_patent_title valign=top>Method and apparatus for interfacing with a computer user via virtual thumbnails</td></tr><tr><td valign=top nowrap><a href="/patents/US8150937">US8150937</a></td><td valign=top nowrap>Nov 12, 2004</td><td valign=top nowrap>Apr 3, 2012</td><td valign=top>Apple Inc.</td><td class=rel_patent_title valign=top>Wireless synchronization between media player and host device</td></tr><tr><td valign=top nowrap><a href="/patents/US8156074">US8156074</a></td><td valign=top nowrap>Jan 26, 2000</td><td valign=top nowrap>Apr 10, 2012</td><td valign=top>Synchronoss Technologies, Inc.</td><td class=rel_patent_title valign=top>Data transfer and synchronization system</td></tr><tr><td valign=top nowrap><a href="/patents/US8165575">US8165575</a></td><td valign=top nowrap>May 19, 2011</td><td valign=top nowrap>Apr 24, 2012</td><td valign=top>Research In Motion Limited</td><td class=rel_patent_title valign=top>Wireless router system and method</td></tr><tr><td valign=top nowrap><a href="/patents/US8166164">US8166164</a></td><td valign=top nowrap>Oct 14, 2011</td><td valign=top nowrap>Apr 24, 2012</td><td valign=top>Seven Networks, Inc.</td><td class=rel_patent_title valign=top>Application and network-based long poll request detection and cacheability assessment therefor</td></tr><tr><td valign=top nowrap><a href="/patents/US8180900">US8180900</a></td><td valign=top nowrap>Feb 15, 2008</td><td valign=top nowrap>May 15, 2012</td><td valign=top>Research In Motion Limited</td><td class=rel_patent_title valign=top>System and method of managing information distribution to mobile stations</td></tr><tr><td valign=top nowrap><a href="/patents/US8181111">US8181111</a></td><td valign=top nowrap>Dec 31, 2008</td><td valign=top nowrap>May 15, 2012</td><td valign=top>Synchronoss Technologies, Inc.</td><td class=rel_patent_title valign=top>System and method for providing social context to digital activity</td></tr><tr><td valign=top nowrap><a href="/patents/US8188357">US8188357</a></td><td valign=top nowrap>May 12, 2009</td><td valign=top nowrap>May 29, 2012</td><td valign=top>Apple Inc.</td><td class=rel_patent_title valign=top>Graphical user interface and methods of use thereof in a multimedia player</td></tr><tr><td valign=top nowrap><a href="/patents/US8190701">US8190701</a></td><td valign=top nowrap>Nov 1, 2011</td><td valign=top nowrap>May 29, 2012</td><td valign=top>Seven Networks, Inc.</td><td class=rel_patent_title valign=top>Cache defeat detection and caching of content addressed by identifiers intended to defeat cache</td></tr><tr><td valign=top nowrap><a href="/patents/USRE41006">USRE41006</a></td><td valign=top nowrap>Jul 5, 2005</td><td valign=top nowrap>Nov 24, 2009</td><td valign=top>TeleCommunication Systems, Inc.</td><td class=rel_patent_title valign=top>Inter-carrier short messaging service providing phone number only experience</td></tr></table></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="patent_claims_anchor"></a>Claims</h3><div id=patent_claims class=about_content><div id=patent_claims_v><p>1. A method of sharing information on a first computer system and a second computer system, said method comprising:<p><dl><dd style="margin-left:1em;">connecting said first computer system to said second computer system with a data communications link;</dd><dd style="margin-left:1em;">providing a library of functions in said second computer system for accessing information on said first computer system;</dd><dd style="margin-left:1em;">creating a conduit program database, said conduit program database for storing a list of conduit programs that may be executed,</dd><dd style="margin-left:1em;">registering a first conduit program by placing an identifier for said first conduit program in said conduit program database, said first conduit program comprising a computer program on said second computer system for performing a specific data transfer task;</dd><dd style="margin-left:1em;">successively executing a set of conduit programs identified within said conduit program database from a manager program, each of said conduit programs accessing said library of functions for communicating with said first computer system.</dd></dl><p>2. The method of sharing information as claimed in claim 1 further comprising:<p><dl><dd style="margin-left:1em;">registering a second conduit program by placing an identifier for said second conduit program in said conduit program database, said second conduit program comprising a computer program on said second computer system for performing a specific data transfer task.</dd></dl><p>3. The method of sharing information as claimed in claim 1 further comprising:<p><dl><dd style="margin-left:1em;">executing a memory resident program in said second computer system; and</dd><dd style="margin-left:1em;">loading in and executing said manager program when said memory resident program detects that a synchronization has been requested by a user.</dd></dl><p>4. The method of sharing information as claimed in claim 3 further comprising:<p><dl><dd style="margin-left:1em;">monitoring said communications link from said memory resident program; and</dd><dd style="margin-left:1em;">detecting a synchronization request when a predetermined packet is received on said communications link.</dd></dl><p>5. The method of sharing information as claimed in claim 3 further comprising:<p><dl><dd style="margin-left:1em;">providing a communication link library, said communication link library comprising a set of functions in said second computer system for communicating across said data communications link,</dd></dl><p><dl><dd style="margin-left:1em;">wherein said library of functions in said second computer system for accessing information on said first computer system uses said communication link library for communicating across said data communications link.</dd></dl><p>6. The method of sharing information as claimed in claim 1 wherein said first conduit program comprises an installation program that loads a new software program onto said first computer system.<p>7. The method of sharing information as claimed in claim 1 wherein said first conduit program sends and retrieves queued email.<p>8. The method of sharing information as claimed in claim 1 wherein said first conduit program analyzes and cleans up a file system on said first computer system.<p>9. The method of sharing information as claimed in claim 1 wherein said first conduit program performs the following steps<p><dl><dd style="margin-left:1em;">retrieving a set of modified records from a first database on said first computer;</dd><dd style="margin-left:1em;">comparing said set of modified records retrieved from said first database on said first computer system with a second database on said second computer system to create a synchronized database; and</dd><dd style="margin-left:1em;">writing records from said synchronized database to said first database on said first computer system.</dd></dl><p>10. The method of sharing information as claimed in claim 1 wherein said first conduit program performs the following steps:<p><dl><dd style="margin-left:1em;">retrieving all records from a first database on said first computer;</dd><dd style="margin-left:1em;">comparing said records retrieved from said first database on said first computer system with a second database on said second computer system to create a synchronized database; and</dd><dd style="margin-left:1em;">writing records from said synchronized database to said first database on said first computer system.</dd></dl><p>11. An apparatus for transferring information on a first computer system and a second computer system, said apparatus comprising:<p><dl><dd style="margin-left:1em;">a data communications link, said data communications link connecting said first computer system to said second computer system;</dd><dd style="margin-left:1em;">a conduit program registry on said second computer system, said conduit program registry storing a list of identifiers of conduit programs that perform specific data transfer tasks;</dd><dd style="margin-left:1em;">at least one conduit program on said second computer system, said conduit program registered in said conduit program registry, said conduit program for transferring information between said first computer system and said second computer system; and</dd><dd style="margin-left:1em;">a manager program on said second computer system, said manager program successively invoking said conduit programs.</dd></dl><p>12. The apparatus as claimed in claim 11 wherein said conduit program comprises an installation program that loads a new software program onto said first computer system.<p>13. The apparatus as claimed in claim 11 wherein said conduit program sends and retrieves queued email.<p>14. The apparatus as claimed in claim 11 wherein said conduit program analyzes and cleans up a file system on said first computer system.<p>15. The apparatus for transferring information as claimed in claim 11 further comprising:<p><dl><dd style="margin-left:1em;">a memory resident program in said second computer system, said memory resident program loading in said manager program when said memory resident program determines that a synchronization has been requested by a user.</dd></dl><p>16. The apparatus for transferring information as claimed in claim 11 further comprising:<p><dl><dd style="margin-left:1em;">a sync manager link library on said second computer system, said sync manager link library comprising a set of functions for accessing information on said first computer system from said second computer system.</dd></dl><p>17. The apparatus for transferring information as claimed in claim 16 further comprising:<p><dl><dd style="margin-left:1em;">a communications link library, said communications link library comprising a set of communication functions for communicating via said data communications link, said sync manager link library accessing said set of communication functions for communicating via said data communications link.</dd></dl><p>18. The apparatus for transferring information as claimed in claim 11 further comprising:<p><dl><dd style="margin-left:1em;">a first database on said first computer; and</dd><dd style="margin-left:1em;">a second database on said second computer, said conduit program reconciling said first database with said second database.</dd></dl><p>19. A cooperative computer system apparatus for transferring information, said apparatus comprising:<p><dl><dd style="margin-left:1em;">a first computer system;</dd><dd style="margin-left:1em;">a second computer system;</dd><dd style="margin-left:1em;">a data communications link, said data communications link coupling said first computer system to said second computer system;</dd><dd style="margin-left:1em;">at least one conduit program on said second computer system, said conduit program for transferring information between said first computer system and said second computer system;</dd><dd style="margin-left:1em;">a synchronization registry on said second computer system, said synchronization registry containing a list of said conduit programs; and</dd><dd style="margin-left:1em;">a manager program on said second computer system, said manager program successively invoking said list of said conduit programs.</dd></dl><p>20. The apparatus as claimed in claim 19 further comprising:<p><dl><dd style="margin-left:1em;">a memory resident program in said second computer system, said memory resident program loading in and executing said manager program when said memory resident program determines that a synchronization has been requested by a user.</dd></dl><p>21. The apparatus as claimed in claim 19 wherein said conduit program comprises an installation program that loads a new software program onto said first computer system.<p>22. The apparatus as claimed in claim 19 wherein said conduit program sends and retrieves queued email.<p>23. The apparatus as claimed in claim 19 wherein said conduit program analyzes and cleans up a file system on said first computer system.<p>24. The apparatus for transferring information as claimed in claim 19 further comprising:<p><dl><dd style="margin-left:1em;">a sync manager link library on said second computer system, said sync manager link library comprising a set of functions for accessing information on said first computer system from said second computer system.</dd></dl><p>25. The apparatus for transferring information as claimed in claim 24 further comprising:<p><dl><dd style="margin-left:1em;">a communications link library, said communications link library comprising a set of communication functions for communicating via said data communications link, said sync manager link library accessing said set of communication functions for communicating via said data communications link.</dd></dl><p>26. The apparatus for transferring information as claimed in claim 19 further comprising:<p><dl><dd style="margin-left:1em;">a first database on said first computer; and</dd><dd style="margin-left:1em;">a second database on said second computer, said conduit program reconciling said first database with said second database.</dd></dl><p>27. The cooperative computer system as claimed in claim 19 wherein said manager program comprises a set of functions for communicating with said first computer system.</div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="selected_pages_anchor"></a>Drawings</h3><div id=selected_pages class=about_content><div id=selected_pages_v><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=6ugYAAAAEBAJ&pg=PA3&source=gbs_selected_pages&cad=4" ><img src="http://bks2.books.google.com/patents?id=6ugYAAAAEBAJ&amp;pg=PA3&amp;img=1&amp;zoom=1&amp;sig=ACfU3U2oItRdy5y9tfUgqdehtgHx40yoCA" alt="Drawings" title="Drawings" height="160" border="1"></a><br/><a class="primary" href="http://www.google.com/patents?id=6ugYAAAAEBAJ&pg=PA3&source=gbs_selected_pages&cad=4" >Drawings</a></div><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=6ugYAAAAEBAJ&pg=PA4&source=gbs_selected_pages&cad=4" ><img src="http://bks2.books.google.com/patents?id=6ugYAAAAEBAJ&amp;pg=PA4&amp;img=1&amp;zoom=1&amp;sig=ACfU3U1wxuplx_ni7bVhJIbugenbCe9udw" alt="Drawings" title="Drawings" height="160" border="1"></a><br/><a class="primary" href="http://www.google.com/patents?id=6ugYAAAAEBAJ&pg=PA4&source=gbs_selected_pages&cad=4" >Drawings</a></div><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=6ugYAAAAEBAJ&pg=PA5&source=gbs_selected_pages&cad=4" ><img src="http://bks2.books.google.com/patents?id=6ugYAAAAEBAJ&amp;pg=PA5&amp;img=1&amp;zoom=1&amp;sig=ACfU3U0I7jkmnC88v5usm0_ovEDGbARq6A" alt="Drawings" title="Drawings" height="160" border="1"></a><br/><a class="primary" href="http://www.google.com/patents?id=6ugYAAAAEBAJ&pg=PA5&source=gbs_selected_pages&cad=4" >Drawings</a></div><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=6ugYAAAAEBAJ&pg=PA6&source=gbs_selected_pages&cad=4" ><img src="http://bks2.books.google.com/patents?id=6ugYAAAAEBAJ&amp;pg=PA6&amp;img=1&amp;zoom=1&amp;sig=ACfU3U13pMXj81bq2kXA0Dk9veS9iqppBQ" alt="Drawings" title="Drawings" height="160" border="1"></a><br/><a class="primary" href="http://www.google.com/patents?id=6ugYAAAAEBAJ&pg=PA6&source=gbs_selected_pages&cad=4" >Drawings</a></div><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=6ugYAAAAEBAJ&pg=PA7&source=gbs_selected_pages&cad=4" ><img src="http://bks2.books.google.com/patents?id=6ugYAAAAEBAJ&amp;pg=PA7&amp;img=1&amp;zoom=1&amp;sig=ACfU3U3CgQA3TmdKC2p4sPlK7LUW5WHj5w" alt="Drawings" title="Drawings" height="160" border="1"></a><br/><a class="primary" href="http://www.google.com/patents?id=6ugYAAAAEBAJ&pg=PA7&source=gbs_selected_pages&cad=4" >Drawings</a></div><div style="clear:both;"></div></div></div></div></td></tr></table><script type="text/javascript">_OC_addFlags({LockSrc:"/books/javascript/lock_b9ee852b3231a450c67d122471b67ac7.js", IsWebstoreDisplayCaseEnabled:1, IsObfuscationEnabled:1, IsBrowsingHistoryEnabled:1, IsGeoLayerEnabled:0, IsGiftingEnabled:0, IsOfflineBubbleEnabled:1, IsReaderEnabledForPlayRequests:1, IsUnifiedHovercardEnabled:1, IsFutureOnSaleVolumesEnabled:1, IsBooksUnifiedLeftNavEnabled:1, IsZipitFolderCollectionEnabled:1, IsRatingsOnBookcardsEnabled:1, IsEmbeddedMediaEnabled:1, IsImageModeAnnotationsEnabled:0, IsMyLibraryGooglePlusEnabled:1, IsBookcardListPriceSmall:0, IsBooksShareButtonEnabled:0, IsPreOrdersEnabled:1, IsDisabledRandomBookshelves:0, WebstoreDisplayCasePosition:3});_OC_addMsgs();_OC_Run({"enable_p13n":false,"add_vol_to_collection_base_url":"http://www.google.com/patents?op=add\u0026sig=ACfU3U2NR9gLbaUjBBmf3hRNvlVxNGjPdw\u0026id=6ugYAAAAEBAJ","remove_vol_from_collection_base_url":"http://www.google.com/patents?op=remove\u0026sig=ACfU3U1ASqT0009jj4tQlE1VzGgKmai3sA\u0026id=6ugYAAAAEBAJ","logged_in":true,"p13n_save_user_settings_url":"http://www.google.com/patents?op=edit_user_settings\u0026sig=ACfU3U1csLrPRWWF41pcqYdLt6glRm7l_A","is_cobrand":false,"is_play_enabled":true}, {"volume_id":"","is_ebook":true,"volumeresult":{"has_flowing_text":false,"has_scanned_text":true,"can_download_pdf":false,"can_download_epub":false,"is_pdf_drm_enabled":false,"is_epub_drm_enabled":false,"download_pdf_url":"http://www.google.com/patents/download/6000000_Extendible_method_and_apparatus.pdf?id=6ugYAAAAEBAJ\u0026output=pdf\u0026sig=ACfU3U09g9xRAzHbBUpfHfVx_9C3TRD2WA"},"sample_url":"http://www.google.com/patents/reader?id=6ugYAAAAEBAJ\u0026printsec=frontcover\u0026output=reader\u0026source=gbs_atb_hover","is_browsable":true,"is_public_domain":true}, {"uid":"112034765180046512987"});</script><div id="footer_table" style="font-size:83%;text-align:center;position:relative;top:20px;height:4.5em;margin-top:2em"><div style="margin-bottom:8px"><a href=http://www.google.com/><nobr>Google&nbsp;Home</nobr></a> - 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The second level cache holds tag address words each having two status bits V and R. The V bit indicates validity/invalidity status while the R bit informs the second level cache of the validity/invalidity status of the corresponding address in the first level cache. As a result of the status information between the two caches, the spy-snoop operation and invalidation operation cycles are minimized as to the use required of the processor bus, enabling higher efficiency processor operations. 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id="appbar-view-ebook-sample-link" href=""></a><a id="appbar-patents-prior-art-finder-link" href=""></a><a id="appbar-read-patent-link" href="/patents/US6000015?printsec=abstract"></a><a id="appbar-download-pdf-link" href="/patents/US6000015.pdf"></a></div><div class="kd-buttonbar right" id="right-toolbar-buttons"></div></div><div id="books-microdata" itemscope=""itemtype="http://schema.org/Book"itemid="http://www.google.com/patents/US6000015" style="display:none"><span itemprop="description">A small first level cache and large second level cache support a central processor in accessing necessary data for processing. The second level cache holds tag address words each having two status bits V and R. The V bit indicates validity/invalidity status while the R bit informs the second level cache...</span><span itemprop="url">http://www.google.com/patents/US6000015?utm_source=gb-gplus-share</span><span class="main-title" itemprop="name">Patent US6000015 - Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in a higher level cache</span><img itemprop="image" src="http://www.google.com/patents?id=-OgYAAAAEBAJ&amp;printsec=frontcover&amp;img=1&amp;zoom=1"alt="Patent US6000015 - Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in a higher level cache" title="Patent US6000015 - Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in a higher level cache"></div><table id="viewport_table" cellpadding="0" style="clear:both" cellspacing="0"><tr><td id="menu_td" class="menu_td"><div id=menu_container><div class=menu id=menu><div class="menu_content" style="margin-bottom:6px"><div id="volume-info-sidebar"><span class="gb-survey-link"></span><h1 class="gb-volume-title" dir=ltr>Processor bus traffic optimization system for multi-level cache utilizing ...</h1>&nbsp;<span class="addmd">Bruce Ernest Whittaker</span></div><div style="margin-bottom:4px"><div class=sidebarnav><div class=sidebarcover><a href="http://www.google.com/patents?id=-OgYAAAAEBAJ&printsec=abstract&zoom=4" ><img src="http://bks2.books.google.com/patents?id=-OgYAAAAEBAJ&printsec=abstract&img=1&zoom=1&sig=ACfU3U2WBcgvT0jZ7JbdSGqG9z-eczyXtw" alt="Abstract" title="Abstract" width=102 border=1 id=summary-frontcover ></a></div><span class=nolink>&rsaquo;&nbsp;Overview</span><br><a href="/patents/US6000015?printsec=abstract">Abstract</a><br><a href="/patents/US6000015?printsec=drawing">Drawings</a><br><a href="/patents/US6000015?printsec=description">Description</a><br><a href="/patents/US6000015?printsec=claims">Claims</a><br><span id="gb-atb-patents-plusone-container"></span></div></div></div><div style="clear:both"></div><div style="margin-left:10px"><form action=/patents id=search_form style="margin:0px;padding:0px;" method=get> <input type=hidden name=id value="-OgYAAAAEBAJ"><table cellpadding=0 cellspacing=0 class="swv-table"><tr><td width="100%" class="swv-td-search"><span><input id=search_form_input type=text maxlength=1024 class="text_flat swv-input-search" name=q value="" title="Go" accesskey=i></span></td><td class="swv-td-space">&nbsp;&nbsp;</td><td><input type=submit value="Go"></td></tr></table><script type="text/javascript">if (window['_OC_autoDir']) {_OC_autoDir('search_form_input');}</script></form></div><div id="menu_scroll"><div id=metadata_content class=menu_content><div id=metadata_v><div class=patent_bibdata><p><b>Patent number</b>: 6000015<br><b>Filing date</b>: Jan 16, 1999<br><b>Issue date</b>: Dec 7, 1999<br></p></div></div></div></div></div></div></td><td id="viewport_td"><div class=vertical_module_list_row><div id=overview class=about_content><div id=overview_v><table id="summarytable" cellpadding="0" cellspacing="0" border="0" width="100%"><tr><td valign=top><p class="patent_abstract_text">A small first level cache and large second level cache support a central processor in accessing necessary data for processing. The second level cache holds tag address words each having two status bits V and R. The V bit indicates validity/invalidity status while the R bit informs the second level cache of the validity/invalidity status of the corresponding address in the first level cache. As a result of the status information between the two caches, the spy-snoop operation and invalidation operation cycles are minimized as to the use required of the processor bus, enabling higher efficiency processor operations. Utilization is made of a smart-fill algorithm which selects the address locations for placement of new data in a second level cache for a Write operation and after a Read-Miss by analyzing the status values (V,R) for each address in order to minimize the overwriting of valid cache data.</p><div class="patent_bibdata"><b>Inventor</b>:&nbsp;<a href="http://www.google.com/search?tbo=p&amp;tbm=pts&amp;hl=en&amp;q=ininventor:%22Bruce+Ernest+Whittaker%22">Bruce Ernest Whittaker</a><br><b>Original Assignee</b>:&nbsp;<a href="http://www.google.com/search?tbo=p&amp;tbm=pts&amp;hl=en&amp;q=inassignee:%22Unisys+Corporation%22">Unisys Corporation</a><br><b>Primary Examiner</b>:&nbsp;Christopher S. Chow<br><b>Current U.S. Classification</b>:&nbsp;<a href="http://www.google.com/url?id=-OgYAAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc711/defs711.htm&amp;usg=AFQjCNFvcWlFh993jZihOpA01Yh9sD4HJQ#C711S134000">711/134</a>; <a href="http://www.google.com/url?id=-OgYAAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc711/defs711.htm&amp;usg=AFQjCNFvcWlFh993jZihOpA01Yh9sD4HJQ#C711S122000">711/122</a>; <a href="http://www.google.com/url?id=-OgYAAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc711/defs711.htm&amp;usg=AFQjCNFvcWlFh993jZihOpA01Yh9sD4HJQ#C711S141000">711/141</a>; <a href="http://www.google.com/url?id=-OgYAAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc711/defs711.htm&amp;usg=AFQjCNFvcWlFh993jZihOpA01Yh9sD4HJQ#C711SE12024">711/E12.024</a><br><b>International Classification</b>:&nbsp;G06F 1314<br><br><a href="http://www.google.com/url?id=-OgYAAAAEBAJ&q=http://patft.uspto.gov/netacgi/nph-Parser%3FSect2%3DPTO1%26Sect2%3DHITOFF%26p%3D1%26u%3D/netahtml/PTO/search-bool.html%26r%3D1%26f%3DG%26l%3D50%26d%3DPALL%26RefSrch%3Dyes%26Query%3DPN/6000015&usg=AFQjCNHfe2Leood9G4wvV9KO3sWbYhfP0g">View patent at USPTO</a><br><a href="http://www.google.com/url?id=-OgYAAAAEBAJ&q=http://assignments.uspto.gov/assignments/q%3Fdb%3Dpat%26pat%3D6000015&usg=AFQjCNFFl3G7_oVCPzcsZ3ssEwuGP8r2Hg">Search USPTO Assignment Database</a><br></div></table></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="patent_citations_anchor"></a>Citations</h3><div id=patent_citations class=about_content><div id=patent_citations_v><table class=rel_patent style="border-spacing:10px 0" cellpadding=4><tr><td class=rel_patent_header><b>Cited Patent</b></td><td class=rel_patent_header><b>Filing date</b></td><td class=rel_patent_header><b>Issue date</b></td><td class=rel_patent_header><b>Original Assignee</b></td><td class="rel_patent_header rel_patent_title"><b>Title</b></td></tr><tr><td valign=top nowrap><a href="/patents/US5058006">US5058006</a></td><td valign=top nowrap>Jun 27, 1988</td><td valign=top nowrap>Oct 15, 1991</td><td valign=top>Digital Equipment Corporation</td><td class=rel_patent_title valign=top>Method and apparatus for filtering invalidate requests</td></tr><tr><td valign=top nowrap><a href="/patents/US5136700">US5136700</a></td><td valign=top nowrap>Dec 22, 1989</td><td valign=top nowrap>Aug 4, 1992</td><td valign=top>Digital Equipment Corporation</td><td class=rel_patent_title valign=top>Apparatus and method for reducing interference in two-level cache memories</td></tr><tr><td valign=top nowrap><a href="/patents/US5197139">US5197139</a></td><td valign=top nowrap>Apr 5, 1990</td><td valign=top nowrap>Mar 23, 1993</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Cache management for multi-processor systems utilizing bulk cross-invalidate</td></tr><tr><td valign=top nowrap><a href="/patents/US5249284">US5249284</a></td><td valign=top nowrap>Dec 13, 1991</td><td valign=top nowrap>Sep 28, 1993</td><td valign=top>NCR Corporation</td><td class=rel_patent_title valign=top>Method and system for maintaining data coherency between main and cache memories</td></tr><tr><td valign=top nowrap><a href="/patents/US5369753">US5369753</a></td><td valign=top nowrap>May 27, 1993</td><td valign=top nowrap>Nov 29, 1994</td><td valign=top>Compaq Computer Corporation</td><td class=rel_patent_title valign=top>Method and apparatus for achieving multilevel inclusion in multilevel cache hierarchies</td></tr><tr><td valign=top nowrap><a href="/patents/US5530832">US5530832</a></td><td valign=top nowrap>Oct 14, 1993</td><td valign=top nowrap>Jun 25, 1996</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>System and method for practicing essential inclusion in a multiprocessor and cache hierarchy</td></tr><tr><td valign=top nowrap><a href="/patents/US5551001">US5551001</a></td><td valign=top nowrap>Jun 29, 1994</td><td valign=top nowrap>Aug 27, 1996</td><td valign=top>Exponential Technology, Inc.</td><td class=rel_patent_title valign=top>Master-slave cache system for instruction and data cache memories</td></tr><tr><td valign=top nowrap><a href="/patents/US5564035">US5564035</a></td><td valign=top nowrap>Mar 23, 1994</td><td valign=top nowrap>Oct 8, 1996</td><td valign=top>Intel Corporation</td><td class=rel_patent_title valign=top>Exclusive and/or partially inclusive extension cache system and method to minimize swapping therein</td></tr><tr><td valign=top nowrap><a href="/patents/US5577227">US5577227</a></td><td valign=top nowrap>Aug 4, 1994</td><td valign=top nowrap>Nov 19, 1996</td><td valign=top></td><td class=rel_patent_title valign=top>Method for decreasing penalty resulting from a cache miss in multi-level cache system</td></tr><tr><td valign=top nowrap><a href="/patents/US5584013">US5584013</a></td><td valign=top nowrap>Dec 9, 1994</td><td valign=top nowrap>Dec 10, 1996</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache</td></tr><tr><td valign=top nowrap><a href="/patents/US5584014">US5584014</a></td><td valign=top nowrap>Dec 20, 1994</td><td valign=top nowrap>Dec 10, 1996</td><td valign=top>Sun Microsystems, Inc.</td><td class=rel_patent_title valign=top>Apparatus and method to preserve data in a set associative memory device</td></tr><tr><td valign=top nowrap><a href="/patents/US5729712">US5729712</a></td><td valign=top nowrap>Jan 26, 1996</td><td valign=top nowrap>Mar 17, 1998</td><td valign=top>Unisys Corporation</td><td class=rel_patent_title valign=top>Smart fill system for multiple cache network</td></tr></table></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="patent_referenced_by_anchor"></a>Referenced by</h3><div id=patent_referenced_by class=about_content><div id=patent_referenced_by_v><table class=rel_patent style="border-spacing:10px 0" cellpadding=4><tr><td class=rel_patent_header><b>Citing Patent</b></td><td class=rel_patent_header><b>Filing date</b></td><td class=rel_patent_header><b>Issue date</b></td><td class=rel_patent_header><b>Original Assignee</b></td><td class="rel_patent_header rel_patent_title"><b>Title</b></td></tr><tr><td valign=top nowrap><a href="/patents/US6490660">US6490660</a></td><td valign=top nowrap>Jul 1, 2000</td><td valign=top nowrap>Dec 3, 2002</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Method and apparatus for a configurable multiple level cache with coherency in a multiprocessor system</td></tr><tr><td valign=top nowrap><a href="/patents/US6587923">US6587923</a></td><td valign=top nowrap>May 22, 2000</td><td valign=top nowrap>Jul 1, 2003</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Dual line size cache directory</td></tr><tr><td valign=top nowrap><a href="/patents/US6651143">US6651143</a></td><td valign=top nowrap>Dec 21, 2000</td><td valign=top nowrap>Nov 18, 2003</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Cache management using a buffer for invalidation requests</td></tr><tr><td valign=top nowrap><a href="/patents/US7007135">US7007135</a></td><td valign=top nowrap>Mar 8, 2002</td><td valign=top nowrap>Feb 28, 2006</td><td valign=top>Samsung Electronics Co., Ltd.</td><td class=rel_patent_title valign=top>Multi-level cache system with simplified miss/replacement control</td></tr></table></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="patent_claims_anchor"></a>Claims</h3><div id=patent_claims class=about_content><div id=patent_claims_v><p>1. In a digital network connected by a system bus means having a snoop logic module to retrieve addresses being modified, a central processor and processor bus having a multi-level cache system which reduces traffic on the processor bus of a central processor and allows different cache fill algorithms for a first and second level cache memory, said multi-level cache system comprising:<p><dl><dd style="margin-left:1em;">(a) a first level cache means for supplying requested data to said central processor and including:</dd><dd style="margin-left:1em;"><dl><dd style="margin-left:1em;">(a1) a first Tag array holding addresses of data in said first level cache where each address has an appended Validity V=1/Invalidity V=0 status bit (V);</dd><dd style="margin-left:1em;">(a2) cache fill means which uses a LRU fill algorithm to place data in said first level cache means for a Write OP and after a Read-Miss;</dd></dl></dd><dd style="margin-left:1em;">(b) a second level cache means of much larger capacity than said first level cache means for supplying to said central processor, requested data not available in said first level cache means, and including:</dd><dd style="margin-left:1em;"><dl><dd style="margin-left:1em;">(b1) a second Tag array holding addresses of data in said second level cache where each address has (i) an appended validity V=1/Invalidity V=0 status bit (V) and (ii) a Reflection bit (R) which indicates the validity R=1/invalidity R=0 of a duplicate copy of the address residing in said first level cache;</dd><dd style="margin-left:1em;">(b2) second cache fill means which uses a smart-fill algorithm to place data in said second level cache means for a Write OP and after a Read-Miss, said smart-fill algorithm for selecting addresses, for writing in new data, into addresses which minimize the overwriting of valid data in said second level cache means and which utilizes a random count generator to select addresses for overwriting when V=1 and R=1 for all addresses;</dd></dl></dd><dd style="margin-left:1em;">(c) said snoop logic module, connected to said system bus means, for holding addresses which have undergone modification and thus need to be invalidated in said second level and first level cache means;</dd><dd style="margin-left:1em;">(d) means using said processor bus, to transfer to said central processor for invalidation (V=0) only those invalidation addresses in said second level cache means which have the Reflection bit R=1 and are thus indicated as presently existing and marked valid (V=1) in said first level cache means in order that these first level cache addresses can be rendered invalid (V=0).</dd></dl><p>2. The system of claim 1 which includes:<p><dl><dd style="margin-left:1em;">(a) means, when said first level cache means is overfilled by a new address deleting an old address, to indicate in said second level cache means that, said old address in said first level cache means is invalid, by setting R=0 in said second level cache means.</dd></dl><p>3. The system of claim 1 which includes:<p><dl><dd style="margin-left:1em;">(a) means, when said second level cache means is overfilled with a new address deleting an old address, to transfer, only if said old address in said second level cache indicated the R bit=1, said old address to said first level cache means for invalidation so that V is made =0 in said first level cache means.</dd></dl><p>4. The system of claim 1 which includes:<p><dl><dd style="margin-left:1em;">(a) means in said snoop logic module for sending an address to said second level cache means for invalidation by setting the V status bit=0 for that address in said second level cache means;</dd><dd style="margin-left:1em;">(b) means to sense the R bit for said address sent to said second level cache means, to initiate a control decision logic means.</dd></dl><p>5. The system of claim 4 wherein said control decision logic means includes:<p><dl><dd style="margin-left:1em;">(a) means to sense when said R status bit is 0 for said address sent to said second level cache means, and then take no action for invalidating the same said address in said first level cache means.</dd></dl><p>6. The system of claim 5 wherein said control decision logic means further includes:<p><dl><dd style="margin-left:1em;">(a) means to sense when said R status bit=1 for said address sent to said second level cache means;</dd><dd style="margin-left:1em;">(b) means to initiate an invalidation operation in said first level cache means to invalidate and make V=0 for the same address in said first level cache means.</dd></dl><p>7. The system of claim 1 in which includes:<p><dl><dd style="margin-left:1em;">(a) means, when said snoop logic has sent an address to said second level cache means for invalidation, to set the V bit=0 for that sent-address in said second level cache means;</dd><dd style="margin-left:1em;">(b) means to sense the R bit at said sent-address in said second level cache means to initiate, when R=1, a transfer of said sent-address to said first level cache for invalidation, to make V=0.</dd></dl></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="selected_pages_anchor"></a>Drawings</h3><div id=selected_pages class=about_content><div id=selected_pages_v><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=-OgYAAAAEBAJ&pg=PA2&source=gbs_selected_pages&cad=4" ><img src="http://bks2.books.google.com/patents?id=-OgYAAAAEBAJ&amp;pg=PA2&amp;img=1&amp;zoom=1&amp;sig=ACfU3U1RKgU9Fw40Jkjut4zv24Cx-ZjwmA" alt="Drawings" title="Drawings" height="160" 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During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. 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id="appbar-download-pdf-link" href="/patents/US7114060.pdf"></a></div><div class="kd-buttonbar right" id="right-toolbar-buttons"></div></div><div id="books-microdata" itemscope=""itemtype="http://schema.org/Book"itemid="http://www.google.com/patents/US7114060" style="display:none"><span itemprop="description">One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering...</span><span itemprop="url">http://www.google.com/patents/US7114060?utm_source=gb-gplus-share</span><span class="main-title" itemprop="name">Patent US7114060 - Selectively deferring instructions issued in program order utilizing a checkpoint and multiple deferral scheme</span><img itemprop="image" src="http://www.google.com/patents?id=Bdt6AAAAEBAJ&amp;printsec=frontcover&amp;img=1&amp;zoom=1"alt="Patent US7114060 - Selectively deferring instructions issued in program order utilizing a checkpoint and multiple deferral scheme" title="Patent US7114060 - Selectively deferring instructions issued in program order utilizing a checkpoint and multiple deferral scheme"></div><table id="viewport_table" cellpadding="0" style="clear:both" cellspacing="0"><tr><td id="menu_td" class="menu_td"><div id=menu_container><div class=menu id=menu><div class="menu_content" style="margin-bottom:6px"><div id="volume-info-sidebar"><span class="gb-survey-link"></span><h1 class="gb-volume-title" dir=ltr>Selectively deferring instructions issued in program order utilizing a ...</h1>&nbsp;<span class="addmd">Shailender Chaudhry et al</span></div><div style="margin-bottom:4px"><div class=sidebarnav><div class=sidebarcover><a href="http://www.google.com/patents?id=Bdt6AAAAEBAJ&printsec=abstract" ><img src="http://bks9.books.google.com/patents?id=Bdt6AAAAEBAJ&printsec=abstract&img=1&zoom=1&sig=ACfU3U2KQWMN8l9cNEDqEeQ3nfF0z1Ks4w" alt="Abstract" title="Abstract" width=102 border=1 id=summary-frontcover ></a></div><span class=nolink>&rsaquo;&nbsp;Overview</span><br><a href="/patents/US7114060?printsec=abstract&dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">Abstract</a><br><a href="/patents/US7114060?printsec=drawing&dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">Drawings</a><br><a href="/patents/US7114060?printsec=description&dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">Description</a><br><a href="/patents/US7114060?printsec=claims&dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">Claims</a><br><span id="gb-atb-patents-plusone-container"></span></div></div></div><div style="clear:both"></div><div style="margin-left:10px"><form action=/patents id=search_form style="margin:0px;padding:0px;" method=get> <input type=hidden name=ei value="EQj-T5-UOYaI0QGdrvHkBg"><input type=hidden name=id value="Bdt6AAAAEBAJ"><input type=hidden name=dq value="george david zalepa"><table cellpadding=0 cellspacing=0 class="swv-table"><tr><td width="100%" class="swv-td-search"><span><input id=search_form_input type=text maxlength=1024 class="text_flat swv-input-search" name=q value="" title="Go" accesskey=i></span></td><td class="swv-td-space">&nbsp;&nbsp;</td><td><input type=submit value="Go"></td></tr></table><script type="text/javascript">if (window['_OC_autoDir']) {_OC_autoDir('search_form_input');}</script></form></div><div id="menu_scroll"><div id=metadata_content class=menu_content><div id=metadata_v><div class=patent_bibdata><p><b>Patent number</b>: 7114060<br><b>Filing date</b>: Oct 14, 2003<br><b>Issue date</b>: Sep 26, 2006<br><b>Application number</b>:&nbsp;<a href="/patents/US20050081195?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">10/686,061</a><br></p></div></div></div></div></div></div></td><td id="viewport_td"><div class=vertical_module_list_row><div id=overview class=about_content><div id=overview_v><table id="summarytable" cellpadding="0" cellspacing="0" border="0" width="100%"><tr><td valign=top><p class="patent_abstract_text">One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order.</p><div class="patent_bibdata"><b>Inventors</b>:&nbsp;<a href="http://www.google.com/search?tbo=p&amp;tbm=pts&amp;hl=en&amp;q=ininventor:%22Shailender+Chaudhry%22">Shailender Chaudhry</a>, <a href="http://www.google.com/search?tbo=p&amp;tbm=pts&amp;hl=en&amp;q=ininventor:%22Marc+Tremblay%22">Marc Tremblay</a><br><b>Original Assignee</b>:&nbsp;<a href="http://www.google.com/search?tbo=p&amp;tbm=pts&amp;hl=en&amp;q=inassignee:%22Sun+Microsystems,+Inc.%22">Sun Microsystems, Inc.</a><br><b>Primary Examiner</b>:&nbsp;Richard L. Ellis<br><b>Secondary Examiner</b>:&nbsp;George D. Zalepa<br><b>Attorney</b>:&nbsp;Park, Vaughan &amp; Fleming, LLP<br><b>Current U.S. Classification</b>:&nbsp;<a href="http://www.google.com/url?id=Bdt6AAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc712/defs712.htm&amp;usg=AFQjCNFSlkDLYE-yriA4W3Ix_OZ4YREIEw#C712S219000">712/219</a>; <a href="http://www.google.com/url?id=Bdt6AAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc712/defs712.htm&amp;usg=AFQjCNFSlkDLYE-yriA4W3Ix_OZ4YREIEw#C712S215000">712/215</a>; <a href="http://www.google.com/url?id=Bdt6AAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc712/defs712.htm&amp;usg=AFQjCNFSlkDLYE-yriA4W3Ix_OZ4YREIEw#C712S216000">712/216</a>; <a href="http://www.google.com/url?id=Bdt6AAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc712/defs712.htm&amp;usg=AFQjCNFSlkDLYE-yriA4W3Ix_OZ4YREIEw#C712SE09049">712/E09.049</a>; <a href="http://www.google.com/url?id=Bdt6AAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc712/defs712.htm&amp;usg=AFQjCNFSlkDLYE-yriA4W3Ix_OZ4YREIEw#C712SE09050">712/E09.05</a>; <a href="http://www.google.com/url?id=Bdt6AAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc712/defs712.htm&amp;usg=AFQjCNFSlkDLYE-yriA4W3Ix_OZ4YREIEw#C712SE09061">712/E09.061</a><br><br><a href="http://www.google.com/url?id=Bdt6AAAAEBAJ&q=http://patft.uspto.gov/netacgi/nph-Parser%3FSect2%3DPTO1%26Sect2%3DHITOFF%26p%3D1%26u%3D/netahtml/PTO/search-bool.html%26r%3D1%26f%3DG%26l%3D50%26d%3DPALL%26RefSrch%3Dyes%26Query%3DPN/7114060&usg=AFQjCNFUh0h27ILJAr0wdzruZdb9d3lAWg">View patent at USPTO</a><br><a href="http://www.google.com/url?id=Bdt6AAAAEBAJ&q=http://assignments.uspto.gov/assignments/q%3Fdb%3Dpat%26pat%3D7114060&usg=AFQjCNFchLdft0m8yGtBCFwlyWoOHuJxKA">Search USPTO Assignment Database</a><br></div></table></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="patent_citations_anchor"></a>Citations</h3><div id=patent_citations class=about_content><div id=patent_citations_v><table class=rel_patent style="border-spacing:10px 0" cellpadding=4><tr><td class=rel_patent_header><b>Cited Patent</b></td><td class=rel_patent_header><b>Filing date</b></td><td class=rel_patent_header><b>Issue date</b></td><td class=rel_patent_header><b>Original Assignee</b></td><td class="rel_patent_header rel_patent_title"><b>Title</b></td></tr><tr><td valign=top nowrap><a href="/patents/US5471591?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US5471591</a></td><td valign=top nowrap>Oct 30, 1992</td><td valign=top nowrap>Nov 28, 1995</td><td valign=top>Digital Equipment Corporation</td><td class=rel_patent_title valign=top>Combined write-operand queue and read-after-write dependency scoreboard</td></tr><tr><td valign=top nowrap><a href="/patents/US5751985?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US5751985</a></td><td valign=top nowrap>Jun 7, 1995</td><td valign=top nowrap>May 12, 1998</td><td valign=top>Hal Computer Systems, Inc.</td><td class=rel_patent_title valign=top>Processor structure and method for tracking instruction status to maintain precise state </td></tr><tr><td valign=top nowrap><a href="/patents/US5881280?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US5881280</a></td><td valign=top nowrap>Jul 25, 1997</td><td valign=top nowrap>Mar 9, 1999</td><td valign=top>Hewlett-Packard Company</td><td class=rel_patent_title valign=top>Method and system for selecting instructions for re-execution for in-line exception recovery in a speculative execution processor</td></tr><tr><td valign=top nowrap><a href="/patents/US5966530?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US5966530</a></td><td valign=top nowrap>Jun 11, 1997</td><td valign=top nowrap>Oct 12, 1999</td><td valign=top>Fujitsu, Ltd.</td><td class=rel_patent_title valign=top>Structure and method for instruction boundary machine state restoration</td></tr><tr><td valign=top nowrap><a href="/patents/US20010029590?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US20010029590</a></td><td valign=top nowrap>Feb 2, 2001</td><td valign=top nowrap></td><td valign=top>Intel Corporation</td><td class=rel_patent_title valign=top>Processor having execution core sections operating at different clock rates</td></tr></table></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="patent_referenced_by_anchor"></a>Referenced by</h3><div id=patent_referenced_by class=about_content><div id=patent_referenced_by_v><table class=rel_patent style="border-spacing:10px 0" cellpadding=4><tr><td class=rel_patent_header><b>Citing Patent</b></td><td class=rel_patent_header><b>Filing date</b></td><td class=rel_patent_header><b>Issue date</b></td><td class=rel_patent_header><b>Original Assignee</b></td><td class="rel_patent_header rel_patent_title"><b>Title</b></td></tr><tr><td valign=top nowrap><a href="/patents/US7421567?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US7421567</a></td><td valign=top nowrap>Dec 17, 2004</td><td valign=top nowrap>Sep 2, 2008</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Using a modified value GPR to enhance lookahead prefetch</td></tr><tr><td valign=top nowrap><a href="/patents/US7444498?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US7444498</a></td><td valign=top nowrap>Dec 17, 2004</td><td valign=top nowrap>Oct 28, 2008</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Load lookahead prefetch for microprocessors</td></tr><tr><td valign=top nowrap><a href="/patents/US7519775?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US7519775</a></td><td valign=top nowrap>Nov 3, 2006</td><td valign=top nowrap>Apr 14, 2009</td><td valign=top>Sun Microsystems, Inc.</td><td class=rel_patent_title valign=top>Enforcing memory-reference ordering requirements at the L2 cache level</td></tr><tr><td valign=top nowrap><a href="/patents/US7523266?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US7523266</a></td><td valign=top nowrap>Nov 3, 2006</td><td valign=top nowrap>Apr 21, 2009</td><td valign=top>Sun Microsystems, Inc.</td><td class=rel_patent_title valign=top>Method and apparatus for enforcing memory reference ordering requirements at the L1 cache level</td></tr><tr><td valign=top nowrap><a href="/patents/US7552318?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US7552318</a></td><td valign=top nowrap>Dec 17, 2004</td><td valign=top nowrap>Jun 23, 2009</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Branch lookahead prefetch for microprocessors</td></tr><tr><td valign=top nowrap><a href="/patents/US7594096?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US7594096</a></td><td valign=top nowrap>Dec 5, 2007</td><td valign=top nowrap>Sep 22, 2009</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Load lookahead prefetch for microprocessors</td></tr><tr><td valign=top nowrap><a href="/patents/US7620799?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US7620799</a></td><td valign=top nowrap>Apr 2, 2008</td><td valign=top nowrap>Nov 17, 2009</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Using a modified value GPR to enhance lookahead prefetch</td></tr><tr><td valign=top nowrap><a href="/patents/US7650485?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US7650485</a></td><td valign=top nowrap>Apr 10, 2007</td><td valign=top nowrap>Jan 19, 2010</td><td valign=top>Sun Microsystems, Inc.</td><td class=rel_patent_title valign=top>Structure and method for achieving very large lookahead instruction window via non-sequential instruction fetch and issue</td></tr><tr><td valign=top nowrap><a href="/patents/US7747841?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US7747841</a></td><td valign=top nowrap>Sep 26, 2006</td><td valign=top nowrap>Jun 29, 2010</td><td valign=top>Cornell Research Foundation, Inc.</td><td class=rel_patent_title valign=top>Method and apparatus for early load retirement in a processor system</td></tr><tr><td valign=top nowrap><a href="/patents/US7877580?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US7877580</a></td><td valign=top nowrap>Dec 10, 2007</td><td valign=top nowrap>Jan 25, 2011</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Branch lookahead prefetch for microprocessors</td></tr></table></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="patent_claims_anchor"></a>Claims</h3><div id=patent_claims class=about_content><div id=patent_claims_v><p>1. A method for deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order, comprising:<p><dl><dd style="margin-left:1em;">issuing instructions for execution in program order during a normal execution mode; and</dd></dl><p><dl><dd style="margin-left:1em;">upon encountering an unresolved data dependency during execution of an instruction,</dd><dd style="margin-left:1em;"><dl><dd style="margin-left:1em;">generating a checkpoint that can subsequently be used to return execution of the program to the point of the instruction, and</dd></dl></dd><dd style="margin-left:1em;"><dl><dd style="margin-left:1em;">executing subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order;</dd><dd style="margin-left:1em;">wherein if a non-data-dependent stall condition is encountered while executing in normal mode or execute-ahead mode, the method further comprises;</dd><dd style="margin-left:1em;">moving to a scout mode, wherein instructions are speculatively executed to prefetch future loads, but wherein results are not committed to the architectural state of the processor; and</dd><dd style="margin-left:1em;">when the launch point stall condition (the unresolved data dependency or the non-data dependent stall condition that originally caused the system to move out of normal execution mode) is finally resolved, using the checkpoint to resume execution in normal mode from the launch point instruction (the instruction that originally encountered the launch point stall condition).</dd></dl></dd></dl><p>2. The method of claim 1, wherein if the unresolved data dependency is resolved during execute-ahead mode, the method further comprises:<p><dl><dd style="margin-left:1em;">executing deferred instructions in a deferred execution mode; and</dd></dl><p><dl><dd style="margin-left:1em;">if all deferred instructions are executed, returning to the normal execution mode to resume normal program execution from the point where the execute-ahead mode left off.</dd></dl><p>3. The method of claim 2, wherein executing deferred instructions in the deferred execution mode involves:<p><dl><dd style="margin-left:1em;">issuing deferred instructions for execution in program order;</dd></dl><p><dl><dd style="margin-left:1em;">deferring execution of deferred instructions that still cannot be executed because of unresolved data dependencies; and</dd></dl><p><dl><dd style="margin-left:1em;">executing other deferred instructions that are able to be executed in program order.</dd></dl><p>4. The method of claim 3, wherein if some deferred instruction are deferred again, the method further comprises returning to execute-ahead mode at the point where execute-ahead mode left off.<p>5. The method of claim 2, wherein generating the checkpoint involves saving a precise architectural state of the processor to facilitate subsequent recovery from exceptions that arise during execute-ahead mode or deferred mode.<p>6. The method of claim 1, wherein executing instructions involves keeping track of data dependencies to facilitate determining if an instruction is subject to an unresolved data dependency.<p>7. The method of claim 6, wherein keeping track of data dependencies involves maintaining state information for each register, which indicates whether or not a value in the register depends on an unresolved data-dependency.<p>8. The method of claim 1, wherein the unresolved data dependency can include:<p><dl><dd style="margin-left:1em;">a use of an operand that has not returned from a preceding load miss;</dd></dl><p><dl><dd style="margin-left:1em;">a use of an operand that has not returned from a preceding translation lookaside buffer (TLB) miss;</dd></dl><p><dl><dd style="margin-left:1em;">a use of an operand that has not returned from a preceding full or partial read-after-write (RAW) from store buffer operation; and</dd></dl><p><dl><dd style="margin-left:1em;">a use of an operand that depends on another operand that is subject to an unresolved data dependency.</dd></dl><p>9. The method of claim 1, wherein the non-data-dependant stall condition can include:<p><dl><dd style="margin-left:1em;">a memory barrier operation;</dd></dl><p><dl><dd style="margin-left:1em;">a load buffer full condition; and</dd></dl><p><dl><dd style="margin-left:1em;">a store buffer full condition.</dd></dl><p>10. The method of claim 1, wherein deferring instructions involves storing instructions in a deferred buffer that is organized as a first-in first-out buffer.<p>11. The method of claim 1, wherein issuing instructions for execution in program order involves issuing instructions from an instruction buffer that is organized as a first-in first-out buffer.<p>12. An apparatus that defers execution of instructions with unresolved data dependencies as they are issued for execution in program order, comprising:<p><dl><dd style="margin-left:1em;">an execution mechanism configured to issue instructions for execution in program order during a normal execution mode;</dd></dl><p><dl><dd style="margin-left:1em;">a detection mechanism configured to detect an unresolved data dependency;</dd></dl><p><dl><dd style="margin-left:1em;">wherein if an unresolved data dependency is detected during execution of an instruction, the execution mechanism is configured to,</dd><dd style="margin-left:1em;"><dl><dd style="margin-left:1em;">generate a checkpoint that can subsequently be used to return execution of the program to the point of the instruction, and to</dd><dd style="margin-left:1em;">execute subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order;</dd><dd style="margin-left:1em;">wherein if a non-data-dependent stall condition is encountered while executing in normal mode or execute-ahead mode, the execution mechanism is configured to move into a scout mode;</dd><dd style="margin-left:1em;">wherein during scout mode instructions are speculatively executed to prefetch future loads, but results are not committed to the architectural state of the processor; and</dd><dd style="margin-left:1em;">wherein during scout mode when the launch point stall condition (the unresolved data dependency or the non-data dependent stall condition that originally caused the system to move out of normal execution mode) is finally resolved, the checkpoint is used to resume execution in normal mode from the launch point instruction (the instruction that originally encountered the launch point stall condition).</dd></dl></dd></dl><p>13. The apparatus of claim 12,<p><dl><dd style="margin-left:1em;">wherein if the unresolved data dependency is resolved during execute-ahead mode, the execution mechanism is configured to execute deferred instructions in a deferred execution mode; and</dd></dl><p><dl><dd style="margin-left:1em;">wherein if all deferred instructions are executed during deferred execution mode, the execution mechanism is configured to return to normal execution mode to resume normal program execution from the point where the execute-ahead mode left off.</dd></dl><p>14. The apparatus of claim 13, wherein while executing deferred instructions in the deferred execution mode, the execution mechanism is configured to:<p><dl><dd style="margin-left:1em;">issue deferred instructions for execution in program order;</dd></dl><p><dl><dd style="margin-left:1em;">defer execution of deferred instructions that still cannot be executed because of unresolved data dependencies; and to</dd></dl><p><dl><dd style="margin-left:1em;">execute other deferred instructions that are able to be executed in program order.</dd></dl><p>15. The apparatus of claim 14, wherein if some deferred instruction are deferred again, the execution mechanism is configured to return to execute-ahead mode at the point where execute-ahead mode left off.<p>16. The apparatus of claim 13, wherein while generating the checkpoint, the execution mechanism is configured to save a precise architectural state of the processor to facilitate subsequent recovery from exceptions that arise during execute-ahead mode or deferred mode.<p>17. The apparatus of claim 12, wherein the execution mechanism is configured to keep track of data dependencies to facilitate determining if an instruction is subject to an unresolved data dependency.<p>18. The apparatus of claim 17, wherein while keeping track of data dependencies, the execution mechanism is configured to maintaining state information for each register, which indicates whether or not a value in the register depends on an unresolved data-dependency.<p>19. The apparatus of claim 12, wherein the unresolved data dependency can include:<p><dl><dd style="margin-left:1em;">a use of an operand that has not returned from a preceding load miss;</dd></dl><p><dl><dd style="margin-left:1em;">a use of an operand that has not returned from a preceding translation lookaside buffer (TLB) miss;</dd></dl><p><dl><dd style="margin-left:1em;">a use of an operand that has not returned from a preceding full or partial read-after-write (RAW) from store buffer operation; and</dd></dl><p><dl><dd style="margin-left:1em;">a use of an operand that depends on another operand that is subject to an unresolved data dependency.</dd></dl><p>20. The apparatus of claim 12, wherein the non-data-dependent stall condition can include:<p><dl><dd style="margin-left:1em;">a memory barrier operation;</dd></dl><p><dl><dd style="margin-left:1em;">a load buffer full condition; and</dd></dl><p><dl><dd style="margin-left:1em;">a store buffer full condition.</dd></dl><p>21. The apparatus of claim 12, further comprising a deferred buffer for storing deferred instructions, wherein the deferred buffer is organized as a first-in first-out buffer.<p>22. The apparatus of claim 12, further comprising an instruction buffer for storing instructions to be issued for execution in program order, wherein the instruction buffer is organized as a first-in first-out buffer.<p>23. A microprocessor that defers execution of instructions with unresolved data dependencies as they are issued for execution in program order, comprising:<p><dl><dd style="margin-left:1em;">a microprocessor chip containing one or more microprocessor cores;</dd></dl><p><dl><dd style="margin-left:1em;">an execution mechanism within a microprocessor core configured to issue instructions for execution in program order during a normal execution mode;</dd></dl><p><dl><dd style="margin-left:1em;">a detection mechanism within the microprocessor core configured to detect an unresolved data dependency during execution of an instruction;</dd></dl><p><dl><dd style="margin-left:1em;">wherein if an unresolved data dependency is detected during execution of an instruction, the execution mechanism is configured to,</dd><dd style="margin-left:1em;">generate a checkpoint that can subsequently be used to return execution of the program to the point of the instruction, and to</dd><dd style="margin-left:1em;">execute subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order;</dd><dd style="margin-left:1em;">wherein if a non-data-dependent stall condition is encountered while executing in normal mode or execute-ahead mode, the execution mechanism is configured to move into a scout mode;</dd><dd style="margin-left:1em;">wherein during scout mode instructions are speculatively executed to prefetch future loads, but results are not committed to the architectural state of the processor; and</dd><dd style="margin-left:1em;">wherein during scout mode when the launch point stall condition (the unresolved data dependency or the non-data dependent stall condition that originally caused the system to move out of normal execution mode) is finally resolved, the checkpoint is used to resume execution in normal mode from the launch point instruction (the instruction that originally encountered the launch point stall condition).</dd></dl></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="selected_pages_anchor"></a>Drawings</h3><div id=selected_pages class=about_content><div id=selected_pages_v><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=Bdt6AAAAEBAJ&pg=PA2&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" ><img src="http://bks9.books.google.com/patents?id=Bdt6AAAAEBAJ&amp;pg=PA2&amp;img=1&amp;zoom=1&amp;sig=ACfU3U0ynsc7TUbPIdbUCR-bwke8IwiKLA" alt="Drawings" title="Drawings" height="160" border="1"></a><br/><a class="primary" href="http://www.google.com/patents?id=Bdt6AAAAEBAJ&pg=PA2&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" >Drawings</a></div><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=Bdt6AAAAEBAJ&pg=PA3&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" ><img src="http://bks9.books.google.com/patents?id=Bdt6AAAAEBAJ&amp;pg=PA3&amp;img=1&amp;zoom=1&amp;sig=ACfU3U38SeZJNkKKS4tPxl25LYFdqzlbTg" alt="Drawings" title="Drawings" height="160" border="1"></a><br/><a class="primary" href="http://www.google.com/patents?id=Bdt6AAAAEBAJ&pg=PA3&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" >Drawings</a></div><div style="clear:both;"></div></div></div></div></td></tr></table><script type="text/javascript">_OC_addFlags({LockSrc:"/books/javascript/lock_b9ee852b3231a450c67d122471b67ac7.js", IsWebstoreDisplayCaseEnabled:1, IsObfuscationEnabled:1, IsBrowsingHistoryEnabled:1, IsGeoLayerEnabled:0, IsGiftingEnabled:0, IsOfflineBubbleEnabled:1, IsReaderEnabledForPlayRequests:1, IsUnifiedHovercardEnabled:1, IsFutureOnSaleVolumesEnabled:1, IsBooksUnifiedLeftNavEnabled:1, IsZipitFolderCollectionEnabled:1, IsRatingsOnBookcardsEnabled:1, IsEmbeddedMediaEnabled:1, IsImageModeAnnotationsEnabled:0, IsMyLibraryGooglePlusEnabled:1, IsBookcardListPriceSmall:0, IsBooksShareButtonEnabled:0, IsPreOrdersEnabled:1, IsDisabledRandomBookshelves:0, WebstoreDisplayCasePosition:3});_OC_addMsgs();_OC_Run({"enable_p13n":false,"add_vol_to_collection_base_url":"http://www.google.com/patents?op=add\u0026sig=ACfU3U2NR9gLbaUjBBmf3hRNvlVxNGjPdw\u0026id=Bdt6AAAAEBAJ","remove_vol_from_collection_base_url":"http://www.google.com/patents?op=remove\u0026sig=ACfU3U1ASqT0009jj4tQlE1VzGgKmai3sA\u0026id=Bdt6AAAAEBAJ","logged_in":true,"p13n_save_user_settings_url":"http://www.google.com/patents?op=edit_user_settings\u0026sig=ACfU3U1csLrPRWWF41pcqYdLt6glRm7l_A","is_cobrand":false,"is_play_enabled":true}, {"volume_id":"","is_ebook":true,"volumeresult":{"has_flowing_text":false,"has_scanned_text":true,"can_download_pdf":false,"can_download_epub":false,"is_pdf_drm_enabled":false,"is_epub_drm_enabled":false,"download_pdf_url":"http://www.google.com/patents/download/7114060_Selectively_deferring_instructio.pdf?id=Bdt6AAAAEBAJ\u0026output=pdf\u0026sig=ACfU3U1uFWgnYYRGLojtRo-tN5qpSugHRA"},"sample_url":"http://www.google.com/patents/reader?id=Bdt6AAAAEBAJ\u0026printsec=frontcover\u0026output=reader\u0026source=gbs_atb_hover","is_browsable":true,"is_public_domain":true}, {});</script><div id="footer_table" style="font-size:83%;text-align:center;position:relative;top:20px;height:4.5em;margin-top:2em"><div style="margin-bottom:8px"><a href=http://www.google.com/><nobr>Google&nbsp;Home</nobr></a> - <a href=http://www.google.com/googlebooks/uspto.html><nobr>USPTO Bulk Downloads</nobr></a> - <a href=https://www.google.com/intl/en/privacy/><nobr>Privacy Policy</nobr></a> - <a href=https://www.google.com/accounts/TOS><nobr>Terms of Service</nobr></a> - <a href=/googlepatents/about.html><nobr>About Google Patents</nobr></a> - <a href=/googlepatents/help.html><nobr><nobr>Google Patents Help</nobr></nobr></a> - <a href="http://www.google.com/tools/feedback/intl/en/error.html" onclick="try{_OC_startFeedback({productId: '72792',locale: 'en'});return false;}catch(e){}"><nobr>Send Feedback</nobr></a></div><span >&copy;2012 Google</span></div> <script type="text/javascript">var gaJsHost = (("https:" == document.location.protocol) ? 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id="appbar-download-pdf-link" href="/patents/US7130991.pdf"></a></div><div class="kd-buttonbar right" id="right-toolbar-buttons"></div></div><div id="books-microdata" itemscope=""itemtype="http://schema.org/Book"itemid="http://www.google.com/patents/US7130991" style="display:none"><span itemprop="description">A method and apparatus for loop detection for improved branch prediction accuracy. In one embodiment, the method may comprise executing a branch instruction, updating a plurality of event counts corresponding to the branch instruction in response to its executing, determining a loop behavior status corresponding...</span><span itemprop="url">http://www.google.com/patents/US7130991?utm_source=gb-gplus-share</span><span class="main-title" itemprop="name">Patent US7130991 - Method and apparatus for loop detection utilizing multiple loop counters and a branch promotion scheme</span><img itemprop="image" src="http://www.google.com/patents?id=10Z7AAAAEBAJ&amp;printsec=frontcover&amp;img=1&amp;zoom=1"alt="Patent US7130991 - Method and apparatus for loop detection utilizing multiple loop counters and a branch promotion scheme" title="Patent US7130991 - Method and apparatus for loop detection utilizing multiple loop counters and a branch promotion scheme"></div><table id="viewport_table" cellpadding="0" style="clear:both" cellspacing="0"><tr><td id="menu_td" class="menu_td"><div id=menu_container><div class=menu id=menu><div class="menu_content" style="margin-bottom:6px"><div id="volume-info-sidebar"><span class="gb-survey-link"></span><h1 class="gb-volume-title" dir=ltr>Method and apparatus for loop detection utilizing multiple loop counters and ...</h1>&nbsp;<span class="addmd">Michael G. Butler</span></div><div style="margin-bottom:4px"><div class=sidebarnav><div class=sidebarcover><a href="http://www.google.com/patents?id=10Z7AAAAEBAJ&printsec=abstract" ><img src="http://bks0.books.google.com/patents?id=10Z7AAAAEBAJ&printsec=abstract&img=1&zoom=1&sig=ACfU3U2JmQXMbtgLT9zS53YeHGvbJ9vRvg" alt="Abstract" title="Abstract" width=102 border=1 id=summary-frontcover ></a></div><span class=nolink>&rsaquo;&nbsp;Overview</span><br><a href="/patents/US7130991?printsec=abstract&dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">Abstract</a><br><a href="/patents/US7130991?printsec=drawing&dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">Drawings</a><br><a href="/patents/US7130991?printsec=description&dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">Description</a><br><a href="/patents/US7130991?printsec=claims&dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">Claims</a><br><span id="gb-atb-patents-plusone-container"></span></div></div></div><div style="clear:both"></div><div style="margin-left:10px"><form action=/patents id=search_form style="margin:0px;padding:0px;" method=get> <input type=hidden name=ei value="EQj-T5-UOYaI0QGdrvHkBg"><input type=hidden name=id value="10Z7AAAAEBAJ"><input type=hidden name=dq value="george david zalepa"><table cellpadding=0 cellspacing=0 class="swv-table"><tr><td width="100%" class="swv-td-search"><span><input id=search_form_input type=text maxlength=1024 class="text_flat swv-input-search" name=q value="" title="Go" accesskey=i></span></td><td class="swv-td-space">&nbsp;&nbsp;</td><td><input type=submit value="Go"></td></tr></table><script type="text/javascript">if (window['_OC_autoDir']) {_OC_autoDir('search_form_input');}</script></form></div><div id="menu_scroll"><div id=metadata_content class=menu_content><div id=metadata_v><div class=patent_bibdata><p><b>Patent number</b>: 7130991<br><b>Filing date</b>: Oct 9, 2003<br><b>Issue date</b>: Oct 31, 2006<br><b>Application number</b>:&nbsp;10/682,551<br></p></div></div></div></div></div></div></td><td id="viewport_td"><div class=vertical_module_list_row><div id=overview class=about_content><div id=overview_v><table id="summarytable" cellpadding="0" cellspacing="0" border="0" width="100%"><tr><td valign=top><p class="patent_abstract_text">A method and apparatus for loop detection for improved branch prediction accuracy. In one embodiment, the method may comprise executing a branch instruction, updating a plurality of event counts corresponding to the branch instruction in response to its executing, determining a loop behavior status corresponding to the branch instruction in response to the event count updating, and promoting the branch instruction to a loop branch prediction type in response to the determination of loop behavior status.</p><div class="patent_bibdata"><b>Inventor</b>:&nbsp;<a href="http://www.google.com/search?tbo=p&amp;tbm=pts&amp;hl=en&amp;q=ininventor:%22Michael+G.+Butler%22">Michael G. Butler</a><br><b>Original Assignee</b>:&nbsp;<a href="http://www.google.com/search?tbo=p&amp;tbm=pts&amp;hl=en&amp;q=inassignee:%22Advanced+Micro+Devices,+Inc.%22">Advanced Micro Devices, Inc.</a><br><b>Primary Examiner</b>:&nbsp;Eddie Chan<br><b>Secondary Examiner</b>:&nbsp;George D. Zalepa<br><b>Attorneys</b>:&nbsp;Meyertons Hood Kivlin Kowert &amp; Goetzel, P.C., B. Noël Kivlin<br><b>Current U.S. Classification</b>:&nbsp;<a href="http://www.google.com/url?id=10Z7AAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc712/defs712.htm&amp;usg=AFQjCNFSlkDLYE-yriA4W3Ix_OZ4YREIEw#C712S241000">712/241</a>; <a href="http://www.google.com/url?id=10Z7AAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc712/defs712.htm&amp;usg=AFQjCNFSlkDLYE-yriA4W3Ix_OZ4YREIEw#C712S233000">712/233</a>; <a href="http://www.google.com/url?id=10Z7AAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc712/defs712.htm&amp;usg=AFQjCNFSlkDLYE-yriA4W3Ix_OZ4YREIEw#C712S239000">712/239</a>; <a href="http://www.google.com/url?id=10Z7AAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc712/defs712.htm&amp;usg=AFQjCNFSlkDLYE-yriA4W3Ix_OZ4YREIEw#C712SE09051">712/E09.051</a>; <a href="http://www.google.com/url?id=10Z7AAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc712/defs712.htm&amp;usg=AFQjCNFSlkDLYE-yriA4W3Ix_OZ4YREIEw#C712SE09078">712/E09.078</a><br><br><a href="http://www.google.com/url?id=10Z7AAAAEBAJ&q=http://patft.uspto.gov/netacgi/nph-Parser%3FSect2%3DPTO1%26Sect2%3DHITOFF%26p%3D1%26u%3D/netahtml/PTO/search-bool.html%26r%3D1%26f%3DG%26l%3D50%26d%3DPALL%26RefSrch%3Dyes%26Query%3DPN/7130991&usg=AFQjCNHS5xN1Wmle2G4yJvv8NLgzuveDBA">View patent at USPTO</a><br><a href="http://www.google.com/url?id=10Z7AAAAEBAJ&q=http://assignments.uspto.gov/assignments/q%3Fdb%3Dpat%26pat%3D7130991&usg=AFQjCNFi-Yu4TH8lzHBVRrxUfXxrP7TH9A">Search USPTO Assignment Database</a><br></div></table></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="patent_citations_anchor"></a>Citations</h3><div id=patent_citations class=about_content><div id=patent_citations_v><table class=rel_patent style="border-spacing:10px 0" cellpadding=4><tr><td class=rel_patent_header><b>Cited Patent</b></td><td class=rel_patent_header><b>Filing date</b></td><td class=rel_patent_header><b>Issue date</b></td><td class=rel_patent_header><b>Original Assignee</b></td><td class="rel_patent_header rel_patent_title"><b>Title</b></td></tr><tr><td valign=top nowrap><a href="/patents/US5574672?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US5574672</a></td><td valign=top nowrap>Oct 21, 1994</td><td valign=top nowrap>Nov 12, 1996</td><td valign=top>Cyrix Corporation</td><td class=rel_patent_title valign=top>Combination multiplier/shifter</td></tr><tr><td valign=top nowrap><a href="/patents/US5909573?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US5909573</a></td><td valign=top nowrap>Mar 28, 1996</td><td valign=top nowrap>Jun 1, 1999</td><td valign=top>Intel Corporation</td><td class=rel_patent_title valign=top>Method of branch prediction using loop counters</td></tr><tr><td valign=top nowrap><a href="/patents/US6003128?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US6003128</a></td><td valign=top nowrap>May 1, 1997</td><td valign=top nowrap>Dec 14, 1999</td><td valign=top>Advanced Micro Devices, Inc.</td><td class=rel_patent_title valign=top>Number of pipeline stages and loop length related counter differential based end-loop prediction</td></tr><tr><td valign=top nowrap><a href="/patents/US6385720?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US6385720</a></td><td valign=top nowrap>Jul 13, 1998</td><td valign=top nowrap>May 7, 2002</td><td valign=top>Matsushita Electric Industrial Co., Ltd.</td><td class=rel_patent_title valign=top>Branch prediction method and processor using origin information, relative position information and history information</td></tr><tr><td valign=top nowrap><a href="/patents/US20040123075?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US20040123075</a></td><td valign=top nowrap>Dec 19, 2002</td><td valign=top nowrap></td><td valign=top></td><td class=rel_patent_title valign=top>Extended loop prediction techniques</td></tr></table></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="patent_referenced_by_anchor"></a>Referenced by</h3><div id=patent_referenced_by class=about_content><div id=patent_referenced_by_v><table class=rel_patent style="border-spacing:10px 0" cellpadding=4><tr><td class=rel_patent_header><b>Citing Patent</b></td><td class=rel_patent_header><b>Filing date</b></td><td class=rel_patent_header><b>Issue date</b></td><td class=rel_patent_header><b>Original Assignee</b></td><td class="rel_patent_header rel_patent_title"><b>Title</b></td></tr><tr><td valign=top nowrap><a href="/patents/US8028180?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US8028180</a></td><td valign=top nowrap>Feb 20, 2008</td><td valign=top nowrap>Sep 27, 2011</td><td valign=top>International Business Machines Corporation</td><td class=rel_patent_title valign=top>Method and system for power conservation in a hierarchical branch predictor</td></tr><tr><td valign=top nowrap><a href="/patents/US8099586?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US8099586</a></td><td valign=top nowrap>Dec 30, 2008</td><td valign=top nowrap>Jan 17, 2012</td><td valign=top>Oracle America, Inc.</td><td class=rel_patent_title valign=top>Branch misprediction recovery mechanism for microprocessors</td></tr></table></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="patent_claims_anchor"></a>Claims</h3><div id=patent_claims class=about_content><div id=patent_claims_v><p>1. A method comprising:<p><dl><dd style="margin-left:1em;">executing a branch instruction;</dd></dl><p><dl><dd style="margin-left:1em;">updating a plurality of event counts corresponding to said branch instruction in response to said executing;</dd></dl><p><dl><dd style="margin-left:1em;">determining a loop behavior status corresponding to said branch instruction in response to said updating; and</dd></dl><p><dl><dd style="margin-left:1em;">promoting said branch instruction to a loop branch prediction type in response to said determining a loop behavior status;</dd><dd style="margin-left:1em;">wherein said plurality of event counts comprises a branch execution count, a branch taken count, and a branch transition count; and</dd><dd style="margin-left:1em;">wherein said determining a loop behavior status comprises detecting the relationship Cexec=Ctaken+ceil(Ctransition/2) in response to a branch misprediction, wherein Cexec corresponds to said branch execution count, Ctaken corresponds to said branch taken count, and Ctransition corresponds to said branch transition count, and wherein ceil(N) specifies a smallest integer greater than or equal to N.</dd></dl><p>2. The method as recited in claim 1, further comprising:<p><dl><dd style="margin-left:1em;">determining a non-loop behavior status corresponding to said branch instruction in response to said promoting; and</dd></dl><p><dl><dd style="margin-left:1em;">demoting said branch instruction to a non-loop branch prediction type in response to said determining a non-loop behavior status.</dd></dl><p>3. The method as recited in claim 1, wherein said promoting comprises:<p><dl><dd style="margin-left:1em;">clearing said branch execution count;</dd></dl><p><dl><dd style="margin-left:1em;">computing a loop period value; and</dd></dl><p><dl><dd style="margin-left:1em;">storing said loop period value.</dd></dl><p>4. The method as recited in claim 3, further comprising:<p><dl><dd style="margin-left:1em;">incrementing said branch execution count in response to an execution of said branch instruction;</dd></dl><p><dl><dd style="margin-left:1em;">comparing said branch execution count to said stored loop period value; and</dd></dl><p><dl><dd style="margin-left:1em;">predicting a final loop iteration in response to said comparing.</dd></dl><p>5. The method as recited in claim 2, wherein said determining a non-loop behavior status comprises detecting a branch misprediction.<p>6. The method as recited in claim 2, wherein said demoting comprises selecting a non-loop branch prediction technique corresponding to said branch instruction.<p>7. The method as recited in claim 1, further comprising:<p><dl><dd style="margin-left:1em;">detecting an overflow of said branch execution count; and</dd></dl><p><dl><dd style="margin-left:1em;">dividing each of said branch execution count, said branch taken count, and said branch transition count by a given value in response to said detecting an overflow.</dd></dl><p>8. The method as recited in claim 7, wherein each of said branch execution count, said branch taken count, and said branch transition count is represented as a binary number, and wherein said dividing comprises a logical right shift operation by one or more binary digit positions.<p>9. A branch processing unit comprising:<p><dl><dd style="margin-left:1em;">a plurality of event counters corresponding to a branch instruction and configured to be updated in response to execution of said branch instruction; and</dd></dl><p><dl><dd style="margin-left:1em;">branch control logic coupled to said plurality of event counters, wherein said branch control logic is configured to determine a loop behavior status corresponding to said branch instruction in response to said updating and further configured to promote said branch instruction to a loop branch prediction type in response to said determining a loop behavior status;</dd></dl><p><dl><dd style="margin-left:1em;">wherein said plurality of event counters comprises a branch execution counter, a branch taken counter, and a branch transition counter, each configured to store a respective value; and</dd></dl><p><dl><dd style="margin-left:1em;">wherein to determine said loop behavior status, said branch control logic is further configured to detect the relationship Cexec=Ctaken+ceil(Ctransition/2) in response to a branch misprediction, wherein Cexec corresponds to a value stored in said branch execution counter, Ctaken corresponds to a value stored in said branch taken counter, and Ctransition corresponds to a value stored in said branch transition counter, and wherein ceil(N) specifies a smallest integer greater than or equal to N.</dd></dl><p>10. The branch processing unit as recited in claim 9, wherein said branch control logic is further configured to determine a non-loop behavior status corresponding to said branch instruction in response to said promoting and to demote said branch instruction to a non-loop branch prediction type in response to said determining a non-loop behavior status.<p>11. The branch processing unit as recited in claim 9, wherein to promote said branch instruction, said branch control logic is further configured to:<p><dl><dd style="margin-left:1em;">clear said branch execution counter;</dd></dl><p><dl><dd style="margin-left:1em;">clear a loop period value; and</dd></dl><p><dl><dd style="margin-left:1em;">store said loop period value in one of said branch taken counter or said branch transition counter.</dd></dl><p>12. The branch processing unit as recited in claim 11,<p><dl><dd style="margin-left:1em;">wherein said branch execution counter is configured to increment in response to an execution of said branch instruction; and</dd></dl><p><dl><dd style="margin-left:1em;">wherein said branch control logic is configured to compare a value stored in said branch execution counter to said stored loop period value and to predict a final loop iteration in response to said comparing.</dd></dl><p>13. The branch processing unit as recited in claim 10, wherein to determine a non-loop behavior status, said branch control logic is further configured to detect a branch misprediction.<p>14. The branch processing unit as recited in claim 10, wherein to demote said branch instruction, said branch control logic is further configured to select a non-loop branch prediction technique corresponding to said branch instruction.<p>15. The branch processing unit as recited in claim 9, wherein said branch execution counter is further configured to detect an overflow, and wherein each of said branch execution counter, said branch taken counter, and said branch transition counter is configured to divide said respective stored value by a given value in response to said detecting an overflow.<p>16. The branch processing unit as recited in claim 15, wherein each said respective stored value comprises a binary number, and wherein said dividing comprises a logical right shift operation by one or more binary digit positions.<p>17. A microprocessor comprising:<p><dl><dd style="margin-left:1em;">an execution unit configured to execute instructions; and</dd></dl><p><dl><dd style="margin-left:1em;">a branch processing unit coupled to said execution unit and configured to:</dd><dd style="margin-left:1em;"><dl><dd style="margin-left:1em;">update a plurality of event counts corresponding to a branch instruction in response to execution of said branch instruction;</dd></dl></dd><dd style="margin-left:1em;"><dl><dd style="margin-left:1em;">determine a loop behavior status corresponding to said branch instruction in response to said updating; and</dd><dd style="margin-left:1em;">promote said branch instruction to a loop branch prediction type in response to said determining a loop behavior status;</dd><dd style="margin-left:1em;">wherein said plurality of event counts comprises a branch execution count, a branch taken count, and a branch transition count, and</dd><dd style="margin-left:1em;">wherein to determine said loop behavior status, said branch prediction unit is further configured to detect the relationship Cexec=Ctaken+ceil(Ctransition/2) in response to a branch misprediction, wherein Cexec corresponds to said branch execution count, Ctaken corresponds to said branch taken count, and Ctransition corresponds to said branch transition count, and wherein ceil(N) specifies a smallest integer greater than or equal to N.</dd></dl></dd></dl><p>18. The microprocessor as recited in claim 17, wherein said branch prediction unit is further configured to:<p><dl><dd style="margin-left:1em;">determine a non-loop behavior status corresponding to said branch instruction in response to said promoting; and</dd></dl><p><dl><dd style="margin-left:1em;">demote said branch instruction to a non-loop branch prediction type in response to said determining a non-loop behavior status.</dd></dl><p>19. The microprocessor as recited in claim 17, wherein to promote said branch instruction, said branch prediction unit is further configured to:<p><dl><dd style="margin-left:1em;">clear said branch execution count;</dd></dl><p><dl><dd style="margin-left:1em;">compute a loop period value; and</dd></dl><p><dl><dd style="margin-left:1em;">store said loop period value.</dd></dl><p>20. The microprocessor as recited in claim 19, wherein said branch prediction unit is further configured to:<p><dl><dd style="margin-left:1em;">increment said branch execution count in response to an execution of said branch instruction;</dd></dl><p><dl><dd style="margin-left:1em;">compare said branch execution count to said stored loop period value; and</dd></dl><p><dl><dd style="margin-left:1em;">predict a final loop iteration in response to said comparing.</dd></dl></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="selected_pages_anchor"></a>Drawings</h3><div id=selected_pages class=about_content><div id=selected_pages_v><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=10Z7AAAAEBAJ&pg=PA2&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" ><img src="http://bks0.books.google.com/patents?id=10Z7AAAAEBAJ&amp;pg=PA2&amp;img=1&amp;zoom=1&amp;sig=ACfU3U1YOgbvRYxNdRLsS_5nxxD5W-dydA" alt="Drawings" title="Drawings" height="160" border="1"></a><br/><a class="primary" href="http://www.google.com/patents?id=10Z7AAAAEBAJ&pg=PA2&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" >Drawings</a></div><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=10Z7AAAAEBAJ&pg=PA3&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" ><img src="http://bks0.books.google.com/patents?id=10Z7AAAAEBAJ&amp;pg=PA3&amp;img=1&amp;zoom=1&amp;sig=ACfU3U28A9P32nFLgROxUTPe8aaouooVAA" alt="Drawings" title="Drawings" height="160" border="1"></a><br/><a class="primary" href="http://www.google.com/patents?id=10Z7AAAAEBAJ&pg=PA3&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" >Drawings</a></div><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=10Z7AAAAEBAJ&pg=PA4&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" ><img src="http://bks0.books.google.com/patents?id=10Z7AAAAEBAJ&amp;pg=PA4&amp;img=1&amp;zoom=1&amp;sig=ACfU3U1Os0McvDfk_r1BUHSXQht36pV2fA" alt="Drawings" title="Drawings" height="160" border="1"></a><br/><a class="primary" href="http://www.google.com/patents?id=10Z7AAAAEBAJ&pg=PA4&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" >Drawings</a></div><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=10Z7AAAAEBAJ&pg=PA5&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" ><img src="http://bks0.books.google.com/patents?id=10Z7AAAAEBAJ&amp;pg=PA5&amp;img=1&amp;zoom=1&amp;sig=ACfU3U2IXYn-qWcEIY2FuYWUwNo21IQe2A" alt="Drawings" title="Drawings" height="160" border="1"></a><br/><a class="primary" href="http://www.google.com/patents?id=10Z7AAAAEBAJ&pg=PA5&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" >Drawings</a></div><div style="clear:both;"></div></div></div></div></td></tr></table><script type="text/javascript">_OC_addFlags({LockSrc:"/books/javascript/lock_b9ee852b3231a450c67d122471b67ac7.js", IsWebstoreDisplayCaseEnabled:1, IsObfuscationEnabled:1, IsBrowsingHistoryEnabled:1, IsGeoLayerEnabled:0, IsGiftingEnabled:0, IsOfflineBubbleEnabled:1, IsReaderEnabledForPlayRequests:1, IsUnifiedHovercardEnabled:1, IsFutureOnSaleVolumesEnabled:1, IsBooksUnifiedLeftNavEnabled:1, IsZipitFolderCollectionEnabled:1, IsRatingsOnBookcardsEnabled:1, IsEmbeddedMediaEnabled:1, IsImageModeAnnotationsEnabled:0, IsMyLibraryGooglePlusEnabled:1, IsBookcardListPriceSmall:0, IsBooksShareButtonEnabled:0, IsPreOrdersEnabled:1, IsDisabledRandomBookshelves:0, WebstoreDisplayCasePosition:3});_OC_addMsgs();_OC_Run({"enable_p13n":false,"add_vol_to_collection_base_url":"http://www.google.com/patents?op=add\u0026sig=ACfU3U2NR9gLbaUjBBmf3hRNvlVxNGjPdw\u0026id=10Z7AAAAEBAJ","remove_vol_from_collection_base_url":"http://www.google.com/patents?op=remove\u0026sig=ACfU3U1ASqT0009jj4tQlE1VzGgKmai3sA\u0026id=10Z7AAAAEBAJ","logged_in":true,"p13n_save_user_settings_url":"http://www.google.com/patents?op=edit_user_settings\u0026sig=ACfU3U1csLrPRWWF41pcqYdLt6glRm7l_A","is_cobrand":false,"is_play_enabled":true}, {"volume_id":"","is_ebook":true,"volumeresult":{"has_flowing_text":false,"has_scanned_text":true,"can_download_pdf":false,"can_download_epub":false,"is_pdf_drm_enabled":false,"is_epub_drm_enabled":false,"download_pdf_url":"http://www.google.com/patents/download/7130991_Method_and_apparatus_for_loop_de.pdf?id=10Z7AAAAEBAJ\u0026output=pdf\u0026sig=ACfU3U2cml0lmi4tGlGI3UlT9Ilb_0HLhw"},"sample_url":"http://www.google.com/patents/reader?id=10Z7AAAAEBAJ\u0026printsec=frontcover\u0026output=reader\u0026source=gbs_atb_hover","is_browsable":true,"is_public_domain":true}, {});</script><div id="footer_table" style="font-size:83%;text-align:center;position:relative;top:20px;height:4.5em;margin-top:2em"><div style="margin-bottom:8px"><a href=http://www.google.com/><nobr>Google&nbsp;Home</nobr></a> - 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id="appbar-download-pdf-link" href="/patents/US7143273.pdf"></a></div><div class="kd-buttonbar right" id="right-toolbar-buttons"></div></div><div id="books-microdata" itemscope=""itemtype="http://schema.org/Book"itemid="http://www.google.com/patents/US7143273" style="display:none"><span itemprop="description">Toggling between accessing an entry in a global history with a stew created from branch predictions implied by the ordering of instructions within a trace of a trace cache when a trace is read out of a trace cache, and accessing an entry in a global history with repeatable variations of a stew when there...</span><span itemprop="url">http://www.google.com/patents/US7143273?utm_source=gb-gplus-share</span><span class="main-title" itemprop="name">Patent US7143273 - Method and apparatus for dynamic branch prediction utilizing multiple stew algorithms for indexing a global history</span><img itemprop="image" src="http://www.google.com/patents?id=fUN9AAAAEBAJ&amp;printsec=frontcover&amp;img=1&amp;zoom=1"alt="Patent US7143273 - Method and apparatus for dynamic branch prediction utilizing multiple stew algorithms for indexing a global history" title="Patent US7143273 - Method and apparatus for dynamic branch prediction utilizing multiple stew algorithms for indexing a global history"></div><table id="viewport_table" cellpadding="0" style="clear:both" cellspacing="0"><tr><td id="menu_td" class="menu_td"><div id=menu_container><div class=menu id=menu><div class="menu_content" style="margin-bottom:6px"><div id="volume-info-sidebar"><span class="gb-survey-link"></span><h1 class="gb-volume-title" dir=ltr>Method and apparatus for dynamic branch prediction utilizing multiple stew ...</h1>&nbsp;<span class="addmd">John Alan Miller et al</span></div><div style="margin-bottom:4px"><div class=sidebarnav><div class=sidebarcover><a href="http://www.google.com/patents?id=fUN9AAAAEBAJ&printsec=abstract" ><img src="http://bks1.books.google.com/patents?id=fUN9AAAAEBAJ&printsec=abstract&img=1&zoom=1&sig=ACfU3U1VgusMneOOpOOpeDsgOMiVJ8NgaQ" alt="Abstract" title="Abstract" width=102 border=1 id=summary-frontcover ></a></div><span class=nolink>&rsaquo;&nbsp;Overview</span><br><a href="/patents/US7143273?printsec=abstract&dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">Abstract</a><br><a href="/patents/US7143273?printsec=drawing&dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">Drawings</a><br><a href="/patents/US7143273?printsec=description&dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">Description</a><br><a href="/patents/US7143273?printsec=claims&dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">Claims</a><br><span id="gb-atb-patents-plusone-container"></span></div></div></div><div style="clear:both"></div><div style="margin-left:10px"><form action=/patents id=search_form style="margin:0px;padding:0px;" method=get> <input type=hidden name=ei value="EQj-T5-UOYaI0QGdrvHkBg"><input type=hidden name=id value="fUN9AAAAEBAJ"><input type=hidden name=dq value="george david zalepa"><table cellpadding=0 cellspacing=0 class="swv-table"><tr><td width="100%" class="swv-td-search"><span><input id=search_form_input type=text maxlength=1024 class="text_flat swv-input-search" name=q value="" title="Go" accesskey=i></span></td><td class="swv-td-space">&nbsp;&nbsp;</td><td><input type=submit value="Go"></td></tr></table><script type="text/javascript">if (window['_OC_autoDir']) {_OC_autoDir('search_form_input');}</script></form></div><div id="menu_scroll"><div id=metadata_content class=menu_content><div id=metadata_v><div class=patent_bibdata><p><b>Patent number</b>: 7143273<br><b>Filing date</b>: Mar 31, 2003<br><b>Issue date</b>: Nov 28, 2006<br><b>Application number</b>:&nbsp;<a href="/patents/US20040193857?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">10/404,812</a><br></p></div></div></div></div></div></div></td><td id="viewport_td"><div class=vertical_module_list_row><div id=overview class=about_content><div id=overview_v><table id="summarytable" cellpadding="0" cellspacing="0" border="0" width="100%"><tr><td valign=top><p class="patent_abstract_text">Toggling between accessing an entry in a global history with a stew created from branch predictions implied by the ordering of instructions within a trace of a trace cache when a trace is read out of a trace cache, and accessing an entry in a global history with repeatable variations of a stew when there is more than branch instruction within a trace within the trace cache and at least a second branch instruction is read out.</p><div class="patent_bibdata"><b>Inventors</b>:&nbsp;<a href="http://www.google.com/search?tbo=p&amp;tbm=pts&amp;hl=en&amp;q=ininventor:%22John+Alan+Miller%22">John Alan Miller</a>, <a href="http://www.google.com/search?tbo=p&amp;tbm=pts&amp;hl=en&amp;q=ininventor:%22Slade+A.+Morgan%22">Slade A. Morgan</a>, <a href="http://www.google.com/search?tbo=p&amp;tbm=pts&amp;hl=en&amp;q=ininventor:%22Stephan+J.+Jourdan%22">Stephan J. Jourdan</a><br><b>Original Assignee</b>:&nbsp;<a href="http://www.google.com/search?tbo=p&amp;tbm=pts&amp;hl=en&amp;q=inassignee:%22Intel+Corporation%22">Intel Corporation</a><br><b>Primary Examiner</b>:&nbsp;Eddie Chan<br><b>Secondary Examiner</b>:&nbsp;George D. Zalepa<br><b>Attorney</b>:&nbsp;Ram P. Yadav<br><b>Current U.S. Classification</b>:&nbsp;<a href="http://www.google.com/url?id=fUN9AAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc712/defs712.htm&amp;usg=AFQjCNFSlkDLYE-yriA4W3Ix_OZ4YREIEw#C712S240000">712/240</a>; <a href="http://www.google.com/url?id=fUN9AAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc712/defs712.htm&amp;usg=AFQjCNFSlkDLYE-yriA4W3Ix_OZ4YREIEw#C712S233000">712/233</a>; <a href="http://www.google.com/url?id=fUN9AAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc712/defs712.htm&amp;usg=AFQjCNFSlkDLYE-yriA4W3Ix_OZ4YREIEw#C712S239000">712/239</a>; <a href="http://www.google.com/url?id=fUN9AAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc712/defs712.htm&amp;usg=AFQjCNFSlkDLYE-yriA4W3Ix_OZ4YREIEw#C712SE09051">712/E09.051</a>; <a href="http://www.google.com/url?id=fUN9AAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc712/defs712.htm&amp;usg=AFQjCNFSlkDLYE-yriA4W3Ix_OZ4YREIEw#C712SE09055">712/E09.055</a>; <a href="http://www.google.com/url?id=fUN9AAAAEBAJ&amp;q=http://www.uspto.gov/web/patents/classification/uspc712/defs712.htm&amp;usg=AFQjCNFSlkDLYE-yriA4W3Ix_OZ4YREIEw#C712SE09057">712/E09.057</a><br><br><a href="http://www.google.com/url?id=fUN9AAAAEBAJ&q=http://patft.uspto.gov/netacgi/nph-Parser%3FSect2%3DPTO1%26Sect2%3DHITOFF%26p%3D1%26u%3D/netahtml/PTO/search-bool.html%26r%3D1%26f%3DG%26l%3D50%26d%3DPALL%26RefSrch%3Dyes%26Query%3DPN/7143273&usg=AFQjCNExWTwOuy-xn2wjDdc8P9e4hKmxYw">View patent at USPTO</a><br><a href="http://www.google.com/url?id=fUN9AAAAEBAJ&q=http://assignments.uspto.gov/assignments/q%3Fdb%3Dpat%26pat%3D7143273&usg=AFQjCNHFx-zi2ugDdtTBJjhsmlwmndM7iQ">Search USPTO Assignment Database</a><br><a href="http://www.google.com/url?id=fUN9AAAAEBAJ&q=http://commondatastorage.googleapis.com/uspto-pair/applications/10404812.zip&usg=AFQjCNE90N7M-uAH46ddh_vqZ77du9ruNA">Download USPTO Public PAIR data</a><br></div></table></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="patent_citations_anchor"></a>Citations</h3><div id=patent_citations class=about_content><div id=patent_citations_v><table class=rel_patent style="border-spacing:10px 0" cellpadding=4><tr><td class=rel_patent_header><b>Cited Patent</b></td><td class=rel_patent_header><b>Filing date</b></td><td class=rel_patent_header><b>Issue date</b></td><td class=rel_patent_header><b>Original Assignee</b></td><td class="rel_patent_header rel_patent_title"><b>Title</b></td></tr><tr><td valign=top nowrap><a href="/patents/US5758142?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US5758142</a></td><td valign=top nowrap>May 31, 1994</td><td valign=top nowrap>May 26, 1998</td><td valign=top>Digital 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cache</td></tr><tr><td valign=top nowrap><a href="/patents/US20050149912?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US20050149912</a></td><td valign=top nowrap>Dec 29, 2003</td><td valign=top nowrap></td><td valign=top></td><td class=rel_patent_title valign=top>Dynamic online optimizer</td></tr><tr><td valign=top nowrap><a href="/patents/US20050289324?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US20050289324</a></td><td valign=top nowrap>Aug 31, 2005</td><td valign=top nowrap></td><td valign=top></td><td class=rel_patent_title valign=top>Trace cache bypassing</td></tr></table></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="patent_referenced_by_anchor"></a>Referenced by</h3><div id=patent_referenced_by class=about_content><div id=patent_referenced_by_v><table class=rel_patent style="border-spacing:10px 0" cellpadding=4><tr><td class=rel_patent_header><b>Citing Patent</b></td><td class=rel_patent_header><b>Filing date</b></td><td class=rel_patent_header><b>Issue date</b></td><td class=rel_patent_header><b>Original Assignee</b></td><td class="rel_patent_header rel_patent_title"><b>Title</b></td></tr><tr><td valign=top nowrap><a href="/patents/US7685410?dq=george+david+zalepa&ei=EQj-T5-UOYaI0QGdrvHkBg">US7685410</a></td><td valign=top nowrap>Feb 13, 2007</td><td valign=top nowrap>Mar 23, 2010</td><td valign=top>Global Foundries Inc.</td><td class=rel_patent_title valign=top>Redirect recovery cache that receives branch misprediction redirects and caches instructions to be dispatched in response to the redirects</td></tr></table></div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="patent_claims_anchor"></a>Claims</h3><div id=patent_claims class=about_content><div id=patent_claims_v><p>1. An apparatus comprising:<p><dl><dd style="margin-left:1em;">a global history in which branch patterns of branches taken and not taken are stored;</dd></dl><p><dl><dd style="margin-left:1em;">a first stew logic having a first stew algorithm for creating a first stew; and</dd></dl><p><dl><dd style="margin-left:1em;">a second stew logic having a second stew algorithm for creating a second stew,</dd></dl><p><dl><dd style="margin-left:1em;">wherein the global history repeatedly toggles between accessing entries with stews from the first stew logic and accessing entries with stews from the second stew logic.</dd></dl><p>2. The apparatus of claim 1, wherein entries corresponding to stored branch patterns are organized in a cache-like array and accessed using some bits comprising a stew as tag bits, and other bits comprising a stew as index bits.<p>3. The apparatus of claim 1, further comprising a trace cache, wherein the global history accesses an entry with a stew from the first stew logic when a trace begins to be read out of the trace cache, and wherein the global history accesses an entry with a stew from the second stew logic if there is a plurality of branch instructions within the trace and at least a second branch instruction is read out of the trace cache.<p>4. The apparatus of claim 1, wherein the second stew algorithm of the second stew logic entails making at least one variation of a stew created by the first stew logic in a manner that is repeatable.<p>5. The apparatus of claim 4, wherein the second stew algorithm of the second stew logic entails repeatedly adding a constant value to a stew created by the first stew logic.<p>6. An apparatus comprising:<p><dl><dd style="margin-left:1em;">an execution engine;</dd></dl><p><dl><dd style="margin-left:1em;">a trace cache reading out traces of instructions stored within the trace cache to be supplied to the execution engine;</dd></dl><p><dl><dd style="margin-left:1em;">a global history in which branch patterns of branches taken and not taken are stored;</dd></dl><p><dl><dd style="margin-left:1em;">a first stew logic supplying to the global history a first stew created from the branch patterns of branches taken and not taken as indicated by the branch predictions implied by the ordering of instructions within the traces stored within the trace cache; and</dd><dd style="margin-left:1em;">a variation logic creating and supplying to the global history a second stew from the first stew by way of a repeatable algorithm.</dd></dl><p>7. The apparatus of claim 6, wherein partial dominance between predictions is employed such that a prediction implied by the ordering of instructions within a trace stored within the trace cache is used for a given branch instruction unless there is a prediction found to exist within the global history that corresponds to the branch pattern history leading up to that branch instruction.<p>8. The apparatus of claim 6, wherein the global history accesses an entry within the global history with a stew supplied by the first stew logic when a trace begins to be read out of the trace cache, and wherein the global history accesses an entry within the global history with a stew supplied by the variation logic when there is a plurality of branch instructions in a given trace and at least a second branch instruction is read out of the trace cache.<p>9. The apparatus of claim 6, further comprising a second stew logic supplying to the global history a third stew created from the actual branch patterns of branches taken and not taken during the execution of instructions by the execution engine, and wherein an entry within the global history is accessed with a stew supplied by the second stew logic when a misprediction occurs.<p>10. The apparatus of claim 6, further comprising: a branch history table; and a second stew logic supplying to the global history a third stew created from the branch patterns of branches taken and not taken as indicated by the branch predictions provided by the branch history table.<p>11. The apparatus of claim 10, wherein the branch history table has entries only for branch instructions where a prediction implied by the ordering of instructions within a trace within the trace cache for those branch instructions proved to be a misprediction at least once when those branch instructions were actually executed by the execution engine.<p>12. The apparatus of claim 11, wherein partial dominance between predictions is employed such that a prediction implied by the ordering of instructions within a trace stored within the trace cache is used for a given branch instruction unless there is a prediction found to exist for that branch instruction within the branch history table, in which case, the prediction found within the branch history table is used for the given branch instruction unless a prediction is found to exist within the global history that corresponds to the branch pattern history leading up to that branch instruction.<p>13. A method comprising:<p><dl><dd style="margin-left:1em;">creating a first stew from the branch patterns of branches to be taken and not taken as indicated by the branch predictions implied by the ordering of instructions within the traces stored within a trace cache;</dd></dl><p><dl><dd style="margin-left:1em;">creating a second stew from a repeatable variation of the first stew;</dd></dl><p><dl><dd style="margin-left:1em;">accessing an entry within a global history with the first stew when a trace is read out of a trace cache; and</dd></dl><p><dl><dd style="margin-left:1em;">accessing an entry within the global history with the second stew when there is a plurality of branch instructions within a trace within the trace cache, and at least a second branch instruction within that trace has been read out.</dd></dl><p>14. The method of claim 13, further comprising supplying an execution engine with a whole trace read out of the trace cache unless a prediction is found to exist within the global history that corresponds to the branch pattern history leading up to the branch instruction within the trace.<p>15. The method of claim 13, further comprising supplying an execution engine with a whole trace read out of the trace cache unless a prediction is found to exist within a branch history table for the branch instruction within the trace.<p>16. The method of claim 13, further comprising: creating a third stew from the branch patterns of the actual branches taken and not taken during execution of instructions by an execution engine; and accessing an entry within the global history with the third stew when a prediction implied by the ordering of instructions within a trace read out of the trace cache proves to be a misprediction.<p>17. The method of claim 13, wherein creating the second stew from a repeatable variation of the first stew entails repeatedly adding a constant value to the first stew.<p>18. A machine-accessible medium comprising code that when executed by a processing device within an electronic device, causes the electronic device to:<p><dl><dd style="margin-left:1em;">create a first stew from the branch patterns of branches to be taken and not taken as indicated by the branch predictions implied by the ordering of instructions within the traces stored within a trace cache;</dd></dl><p><dl><dd style="margin-left:1em;">create a second stew from a repeatable variation of the first stew;</dd></dl><p><dl><dd style="margin-left:1em;">access an entry within a global history with the first stew when a trace is read out of a trace cache; and</dd></dl><p><dl><dd style="margin-left:1em;">access an entry within the global history with the second stew when there is a plurality of branch instructions within a trace within the trace cache, and at least a second branch instruction within that trace has been read out.</dd></dl><p>19. The machine-accessible medium of claim 18, wherein the repeatable variation of the first stew is created by adding a constant value to the first stew.</div></div></div><div class=vertical_module_list_row><h3 class=about_title><a name="selected_pages_anchor"></a>Drawings</h3><div id=selected_pages class=about_content><div id=selected_pages_v><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=fUN9AAAAEBAJ&pg=PA3&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" ><img src="http://bks1.books.google.com/patents?id=fUN9AAAAEBAJ&amp;pg=PA3&amp;img=1&amp;zoom=1&amp;sig=ACfU3U3gBSmc4x0OB--I-P52F-bLomX9EQ" alt="Drawings" title="Drawings" height="160" border="1"></a><br/><a class="primary" href="http://www.google.com/patents?id=fUN9AAAAEBAJ&pg=PA3&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" >Drawings</a></div><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=fUN9AAAAEBAJ&pg=PA4&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" ><img src="http://bks1.books.google.com/patents?id=fUN9AAAAEBAJ&amp;pg=PA4&amp;img=1&amp;zoom=1&amp;sig=ACfU3U1EUnPP6hx43NouhmpFAh1ap6xT0A" alt="Drawings" title="Drawings" height="160" border="1"></a><br/><a class="primary" href="http://www.google.com/patents?id=fUN9AAAAEBAJ&pg=PA4&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" >Drawings</a></div><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=fUN9AAAAEBAJ&pg=PA5&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" ><img src="http://bks1.books.google.com/patents?id=fUN9AAAAEBAJ&amp;pg=PA5&amp;img=1&amp;zoom=1&amp;sig=ACfU3U1kN6wWvZxtHiG2mToT-CnDQ97f6A" alt="Drawings" title="Drawings" height="160" border="1"></a><br/><a class="primary" href="http://www.google.com/patents?id=fUN9AAAAEBAJ&pg=PA5&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" >Drawings</a></div><div class="selectedpagesthumbnail"><a href="http://www.google.com/patents?id=fUN9AAAAEBAJ&pg=PA6&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" ><img src="http://bks1.books.google.com/patents?id=fUN9AAAAEBAJ&amp;pg=PA6&amp;img=1&amp;zoom=1&amp;sig=ACfU3U1KA3V0y5q9FnU2Rd5SYYys6TTy_Q" alt="Drawings" title="Drawings" height="160" border="1"></a><br/><a class="primary" href="http://www.google.com/patents?id=fUN9AAAAEBAJ&pg=PA6&dq=george+david+zalepa&source=gbs_selected_pages&cad=4" >Drawings</a></div><div style="clear:both;"></div></div></div></div></td></tr></table><script type="text/javascript">_OC_addFlags({LockSrc:"/books/javascript/lock_b9ee852b3231a450c67d122471b67ac7.js", IsWebstoreDisplayCaseEnabled:1, IsObfuscationEnabled:1, IsBrowsingHistoryEnabled:1, IsGeoLayerEnabled:0, IsGiftingEnabled:0, IsOfflineBubbleEnabled:1, IsReaderEnabledForPlayRequests:1, IsUnifiedHovercardEnabled:1, IsFutureOnSaleVolumesEnabled:1, IsBooksUnifiedLeftNavEnabled:1, IsZipitFolderCollectionEnabled:1, IsRatingsOnBookcardsEnabled:1, IsEmbeddedMediaEnabled:1, IsImageModeAnnotationsEnabled:0, IsMyLibraryGooglePlusEnabled:1, IsBookcardListPriceSmall:0, IsBooksShareButtonEnabled:0, IsPreOrdersEnabled:1, IsDisabledRandomBookshelves:0, WebstoreDisplayCasePosition:3});_OC_addMsgs();_OC_Run({"enable_p13n":false,"add_vol_to_collection_base_url":"http://www.google.com/patents?op=add\u0026sig=ACfU3U2NR9gLbaUjBBmf3hRNvlVxNGjPdw\u0026id=fUN9AAAAEBAJ","remove_vol_from_collection_base_url":"http://www.google.com/patents?op=remove\u0026sig=ACfU3U1ASqT0009jj4tQlE1VzGgKmai3sA\u0026id=fUN9AAAAEBAJ","logged_in":true,"p13n_save_user_settings_url":"http://www.google.com/patents?op=edit_user_settings\u0026sig=ACfU3U1csLrPRWWF41pcqYdLt6glRm7l_A","is_cobrand":false,"is_play_enabled":true}, {"volume_id":"","is_ebook":true,"volumeresult":{"has_flowing_text":false,"has_scanned_text":true,"can_download_pdf":false,"can_download_epub":false,"is_pdf_drm_enabled":false,"is_epub_drm_enabled":false,"download_pdf_url":"http://www.google.com/patents/download/7143273_Method_and_apparatus_for_dynamic.pdf?id=fUN9AAAAEBAJ\u0026output=pdf\u0026sig=ACfU3U2Oh2iWT_bnOxDzOj9dLzoJN-uBBQ"},"sample_url":"http://www.google.com/patents/reader?id=fUN9AAAAEBAJ\u0026printsec=frontcover\u0026output=reader\u0026source=gbs_atb_hover","is_browsable":true,"is_public_domain":true}, {});</script><div id="footer_table" style="font-size:83%;text-align:center;position:relative;top:20px;height:4.5em;margin-top:2em"><div style="margin-bottom:8px"><a href=http://www.google.com/><nobr>Google&nbsp;Home</nobr></a> - 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