origen_verilog 0.6.2 → 0.6.3

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@@ -1,7 +1,7 @@
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  module OrigenVerilog
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  MAJOR = 0
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  MINOR = 6
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- BUGFIX = 2
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+ BUGFIX = 3
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  DEV = nil
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  VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
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@@ -3,16 +3,46 @@ module OrigenVerilog
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  include Origen::TopLevel
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  attr_reader :name
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+ attr_reader :options
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  def initialize(options = {})
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  @name = options[:ast].to_a[0]
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+ @options = options
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- options[:ast].pins(digital: true).each { |n| _add_pin_(n, :digital) }
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- options[:ast].pins(analog: true).each { |n| _add_pin_(n, :analog) }
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+ pins = options[:ast].pins(digital: true).map { |p| [p, :digital] }.to_h
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+ pins.merge!(options[:ast].pins(analog: true).map { |p| [p, :analog] }.to_h)
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+
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+ # Override any pin types from the user
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+ if options[:forced_pin_types]
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+ pins = pins.map do |pin, type|
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+ matched = options[:forced_pin_types].any? do |matcher, forced_type|
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+ if matcher.is_a?(Regexp) && pin.value =~ matcher
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+ type = forced_type
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+ true
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+ elsif pin.value == matcher
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+ type = forced_type
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+ true
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+ end
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+ end
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+ matched ? [pin, type] : [pin, type]
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+ end.to_h
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+ end
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+ pins.each { |n, type| _add_pin_(n, type) }
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31
  end
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14
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  private
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34
 
35
+ def pin_role?(role, pin)
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+ (options[role] || []).each do |matcher|
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+ if matcher.is_a?(Regexp)
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+ return true if pin.to_s =~ matcher
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+ else
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+ return true if pin.to_s == matcher
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+ end
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+ end
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+ false
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+ end
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+
16
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  def _add_pin_(node, type)
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47
  node = node.evaluate # Resolve any functions in the ranges
18
48
  if node.type == :input_declaration
@@ -31,7 +61,18 @@ module OrigenVerilog
31
61
  end
32
62
  n = node.to_a.dup
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  while n.last.is_a?(String)
34
- add_pin n.pop.to_sym, direction: direction, size: size, offset: offset, type: type
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+ pin = n.pop
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+ if pin_role?(:ground_pins, pin)
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+ add_ground_pin pin.to_sym, direction: direction, size: size, offset: offset, type: type
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+ elsif pin_role?(:power_pins, pin)
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+ add_power_pin pin.to_sym, direction: direction, size: size, offset: offset, type: type
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+ elsif pin_role?(:virtual_pins, pin)
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+ add_virtual_pin pin.to_sym, direction: direction, size: size, offset: offset, type: type
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+ elsif pin_role?(:other_pins, pin)
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+ add_other_pin pin.to_sym, direction: direction, size: size, offset: offset, type: type
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+ else
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+ add_pin pin.to_sym, direction: direction, size: size, offset: offset, type: type
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+ end
35
76
  end
36
77
  end
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  end
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@@ -94,11 +94,12 @@ module OrigenVerilog
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94
  #
95
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  # This will re-load the Origen target with the resultant model instantiated
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  # as the global dut object.
97
- def to_top_level
97
+ def to_top_level(options = {})
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98
  unless type == :module_declaration
99
99
  fail 'Currently only modules support the to_model method'
100
100
  end
101
- Origen.target.temporary = -> { TopLevel.new(ast: self) }
101
+ options[:ast] = self
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+ Origen.target.temporary = -> { TopLevel.new(options) }
102
103
  Origen.load_target
103
104
  end
104
105
  end
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metadata CHANGED
@@ -1,14 +1,14 @@
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  --- !ruby/object:Gem::Specification
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2
  name: origen_verilog
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3
  version: !ruby/object:Gem::Version
4
- version: 0.6.2
4
+ version: 0.6.3
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5
  platform: ruby
6
6
  authors:
7
7
  - Stephen McGinty
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8
  autorequire:
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9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2019-06-12 00:00:00.000000000 Z
11
+ date: 2019-09-24 00:00:00.000000000 Z
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12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: origen