origen_verilog 0.6.2 → 0.6.3
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/config/application.rb +0 -0
- data/config/boot.rb +0 -0
- data/config/commands.rb +0 -0
- data/config/version.rb +1 -1
- data/grammars/preprocessor.rb +0 -0
- data/lib/origen_verilog.rb +0 -0
- data/lib/origen_verilog/commands/parse.rb +0 -0
- data/lib/origen_verilog/node.rb +0 -0
- data/lib/origen_verilog/parser.rb +0 -0
- data/lib/origen_verilog/preprocessor/contatenator.rb +0 -0
- data/lib/origen_verilog/preprocessor/node.rb +0 -0
- data/lib/origen_verilog/preprocessor/parser.rb +0 -0
- data/lib/origen_verilog/preprocessor/processor.rb +0 -0
- data/lib/origen_verilog/preprocessor/verilog_parser.rb +0 -0
- data/lib/origen_verilog/preprocessor/writer.rb +0 -0
- data/lib/origen_verilog/processor.rb +0 -0
- data/lib/origen_verilog/top_level.rb +44 -3
- data/lib/origen_verilog/verilog/evaluator.rb +0 -0
- data/lib/origen_verilog/verilog/node.rb +3 -2
- data/lib/origen_verilog/verilog/parser.rb +0 -0
- data/lib/origen_verilog/verilog/processor.rb +0 -0
- data/lib/origen_verilog/verilog/writer.rb +0 -0
- data/lib/tasks/origen_verilog.rake +0 -0
- data/templates/web/index.md.erb +0 -0
- data/templates/web/layouts/_basic.html.erb +0 -0
- data/templates/web/partials/_navbar.html.erb +0 -0
- data/templates/web/release_notes.md.erb +0 -0
- metadata +2 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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-
metadata.gz:
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-
data.tar.gz:
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metadata.gz: a9fdce456928015804fdbe1484435502d8b800e2ecd5c7ddf78754046920edda
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4
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data.tar.gz: 5b979ee15cd8043d882ef4ad70c083c6fca4b309bb2e57e2982ea657d95405a6
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: daaed8357b6a78f47b58aac1291e554674b3d670657eb98d16bbc9241e797e422baaf5f8e5dc5a5766b1c5d7c2c0da6aa7190bc5f293e9f124bb392e9fa9e58d
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7
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data.tar.gz: 3cea195cee036fd928857134ffe12b8c8771f2267a59b2b643ace3f65eca3f5cca819ace960b76b117e30c0f102d8c07e3236c2aefd7573610a37fd43cec784d
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data/config/application.rb
CHANGED
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data/config/boot.rb
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data/config/commands.rb
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data/config/version.rb
CHANGED
data/grammars/preprocessor.rb
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data/lib/origen_verilog.rb
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data/lib/origen_verilog/node.rb
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@@ -3,16 +3,46 @@ module OrigenVerilog
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include Origen::TopLevel
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attr_reader :name
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attr_reader :options
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def initialize(options = {})
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@name = options[:ast].to_a[0]
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@options = options
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-
options[:ast].pins(digital: true).
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options[:ast].pins(analog: true).
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pins = options[:ast].pins(digital: true).map { |p| [p, :digital] }.to_h
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pins.merge!(options[:ast].pins(analog: true).map { |p| [p, :analog] }.to_h)
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# Override any pin types from the user
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if options[:forced_pin_types]
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pins = pins.map do |pin, type|
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matched = options[:forced_pin_types].any? do |matcher, forced_type|
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if matcher.is_a?(Regexp) && pin.value =~ matcher
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type = forced_type
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true
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elsif pin.value == matcher
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type = forced_type
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true
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end
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end
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matched ? [pin, type] : [pin, type]
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end.to_h
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end
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pins.each { |n, type| _add_pin_(n, type) }
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end
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private
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def pin_role?(role, pin)
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(options[role] || []).each do |matcher|
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if matcher.is_a?(Regexp)
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return true if pin.to_s =~ matcher
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else
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return true if pin.to_s == matcher
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end
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end
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false
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end
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def _add_pin_(node, type)
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node = node.evaluate # Resolve any functions in the ranges
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if node.type == :input_declaration
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@@ -31,7 +61,18 @@ module OrigenVerilog
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end
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n = node.to_a.dup
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while n.last.is_a?(String)
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-
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pin = n.pop
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if pin_role?(:ground_pins, pin)
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add_ground_pin pin.to_sym, direction: direction, size: size, offset: offset, type: type
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elsif pin_role?(:power_pins, pin)
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add_power_pin pin.to_sym, direction: direction, size: size, offset: offset, type: type
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elsif pin_role?(:virtual_pins, pin)
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add_virtual_pin pin.to_sym, direction: direction, size: size, offset: offset, type: type
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elsif pin_role?(:other_pins, pin)
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add_other_pin pin.to_sym, direction: direction, size: size, offset: offset, type: type
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else
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add_pin pin.to_sym, direction: direction, size: size, offset: offset, type: type
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end
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end
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end
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end
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@@ -94,11 +94,12 @@ module OrigenVerilog
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#
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# This will re-load the Origen target with the resultant model instantiated
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# as the global dut object.
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-
def to_top_level
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def to_top_level(options = {})
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unless type == :module_declaration
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fail 'Currently only modules support the to_model method'
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end
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-
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options[:ast] = self
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Origen.target.temporary = -> { TopLevel.new(options) }
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Origen.load_target
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end
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end
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data/templates/web/index.md.erb
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metadata
CHANGED
@@ -1,14 +1,14 @@
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--- !ruby/object:Gem::Specification
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name: origen_verilog
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version: !ruby/object:Gem::Version
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version: 0.6.
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version: 0.6.3
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platform: ruby
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authors:
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- Stephen McGinty
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autorequire:
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bindir: bin
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cert_chain: []
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date: 2019-
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date: 2019-09-24 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: origen
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