origen_verilog 0.6.2 → 0.6.3
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- checksums.yaml +4 -4
- data/config/application.rb +0 -0
- data/config/boot.rb +0 -0
- data/config/commands.rb +0 -0
- data/config/version.rb +1 -1
- data/grammars/preprocessor.rb +0 -0
- data/lib/origen_verilog.rb +0 -0
- data/lib/origen_verilog/commands/parse.rb +0 -0
- data/lib/origen_verilog/node.rb +0 -0
- data/lib/origen_verilog/parser.rb +0 -0
- data/lib/origen_verilog/preprocessor/contatenator.rb +0 -0
- data/lib/origen_verilog/preprocessor/node.rb +0 -0
- data/lib/origen_verilog/preprocessor/parser.rb +0 -0
- data/lib/origen_verilog/preprocessor/processor.rb +0 -0
- data/lib/origen_verilog/preprocessor/verilog_parser.rb +0 -0
- data/lib/origen_verilog/preprocessor/writer.rb +0 -0
- data/lib/origen_verilog/processor.rb +0 -0
- data/lib/origen_verilog/top_level.rb +44 -3
- data/lib/origen_verilog/verilog/evaluator.rb +0 -0
- data/lib/origen_verilog/verilog/node.rb +3 -2
- data/lib/origen_verilog/verilog/parser.rb +0 -0
- data/lib/origen_verilog/verilog/processor.rb +0 -0
- data/lib/origen_verilog/verilog/writer.rb +0 -0
- data/lib/tasks/origen_verilog.rake +0 -0
- data/templates/web/index.md.erb +0 -0
- data/templates/web/layouts/_basic.html.erb +0 -0
- data/templates/web/partials/_navbar.html.erb +0 -0
- data/templates/web/release_notes.md.erb +0 -0
- metadata +2 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
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1
1
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---
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2
2
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SHA256:
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3
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-
metadata.gz:
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4
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-
data.tar.gz:
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3
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+
metadata.gz: a9fdce456928015804fdbe1484435502d8b800e2ecd5c7ddf78754046920edda
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4
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+
data.tar.gz: 5b979ee15cd8043d882ef4ad70c083c6fca4b309bb2e57e2982ea657d95405a6
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5
5
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SHA512:
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6
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-
metadata.gz:
|
7
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-
data.tar.gz:
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6
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+
metadata.gz: daaed8357b6a78f47b58aac1291e554674b3d670657eb98d16bbc9241e797e422baaf5f8e5dc5a5766b1c5d7c2c0da6aa7190bc5f293e9f124bb392e9fa9e58d
|
7
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+
data.tar.gz: 3cea195cee036fd928857134ffe12b8c8771f2267a59b2b643ace3f65eca3f5cca819ace960b76b117e30c0f102d8c07e3236c2aefd7573610a37fd43cec784d
|
data/config/application.rb
CHANGED
File without changes
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data/config/boot.rb
CHANGED
File without changes
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data/config/commands.rb
CHANGED
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data/config/version.rb
CHANGED
data/grammars/preprocessor.rb
CHANGED
File without changes
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data/lib/origen_verilog.rb
CHANGED
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File without changes
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data/lib/origen_verilog/node.rb
CHANGED
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File without changes
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File without changes
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File without changes
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@@ -3,16 +3,46 @@ module OrigenVerilog
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3
3
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include Origen::TopLevel
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4
4
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5
5
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attr_reader :name
|
6
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+
attr_reader :options
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6
7
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|
7
8
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def initialize(options = {})
|
8
9
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@name = options[:ast].to_a[0]
|
10
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+
@options = options
|
9
11
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|
10
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-
options[:ast].pins(digital: true).
|
11
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-
options[:ast].pins(analog: true).
|
12
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+
pins = options[:ast].pins(digital: true).map { |p| [p, :digital] }.to_h
|
13
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+
pins.merge!(options[:ast].pins(analog: true).map { |p| [p, :analog] }.to_h)
|
14
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+
|
15
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+
# Override any pin types from the user
|
16
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+
if options[:forced_pin_types]
|
17
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+
pins = pins.map do |pin, type|
|
18
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+
matched = options[:forced_pin_types].any? do |matcher, forced_type|
|
19
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+
if matcher.is_a?(Regexp) && pin.value =~ matcher
|
20
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+
type = forced_type
|
21
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+
true
|
22
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+
elsif pin.value == matcher
|
23
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+
type = forced_type
|
24
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+
true
|
25
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+
end
|
26
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+
end
|
27
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+
matched ? [pin, type] : [pin, type]
|
28
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+
end.to_h
|
29
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+
end
|
30
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+
pins.each { |n, type| _add_pin_(n, type) }
|
12
31
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end
|
13
32
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|
14
33
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private
|
15
34
|
|
35
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+
def pin_role?(role, pin)
|
36
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+
(options[role] || []).each do |matcher|
|
37
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+
if matcher.is_a?(Regexp)
|
38
|
+
return true if pin.to_s =~ matcher
|
39
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+
else
|
40
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+
return true if pin.to_s == matcher
|
41
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+
end
|
42
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+
end
|
43
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+
false
|
44
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+
end
|
45
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+
|
16
46
|
def _add_pin_(node, type)
|
17
47
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node = node.evaluate # Resolve any functions in the ranges
|
18
48
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if node.type == :input_declaration
|
@@ -31,7 +61,18 @@ module OrigenVerilog
|
|
31
61
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end
|
32
62
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n = node.to_a.dup
|
33
63
|
while n.last.is_a?(String)
|
34
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-
|
64
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+
pin = n.pop
|
65
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+
if pin_role?(:ground_pins, pin)
|
66
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+
add_ground_pin pin.to_sym, direction: direction, size: size, offset: offset, type: type
|
67
|
+
elsif pin_role?(:power_pins, pin)
|
68
|
+
add_power_pin pin.to_sym, direction: direction, size: size, offset: offset, type: type
|
69
|
+
elsif pin_role?(:virtual_pins, pin)
|
70
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+
add_virtual_pin pin.to_sym, direction: direction, size: size, offset: offset, type: type
|
71
|
+
elsif pin_role?(:other_pins, pin)
|
72
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+
add_other_pin pin.to_sym, direction: direction, size: size, offset: offset, type: type
|
73
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+
else
|
74
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+
add_pin pin.to_sym, direction: direction, size: size, offset: offset, type: type
|
75
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+
end
|
35
76
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end
|
36
77
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end
|
37
78
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end
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File without changes
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@@ -94,11 +94,12 @@ module OrigenVerilog
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94
94
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#
|
95
95
|
# This will re-load the Origen target with the resultant model instantiated
|
96
96
|
# as the global dut object.
|
97
|
-
def to_top_level
|
97
|
+
def to_top_level(options = {})
|
98
98
|
unless type == :module_declaration
|
99
99
|
fail 'Currently only modules support the to_model method'
|
100
100
|
end
|
101
|
-
|
101
|
+
options[:ast] = self
|
102
|
+
Origen.target.temporary = -> { TopLevel.new(options) }
|
102
103
|
Origen.load_target
|
103
104
|
end
|
104
105
|
end
|
File without changes
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File without changes
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File without changes
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File without changes
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data/templates/web/index.md.erb
CHANGED
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File without changes
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File without changes
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File without changes
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metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
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--- !ruby/object:Gem::Specification
|
2
2
|
name: origen_verilog
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.6.
|
4
|
+
version: 0.6.3
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Stephen McGinty
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date: 2019-
|
11
|
+
date: 2019-09-24 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: origen
|