origen_verilog 0.6.0 → 0.6.1

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data/config/version.rb CHANGED
@@ -1,7 +1,7 @@
1
1
  module OrigenVerilog
2
2
  MAJOR = 0
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3
  MINOR = 6
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- BUGFIX = 0
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+ BUGFIX = 1
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  DEV = nil
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6
 
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  VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
data/grammars/verilog.rb CHANGED
@@ -7375,9 +7375,9 @@ module OrigenVerilog
7375
7375
  module NetType0
7376
7376
  def to_ast
7377
7377
  if text_value == "wire real" || text_value == 'wreal'
7378
- "real"
7378
+ n(:real)
7379
7379
  else
7380
- text_value
7380
+ n(text_value.to_sym)
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7381
  end
7382
7382
  end
7383
7383
  end
@@ -60,8 +60,7 @@ module OrigenVerilog
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  wreals = self.wreals.map { |n| n.to_a.last }
61
61
  subset = []
62
62
  pins.each do |pin|
63
- attrs = pin.to_a
64
- if attrs.include?('real') || wreals.include?(attrs.last)
63
+ if pin.find(:real) || wreals.include?(pin.to_a.last)
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64
  subset << pin if options[:analog]
66
65
  else
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66
  subset << pin if options[:digital]
@@ -82,7 +81,7 @@ module OrigenVerilog
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  def wreals
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82
  find_all(:non_port_module_item)
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  .map { |item| item.find(:net_declaration) }
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- .select { |net| net.to_a.include?('real') }
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+ .select { |net| net.find(:real) }
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  end
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  # Evaluates all functions and turns numbers into Ruby literals
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
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2
  name: origen_verilog
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.6.0
4
+ version: 0.6.1
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5
  platform: ruby
6
6
  authors:
7
7
  - Stephen McGinty
8
8
  autorequire:
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9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2019-05-16 00:00:00.000000000 Z
11
+ date: 2019-06-06 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: origen