origen_verilog 0.6.0 → 0.6.1

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checksums.yaml CHANGED
@@ -1,7 +1,7 @@
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data/config/version.rb CHANGED
@@ -1,7 +1,7 @@
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  module OrigenVerilog
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  MAJOR = 0
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  MINOR = 6
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- BUGFIX = 0
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+ BUGFIX = 1
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  DEV = nil
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  VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
data/grammars/verilog.rb CHANGED
@@ -7375,9 +7375,9 @@ module OrigenVerilog
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  module NetType0
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  def to_ast
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  if text_value == "wire real" || text_value == 'wreal'
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- "real"
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+ n(:real)
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  else
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- text_value
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+ n(text_value.to_sym)
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  end
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  end
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  end
@@ -60,8 +60,7 @@ module OrigenVerilog
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  wreals = self.wreals.map { |n| n.to_a.last }
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  subset = []
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  pins.each do |pin|
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- attrs = pin.to_a
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- if attrs.include?('real') || wreals.include?(attrs.last)
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+ if pin.find(:real) || wreals.include?(pin.to_a.last)
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  subset << pin if options[:analog]
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  else
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  subset << pin if options[:digital]
@@ -82,7 +81,7 @@ module OrigenVerilog
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  def wreals
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  find_all(:non_port_module_item)
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  .map { |item| item.find(:net_declaration) }
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- .select { |net| net.to_a.include?('real') }
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+ .select { |net| net.find(:real) }
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  end
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  # Evaluates all functions and turns numbers into Ruby literals
metadata CHANGED
@@ -1,14 +1,14 @@
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  --- !ruby/object:Gem::Specification
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  name: origen_verilog
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  version: !ruby/object:Gem::Version
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- version: 0.6.0
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+ version: 0.6.1
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  platform: ruby
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  authors:
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  - Stephen McGinty
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2019-05-16 00:00:00.000000000 Z
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+ date: 2019-06-06 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: origen