origen_verilog 0.5.2 → 0.6.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/config/version.rb

@@ -1,7 +1,7 @@
 module OrigenVerilog
   MAJOR = 0
-  MINOR = 5
-  BUGFIX = 2
+  MINOR = 6
+  BUGFIX = 0
   DEV = nil
 
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')

data/grammars/verilog.rb

@@ -7374,7 +7374,11 @@ module OrigenVerilog
 
       module NetType0
         def to_ast
-          text_value
+          if text_value == "wire real" || text_value == 'wreal'
+            "real"
+          else
+            text_value
+          end
         end
       end
 
@@ -7390,11 +7394,11 @@ module OrigenVerilog
         end
 
         i0 = index
-        if (match_len = has_terminal?("supply0", false, index))
+        if (match_len = has_terminal?("wire real", false, index))
           r1 = instantiate_node(SyntaxNode,input, index...(index + match_len))
           @index += match_len
         else
-          terminal_parse_failure('"supply0"')
+          terminal_parse_failure('"wire real"')
           r1 = nil
         end
         if r1
@@ -7403,11 +7407,11 @@ module OrigenVerilog
           r0.extend(NetType0)
           r0.extend(NetType0)
         else
-          if (match_len = has_terminal?("supply1", false, index))
+          if (match_len = has_terminal?("wreal", false, index))
             r2 = instantiate_node(SyntaxNode,input, index...(index + match_len))
             @index += match_len
           else
-            terminal_parse_failure('"supply1"')
+            terminal_parse_failure('"wreal"')
             r2 = nil
           end
           if r2
@@ -7416,11 +7420,11 @@ module OrigenVerilog
             r0.extend(NetType0)
             r0.extend(NetType0)
           else
-            if (match_len = has_terminal?("tri", false, index))
+            if (match_len = has_terminal?("real", false, index))
               r3 = instantiate_node(SyntaxNode,input, index...(index + match_len))
               @index += match_len
             else
-              terminal_parse_failure('"tri"')
+              terminal_parse_failure('"real"')
               r3 = nil
             end
             if r3
@@ -7429,11 +7433,11 @@ module OrigenVerilog
               r0.extend(NetType0)
               r0.extend(NetType0)
             else
-              if (match_len = has_terminal?("triand", false, index))
+              if (match_len = has_terminal?("supply0", false, index))
                 r4 = instantiate_node(SyntaxNode,input, index...(index + match_len))
                 @index += match_len
               else
-                terminal_parse_failure('"triand"')
+                terminal_parse_failure('"supply0"')
                 r4 = nil
               end
               if r4
@@ -7442,11 +7446,11 @@ module OrigenVerilog
                 r0.extend(NetType0)
                 r0.extend(NetType0)
               else
-                if (match_len = has_terminal?("trior", false, index))
+                if (match_len = has_terminal?("supply1", false, index))
                   r5 = instantiate_node(SyntaxNode,input, index...(index + match_len))
                   @index += match_len
                 else
-                  terminal_parse_failure('"trior"')
+                  terminal_parse_failure('"supply1"')
                   r5 = nil
                 end
                 if r5
@@ -7455,11 +7459,11 @@ module OrigenVerilog
                   r0.extend(NetType0)
                   r0.extend(NetType0)
                 else
-                  if (match_len = has_terminal?("tri0", false, index))
+                  if (match_len = has_terminal?("tri", false, index))
                     r6 = instantiate_node(SyntaxNode,input, index...(index + match_len))
                     @index += match_len
                   else
-                    terminal_parse_failure('"tri0"')
+                    terminal_parse_failure('"tri"')
                     r6 = nil
                   end
                   if r6
@@ -7468,11 +7472,11 @@ module OrigenVerilog
                     r0.extend(NetType0)
                     r0.extend(NetType0)
                   else
-                    if (match_len = has_terminal?("tri1", false, index))
+                    if (match_len = has_terminal?("triand", false, index))
                       r7 = instantiate_node(SyntaxNode,input, index...(index + match_len))
                       @index += match_len
                     else
-                      terminal_parse_failure('"tri1"')
+                      terminal_parse_failure('"triand"')
                       r7 = nil
                     end
                     if r7
@@ -7481,11 +7485,11 @@ module OrigenVerilog
                       r0.extend(NetType0)
                       r0.extend(NetType0)
                     else
-                      if (match_len = has_terminal?("uwire", false, index))
+                      if (match_len = has_terminal?("trior", false, index))
                         r8 = instantiate_node(SyntaxNode,input, index...(index + match_len))
                         @index += match_len
                       else
-                        terminal_parse_failure('"uwire"')
+                        terminal_parse_failure('"trior"')
                         r8 = nil
                       end
                       if r8
@@ -7494,11 +7498,11 @@ module OrigenVerilog
                         r0.extend(NetType0)
                         r0.extend(NetType0)
                       else
-                        if (match_len = has_terminal?("wire", false, index))
+                        if (match_len = has_terminal?("tri0", false, index))
                           r9 = instantiate_node(SyntaxNode,input, index...(index + match_len))
                           @index += match_len
                         else
-                          terminal_parse_failure('"wire"')
+                          terminal_parse_failure('"tri0"')
                           r9 = nil
                         end
                         if r9
@@ -7507,11 +7511,11 @@ module OrigenVerilog
                           r0.extend(NetType0)
                           r0.extend(NetType0)
                         else
-                          if (match_len = has_terminal?("wand", false, index))
+                          if (match_len = has_terminal?("tri1", false, index))
                             r10 = instantiate_node(SyntaxNode,input, index...(index + match_len))
                             @index += match_len
                           else
-                            terminal_parse_failure('"wand"')
+                            terminal_parse_failure('"tri1"')
                             r10 = nil
                           end
                           if r10
@@ -7520,11 +7524,11 @@ module OrigenVerilog
                             r0.extend(NetType0)
                             r0.extend(NetType0)
                           else
-                            if (match_len = has_terminal?("wor", false, index))
+                            if (match_len = has_terminal?("uwire", false, index))
                               r11 = instantiate_node(SyntaxNode,input, index...(index + match_len))
                               @index += match_len
                             else
-                              terminal_parse_failure('"wor"')
+                              terminal_parse_failure('"uwire"')
                               r11 = nil
                             end
                             if r11
@@ -7533,8 +7537,50 @@ module OrigenVerilog
                               r0.extend(NetType0)
                               r0.extend(NetType0)
                             else
-                              @index = i0
-                              r0 = nil
+                              if (match_len = has_terminal?("wire", false, index))
+                                r12 = instantiate_node(SyntaxNode,input, index...(index + match_len))
+                                @index += match_len
+                              else
+                                terminal_parse_failure('"wire"')
+                                r12 = nil
+                              end
+                              if r12
+                                r12 = SyntaxNode.new(input, (index-1)...index) if r12 == true
+                                r0 = r12
+                                r0.extend(NetType0)
+                                r0.extend(NetType0)
+                              else
+                                if (match_len = has_terminal?("wand", false, index))
+                                  r13 = instantiate_node(SyntaxNode,input, index...(index + match_len))
+                                  @index += match_len
+                                else
+                                  terminal_parse_failure('"wand"')
+                                  r13 = nil
+                                end
+                                if r13
+                                  r13 = SyntaxNode.new(input, (index-1)...index) if r13 == true
+                                  r0 = r13
+                                  r0.extend(NetType0)
+                                  r0.extend(NetType0)
+                                else
+                                  if (match_len = has_terminal?("wor", false, index))
+                                    r14 = instantiate_node(SyntaxNode,input, index...(index + match_len))
+                                    @index += match_len
+                                  else
+                                    terminal_parse_failure('"wor"')
+                                    r14 = nil
+                                  end
+                                  if r14
+                                    r14 = SyntaxNode.new(input, (index-1)...index) if r14 == true
+                                    r0 = r14
+                                    r0.extend(NetType0)
+                                    r0.extend(NetType0)
+                                  else
+                                    @index = i0
+                                    r0 = nil
+                                  end
+                                end
+                              end
                             end
                           end
                         end

data/lib/origen_verilog/top_level.rb

@@ -7,26 +7,31 @@ module OrigenVerilog
     def initialize(options = {})
       @name = options[:ast].to_a[0]
 
-      options[:ast].pins.each do |node|
-        node = node.evaluate  # Resolve any functions in the ranges
-        if node.type == :input_declaration
-          direction = :input
-        elsif node.type == :ouput_declaration
-          direction = :output
-        else
-          direction = :io
-        end
-        if r = node.find(:range)
-          size = r.to_a[0] - r.to_a[1] + 1
-          offset = r.to_a[1]
-        else
-          size = 1
-          offset = nil
-        end
-        n = node.to_a.dup
-        while n.last.is_a?(String)
-          add_pin n.pop.to_sym, direction: direction, size: size, offset: offset
-        end
+      options[:ast].pins(digital: true).each { |n| _add_pin_(n, :digital) }
+      options[:ast].pins(analog: true).each { |n| _add_pin_(n, :analog) }
+    end
+
+    private
+
+    def _add_pin_(node, type)
+      node = node.evaluate  # Resolve any functions in the ranges
+      if node.type == :input_declaration
+        direction = :input
+      elsif node.type == :ouput_declaration
+        direction = :output
+      else
+        direction = :io
+      end
+      if r = node.find(:range)
+        size = r.to_a[0] - r.to_a[1] + 1
+        offset = r.to_a[1]
+      else
+        size = 1
+        offset = nil
+      end
+      n = node.to_a.dup
+      while n.last.is_a?(String)
+        add_pin n.pop.to_sym, direction: direction, size: size, offset: offset, type: type
       end
     end
   end

data/lib/origen_verilog/verilog/node.rb

@@ -50,9 +50,39 @@ module OrigenVerilog
         end
       end
 
-      # Returns an array containing all input, output and inout AST nodes
-      def pins
-        find_all(:input_declaration, :output_declaration, :inout_declaration)
+      # Returns an array containing all input, output and inout AST nodes.
+      # Supply analog: true in the options to return only those pins defined as a
+      # real/wreal type and digital: true to return only the pins without a real/wreal
+      # type.
+      def pins(options = {})
+        pins = find_all(:input_declaration, :output_declaration, :inout_declaration)
+        if options[:analog] || options[:digital]
+          wreals = self.wreals.map { |n| n.to_a.last }
+          subset = []
+          pins.each do |pin|
+            attrs = pin.to_a
+            if attrs.include?('real') || wreals.include?(attrs.last)
+              subset << pin if options[:analog]
+            else
+              subset << pin if options[:digital]
+            end
+          end
+          subset
+        else
+          pins
+        end
+      end
+
+      # Returns an array containing all wire real/wreal declaration AST nodes, which have
+      # been declared as part of a module definition, returning something like this:
+      #       [
+      #         s(:net_declaration, "real", "vdd")),
+      #         s(:net_declaration, "real", "vddf")),
+      #       ]
+      def wreals
+        find_all(:non_port_module_item)
+          .map { |item| item.find(:net_declaration) }
+          .select { |net| net.to_a.include?('real') }
       end
 
       # Evaluates all functions and turns numbers into Ruby literals

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_verilog
 version: !ruby/object:Gem::Version
-  version: 0.5.2
+  version: 0.6.0
 platform: ruby
 authors:
 - Stephen McGinty
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2018-12-20 00:00:00.000000000 Z
+date: 2019-05-16 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen
@@ -59,7 +59,6 @@ executables: []
 extensions: []
 extra_rdoc_files: []
 files:
-- bin/fix_my_workspace
 - config/application.rb
 - config/boot.rb
 - config/commands.rb

data/bin/fix_my_workspace

@@ -1,100 +0,0 @@
-#!/usr/bin/env ruby
-$VERBOSE = nil  # Don't care about world writable dir warnings and the like
-
-if $_fix_my_workspace_version_check
-  $_fix_my_workspace_version = '0.7.0'
-else
-  if File.exist?(File.expand_path('../../lib/origen.rb', __FILE__))
-    # If this script is being run from within an origen-core workspace, use that Origen-core,
-    # not the system-installed origen-core version.
-    $LOAD_PATH.unshift(File.expand_path('../../lib', __FILE__))
-    require 'origen'
-  else
-    # Use system-installed Origen (the gem in system Ruby)
-    require 'origen'
-  end
-
-  if !Origen.site_config.gem_manage_bundler
-    puts 'Sorry but you have opted to manage Bundler yourself via your Origen site config, and this means'
-    puts 'that I cannot make certain assumptions about how your workspace is configured.'
-    puts 'You will need to either resolve this problem yourself, or else change the value of'
-    puts 'gem_mange_bundler to true.'
-    puts 'See here for more details on how to do that: http://origen-sdk.org/origen/guides/starting/company/'
-
-  else
-    ENV['BUNDLE_GEMFILE'] = File.join(Origen.root, 'Gemfile')
-    ENV['BUNDLE_PATH'] = File.expand_path(Origen.site_config.gem_install_dir)
-    ENV['BUNDLE_BIN'] = File.join(Origen.root, 'lbin')
-
-    # Force copy system gems to local gems
-    if Origen.site_config.gem_use_from_system
-      local_gem_dir = "#{ENV['BUNDLE_PATH']}/ruby/#{Pathname.new(Gem.dir).basename}"
-      gem_dir = Pathname.new(Gem.dir)
-
-      Origen.site_config.gem_use_from_system.each do |gem, version|
-        begin
-          # This will raise an error if the system doesn't have this gem installed, that
-          # will be rescued below
-          spec = Gem::Specification.find_by_name(gem, version)
-
-          local_dir = File.join(local_gem_dir, Pathname.new(spec.gem_dir).relative_path_from(gem_dir))
-          FileUtils.mkdir_p local_dir
-          FileUtils.cp_r("#{spec.gem_dir}/.", local_dir)
-
-          local_file = Pathname.new(File.join(local_gem_dir, Pathname.new(spec.cache_file).relative_path_from(gem_dir)))
-          FileUtils.mkdir_p local_file.dirname
-          FileUtils.cp(spec.cache_file, local_file)
-
-          if spec.extension_dir && File.exist?(spec.extension_dir)
-            local_dir = File.join(local_gem_dir, Pathname.new(spec.extension_dir).relative_path_from(gem_dir))
-            FileUtils.mkdir_p local_dir
-            FileUtils.cp_r("#{spec.extension_dir}/.", local_dir)
-          end
-
-          local_file = Pathname.new(File.join(local_gem_dir, Pathname.new(spec.spec_file).relative_path_from(gem_dir)))
-          FileUtils.mkdir_p local_file.dirname
-          FileUtils.cp(spec.spec_file, local_file)
-
-        rescue Gem::LoadError
-          # This just means that one of the gems that should be copied from the system
-          # was not actually installed in the system, so nothing we can do about that here
-        end
-      end
-    end
-
-    # Delete lbin
-    FileUtils.rm_rf(ENV['BUNDLE_BIN']) if File.exist?(ENV['BUNDLE_BIN'])
-
-    # Run bundler with correct switches
-    cmd = "bundle install --gemfile #{ENV['BUNDLE_GEMFILE']} --binstubs #{ENV['BUNDLE_BIN']} --path #{ENV['BUNDLE_PATH']}"
-    `chmod o-w #{Origen.root}` # Stops some annoying world writable warnings during install
-    `chmod o-w #{Origen.root}/bin` if File.exist?("#{Origen.root}/bin")
-    `chmod o-w #{Origen.root}/.bin` if File.exist?("#{Origen.root}/.bin")
-
-    # Try again, this time updating the bundle
-    if system(cmd)
-      fixed = true
-    elsif system 'bundle update'
-      fixed = true
-    end
-
-    if File.exist?(ENV['BUNDLE_BIN'])
-      `chmod o-w #{ENV['BUNDLE_BIN']}`
-
-      # Make .bat versions of all executables, Bundler should really be doing this when running
-      # on windows
-      if Origen.os.windows?
-        Dir.glob("#{ENV['BUNDLE_BIN']}/*").each do |bin|
-          unless bin =~ /.bat$/
-            bat = "#{bin}.bat"
-            unless File.exist?(bat)
-              File.open(bat, 'w') { |f| f.write('@"ruby.exe" "%~dpn0" %*') }
-            end
-          end
-        end
-      end
-    end
-
-    system 'origen -v' if fixed
-  end
-end