origen_verilog 0.3.1 → 0.4.0

checksums.yaml

@@ -1,7 +1,7 @@
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-  data.tar.gz: d0d8602e57ecb3eeb04d1dbd0919bb3d36f7a252
+  metadata.gz: 8b7dad778fe01bd22327effb341d610473fa6055
+  data.tar.gz: fb333cbca3fe65cd169c8f09649249dd513082f6
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+  data.tar.gz: da51975ae2e00244dd8f2b930a85c1ae9cd301057c8b419af007d03754f9c7717484f8f0ad2ab5d94a130ba709d89a9ab898ed5c86017054308bd72030a6276a

data/config/version.rb

@@ -1,7 +1,7 @@
 module OrigenVerilog
   MAJOR = 0
-  MINOR = 3
-  BUGFIX = 1
+  MINOR = 4
+  BUGFIX = 0
   DEV = nil
 
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')

data/grammars/preprocessor.rb

@@ -2094,15 +2094,15 @@ module OrigenVerilog
 
       module IfdefDirective3
         def to_ast
-          node = n :ifdef, label.text_value, *elements_to_ast(contents.elements)
+          node = n :ifdef, label.text_value, *elements_to_ast(contents.elements), number_of_lines: number_of_lines(contents.elements)
           elsif_nodes.elements.each do |elsif_node|
             if elsif_node.respond_to?(:contents)
-              e = n :elsif, elsif_node.label.text_value, *elements_to_ast(elsif_node.contents.elements)
+              e = n :elsif, elsif_node.label.text_value, *elements_to_ast(elsif_node.contents.elements), number_of_lines: number_of_lines(elsif_node.contents.elements)
               node = node.updated(nil, node.children + [e])
             end
           end
           if else_node.respond_to?(:contents)
-            node = node.updated(nil, node.children + [n(:else, *elements_to_ast(else_node.contents.elements))])
+            node = node.updated(nil, node.children + [n(:else, *elements_to_ast(else_node.contents.elements), number_of_lines: number_of_lines(else_node.contents.elements))])
           end
           node
         end
@@ -2397,15 +2397,15 @@ module OrigenVerilog
 
       module IfndefDirective3
         def to_ast
-          node = n :ifndef, label.text_value, *elements_to_ast(contents.elements)
+          node = n :ifndef, label.text_value, *elements_to_ast(contents.elements), number_of_lines: number_of_lines(contents.elements)
           elsif_nodes.elements.each do |elsif_node|
             if elsif_node.respond_to?(:contents)
-              e = n :elsif, elsif_node.label.text_value, *elements_to_ast(elsif_node.contents.elements)
+              e = n :elsif, elsif_node.label.text_value, *elements_to_ast(elsif_node.contents.elements), number_of_lines: number_of_lines(elsif_node.contents.elements)
               node = node.updated(nil, node.children + [e])
             end
           end
           if else_node.respond_to?(:contents)
-            node = node.updated(nil, node.children + [n(:else, *elements_to_ast(else_node.contents.elements))])
+            node = node.updated(nil, node.children + [n(:else, *elements_to_ast(else_node.contents.elements), number_of_lines: number_of_lines(else_node.contents.elements))])
           end
           node
         end

data/grammars/verilog.rb

@@ -5450,46 +5450,28 @@ module OrigenVerilog
       end
 
       module InputDeclaration0
-        def S
-          elements[0]
-        end
-
-        def net_type
-          elements[1]
-        end
-      end
-
-      module InputDeclaration1
-        def S
-          elements[0]
-        end
-
-        def signed
+        def s1
           elements[1]
         end
-      end
 
-      module InputDeclaration2
-        def S
-          elements[0]
+        def s2
+          elements[3]
         end
 
-        def range
-          elements[1]
+        def s3
+          elements[5]
         end
-      end
 
-      module InputDeclaration3
-        def S
-          elements[4]
+        def s4
+          elements[7]
         end
 
         def list_of_port_identifiers
-          elements[5]
+          elements[8]
         end
       end
 
-      module InputDeclaration4
+      module InputDeclaration1
         def to_ast
           n :input_declaration, *elements_to_ast
         end
@@ -5516,74 +5498,47 @@ module OrigenVerilog
         end
         s0 << r1
         if r1
-          i3, s3 = index, []
-          r4 = _nt_S
-          s3 << r4
-          if r4
-            r5 = _nt_net_type
-            s3 << r5
-          end
-          if s3.last
-            r3 = instantiate_node(SyntaxNode,input, i3...index, s3)
-            r3.extend(InputDeclaration0)
-          else
-            @index = i3
-            r3 = nil
-          end
-          if r3
-            r2 = r3
-          else
-            r2 = instantiate_node(SyntaxNode,input, index...index)
-          end
+          r2 = _nt_s
           s0 << r2
           if r2
-            i7, s7 = index, []
-            r8 = _nt_S
-            s7 << r8
-            if r8
-              r9 = _nt_signed
-              s7 << r9
-            end
-            if s7.last
-              r7 = instantiate_node(SyntaxNode,input, i7...index, s7)
-              r7.extend(InputDeclaration1)
-            else
-              @index = i7
-              r7 = nil
-            end
-            if r7
-              r6 = r7
+            r4 = _nt_net_type
+            if r4
+              r3 = r4
             else
-              r6 = instantiate_node(SyntaxNode,input, index...index)
+              r3 = instantiate_node(SyntaxNode,input, index...index)
             end
-            s0 << r6
-            if r6
-              i11, s11 = index, []
-              r12 = _nt_S
-              s11 << r12
-              if r12
-                r13 = _nt_range
-                s11 << r13
-              end
-              if s11.last
-                r11 = instantiate_node(SyntaxNode,input, i11...index, s11)
-                r11.extend(InputDeclaration2)
-              else
-                @index = i11
-                r11 = nil
-              end
-              if r11
-                r10 = r11
-              else
-                r10 = instantiate_node(SyntaxNode,input, index...index)
-              end
-              s0 << r10
-              if r10
-                r14 = _nt_S
-                s0 << r14
-                if r14
-                  r15 = _nt_list_of_port_identifiers
-                  s0 << r15
+            s0 << r3
+            if r3
+              r5 = _nt_s
+              s0 << r5
+              if r5
+                r7 = _nt_signed
+                if r7
+                  r6 = r7
+                else
+                  r6 = instantiate_node(SyntaxNode,input, index...index)
+                end
+                s0 << r6
+                if r6
+                  r8 = _nt_s
+                  s0 << r8
+                  if r8
+                    r10 = _nt_range
+                    if r10
+                      r9 = r10
+                    else
+                      r9 = instantiate_node(SyntaxNode,input, index...index)
+                    end
+                    s0 << r9
+                    if r9
+                      r11 = _nt_s
+                      s0 << r11
+                      if r11
+                        r12 = _nt_list_of_port_identifiers
+                        s0 << r12
+                      end
+                    end
+                  end
                 end
               end
             end
@@ -5591,8 +5546,8 @@ module OrigenVerilog
         end
         if s0.last
           r0 = instantiate_node(SyntaxNode,input, i0...index, s0)
-          r0.extend(InputDeclaration3)
-          r0.extend(InputDeclaration4)
+          r0.extend(InputDeclaration0)
+          r0.extend(InputDeclaration1)
         else
           @index = i0
           r0 = nil
@@ -9659,14 +9614,18 @@ module OrigenVerilog
       end
 
       module ListOfNetIdentifiers2
-        def s
+        def s1
           elements[0]
         end
 
-        def net_identifier
+        def s2
           elements[2]
         end
 
+        def net_identifier
+          elements[3]
+        end
+
       end
 
       module ListOfNetIdentifiers3
@@ -9731,33 +9690,37 @@ module OrigenVerilog
                 end
                 s7 << r9
                 if r9
-                  r10 = _nt_net_identifier
+                  r10 = _nt_s
                   s7 << r10
                   if r10
-                    s11, i11 = [], index
-                    loop do
-                      i12, s12 = index, []
-                      r13 = _nt_s
-                      s12 << r13
-                      if r13
-                        r14 = _nt_dimension
-                        s12 << r14
-                      end
-                      if s12.last
-                        r12 = instantiate_node(SyntaxNode,input, i12...index, s12)
-                        r12.extend(ListOfNetIdentifiers1)
-                      else
-                        @index = i12
-                        r12 = nil
-                      end
-                      if r12
-                        s11 << r12
-                      else
-                        break
+                    r11 = _nt_net_identifier
+                    s7 << r11
+                    if r11
+                      s12, i12 = [], index
+                      loop do
+                        i13, s13 = index, []
+                        r14 = _nt_s
+                        s13 << r14
+                        if r14
+                          r15 = _nt_dimension
+                          s13 << r15
+                        end
+                        if s13.last
+                          r13 = instantiate_node(SyntaxNode,input, i13...index, s13)
+                          r13.extend(ListOfNetIdentifiers1)
+                        else
+                          @index = i13
+                          r13 = nil
+                        end
+                        if r13
+                          s12 << r13
+                        else
+                          break
+                        end
                       end
+                      r12 = instantiate_node(SyntaxNode,input, i12...index, s12)
+                      s7 << r12
                     end
-                    r11 = instantiate_node(SyntaxNode,input, i11...index, s11)
-                    s7 << r11
                   end
                 end
               end
@@ -13166,15 +13129,15 @@ module OrigenVerilog
       end
 
       module TfInputDeclaration0
-        def S
+        def s1
           elements[1]
         end
 
-        def s1
+        def s2
           elements[3]
         end
 
-        def s2
+        def s3
           elements[6]
         end
 
@@ -13184,7 +13147,7 @@ module OrigenVerilog
       end
 
       module TfInputDeclaration1
-        def S
+        def s1
           elements[1]
         end
 
@@ -13192,7 +13155,7 @@ module OrigenVerilog
           elements[2]
         end
 
-        def s
+        def s2
           elements[3]
         end
 
@@ -13229,7 +13192,7 @@ module OrigenVerilog
         end
         s1 << r2
         if r2
-          r3 = _nt_S
+          r3 = _nt_s
           s1 << r3
           if r3
             r5 = _nt_reg
@@ -13294,7 +13257,7 @@ module OrigenVerilog
           end
           s13 << r14
           if r14
-            r15 = _nt_S
+            r15 = _nt_s
             s13 << r15
             if r15
               r16 = _nt_task_port_type
@@ -13333,19 +13296,19 @@ module OrigenVerilog
       end
 
       module TfOutputDeclaration0
-        def S
+        def s1
           elements[1]
         end
 
-        def s1
+        def s2
           elements[3]
         end
 
-        def s2
+        def s3
           elements[5]
         end
 
-        def s3
+        def s4
           elements[7]
         end
 
@@ -13355,7 +13318,7 @@ module OrigenVerilog
       end
 
       module TfOutputDeclaration1
-        def S
+        def s1
           elements[1]
         end
 
@@ -13363,7 +13326,7 @@ module OrigenVerilog
           elements[2]
         end
 
-        def s
+        def s2
           elements[3]
         end
 
@@ -13400,7 +13363,7 @@ module OrigenVerilog
         end
         s1 << r2
         if r2
-          r3 = _nt_S
+          r3 = _nt_s
           s1 << r3
           if r3
             r5 = _nt_reg
@@ -13469,7 +13432,7 @@ module OrigenVerilog
           end
           s14 << r15
           if r15
-            r16 = _nt_S
+            r16 = _nt_s
             s14 << r16
             if r16
               r17 = _nt_task_port_type
@@ -13508,19 +13471,19 @@ module OrigenVerilog
       end
 
       module TfInoutDeclaration0
-        def S
+        def s1
           elements[1]
         end
 
-        def s1
+        def s2
           elements[3]
         end
 
-        def s2
+        def s3
           elements[5]
         end
 
-        def s3
+        def s4
           elements[7]
         end
 
@@ -13530,7 +13493,7 @@ module OrigenVerilog
       end
 
       module TfInoutDeclaration1
-        def S
+        def s1
           elements[1]
         end
 
@@ -13538,7 +13501,7 @@ module OrigenVerilog
           elements[2]
         end
 
-        def s
+        def s2
           elements[3]
         end
 
@@ -13575,7 +13538,7 @@ module OrigenVerilog
         end
         s1 << r2
         if r2
-          r3 = _nt_S
+          r3 = _nt_s
           s1 << r3
           if r3
             r5 = _nt_reg
@@ -13644,7 +13607,7 @@ module OrigenVerilog
           end
           s14 << r15
           if r15
-            r16 = _nt_S
+            r16 = _nt_s
             s14 << r16
             if r16
               r17 = _nt_task_port_type
@@ -40792,6 +40755,12 @@ module OrigenVerilog
 
       end
 
+      module ConstantExpression3
+        def to_ast
+          n :constant_expression, *elements_to_ast
+        end
+      end
+
       def _nt_constant_expression
         start_index = index
         if node_cache[:constant_expression].has_key?(index)
@@ -40860,6 +40829,8 @@ module OrigenVerilog
         if r1
           r1 = SyntaxNode.new(input, (index-1)...index) if r1 == true
           r0 = r1
+          r0.extend(ConstantExpression3)
+          r0.extend(ConstantExpression3)
         else
           i11, s11 = index, []
           r12 = _nt_constant_primary
@@ -40883,6 +40854,8 @@ module OrigenVerilog
           if r11
             r11 = SyntaxNode.new(input, (index-1)...index) if r11 == true
             r0 = r11
+            r0.extend(ConstantExpression3)
+            r0.extend(ConstantExpression3)
           else
             @index = i0
             r0 = nil
@@ -41681,11 +41654,11 @@ module OrigenVerilog
       end
 
       module ExpressionTail3
-        def S
+        def s1
           elements[0]
         end
 
-        def s1
+        def s2
           elements[3]
         end
 
@@ -41693,11 +41666,11 @@ module OrigenVerilog
           elements[4]
         end
 
-        def s2
+        def s3
           elements[5]
         end
 
-        def s3
+        def s4
           elements[7]
         end
 
@@ -41781,7 +41754,7 @@ module OrigenVerilog
           r0 = r1
         else
           i12, s12 = index, []
-          r13 = _nt_S
+          r13 = _nt_s
           s12 << r13
           if r13
             if (match_len = has_terminal?("?", false, index))
@@ -48639,57 +48612,33 @@ module OrigenVerilog
 
         i0, s0 = index, []
         i1 = index
-        if (match_len = has_terminal?('inout ', false, index))
-          r2 = instantiate_node(SyntaxNode,input, index...(index + match_len))
-          @index += match_len
-        else
-          terminal_parse_failure('\'inout \'')
-          r2 = nil
-        end
+        r2 = _nt_inout_declaration
         if r2
           @index = i1
           r1 = nil
-          terminal_parse_failure('\'inout \'', true)
         else
-          @terminal_failures.pop
           @index = i1
           r1 = instantiate_node(SyntaxNode,input, index...index)
         end
         s0 << r1
         if r1
           i3 = index
-          if (match_len = has_terminal?('input ', false, index))
-            r4 = instantiate_node(SyntaxNode,input, index...(index + match_len))
-            @index += match_len
-          else
-            terminal_parse_failure('\'input \'')
-            r4 = nil
-          end
+          r4 = _nt_input_declaration
           if r4
             @index = i3
             r3 = nil
-            terminal_parse_failure('\'input \'', true)
           else
-            @terminal_failures.pop
             @index = i3
             r3 = instantiate_node(SyntaxNode,input, index...index)
           end
           s0 << r3
           if r3
             i5 = index
-            if (match_len = has_terminal?('output ', false, index))
-              r6 = instantiate_node(SyntaxNode,input, index...(index + match_len))
-              @index += match_len
-            else
-              terminal_parse_failure('\'output \'')
-              r6 = nil
-            end
+            r6 = _nt_output_declaration
             if r6
               @index = i5
               r5 = nil
-              terminal_parse_failure('\'output \'', true)
             else
-              @terminal_failures.pop
               @index = i5
               r5 = instantiate_node(SyntaxNode,input, index...index)
             end
@@ -48752,11 +48701,11 @@ module OrigenVerilog
         end
 
         i0, s0 = index, []
-        if has_terminal?(@regexps[gr = '\A[a-zA-Z]'] ||= Regexp.new(gr), :regexp, index)
+        if has_terminal?(@regexps[gr = '\A[a-zA-Z_]'] ||= Regexp.new(gr), :regexp, index)
           r1 = true
           @index += 1
         else
-          terminal_parse_failure('[a-zA-Z]')
+          terminal_parse_failure('[a-zA-Z_]')
           r1 = nil
         end
         s0 << r1

data/lib/origen_verilog.rb

@@ -22,17 +22,40 @@ module OrigenVerilog
     autoload :Node,      'origen_verilog/preprocessor/node'
     autoload :Processor, 'origen_verilog/preprocessor/processor'
     autoload :Writer,    'origen_verilog/preprocessor/writer'
+    autoload :Concatenator, 'origen_verilog/preprocessor/contatenator'
+    autoload :VerilogParser, 'origen_verilog/preprocessor/verilog_parser'
   end
 
   # Returns an AST for the given file
-  def self.parse_file(file, options = {})
-    top_dir = Pathname.new(file).dirname
+  def self.parse_file(files, options = {})
+    # Assume if multiple files are given, then the last one is the main one to parse, treat those
+    # given up front as equivalent to including them within the main file via a compiler directive
+    files = files.split(/\s/)
+    file = files.pop
+
+    top_dir = Pathname.new(file).dirname.to_s
     options[:source_dirs] ||= []
     options[:source_dirs] << top_dir unless options[:source_dirs].include?(top_dir)
-    # Evaluates all compiler directives
-    ast = Preprocessor::Parser.parse_file(file, options).process(options)
 
-    # Now parse as verilog
-    Verilog::Parser.parse(ast.to_s, options)
+    # Read in the file to a pre-processor AST (Verilog captured as blocks of text at this point)
+    ast = Preprocessor::Parser.parse_file(file, options)
+    unless files.empty?
+      files.each do |f|
+        ast = ast.updated(nil, [ast.updated(:include, [f])] + ast.children)
+      end
+    end
+
+    Array(options[:defines]).each do |define|
+      name, text = *define.split('=')
+      name = ast.updated(:name, [name])
+      nodes = [name]
+      nodes << ast.updated(:text, [text]) if text
+      ast = ast.updated(nil, [ast.updated(:define, nodes)] + ast.children)
+    end
+
+    # Evaluate all compiler directives
+    ast = ast.process(options)
+    # Now parse as Verilog
+    ast = ast.parse_verilog(options.merge(file: file))
   end
 end

data/lib/origen_verilog/node.rb

@@ -2,7 +2,7 @@ require 'ast'
 require 'treetop'
 module OrigenVerilog
   class Node < ::AST::Node
-    attr_reader :input, :interval, :file
+    attr_reader :input, :interval, :file, :number_of_lines
 
     # Returns the value at the root of an AST node like this:
     #
@@ -94,7 +94,7 @@ module Treetop
         properties[:input] ||= input
         properties[:interval] ||= interval
         properties[:file] ||= file
-        Treetop.origen_verilog_parser.node.new(type, children, properties || {})
+        Treetop.origen_verilog_parser.node.new(type, children, properties)
       end
 
       def elements_to_ast(elmnts = elements)
@@ -107,6 +107,13 @@ module Treetop
         end.compact.flatten
       end
 
+      def number_of_lines(elmnts = elements)
+        elmnts.inject(0) do |sum, e|
+          lines = e.text_value.split("\n").size
+          sum + lines
+        end
+      end
+
       def file
         Treetop.origen_verilog_parser.file
       end

data/lib/origen_verilog/preprocessor/contatenator.rb

@@ -0,0 +1,38 @@
+module OrigenVerilog
+  module Preprocessor
+    # Concatenates all text_block nodes
+    class Concatenator < OrigenVerilog::Processor
+      def run(node)
+        @text_block = nil
+        nodes = process_all(node.children)
+        nodes << @text_block if @text_block
+        node.updated(nil, nodes)
+      end
+
+      def on_text_block(node)
+        if @text_block
+          @text_block = @text_block.updated(:text_block, [@text_block.to_a[0] + node.to_a[0]])
+        else
+          @text_block = node
+        end
+        nil
+      end
+      alias_method :on_comment, :on_text_block
+
+      def on_file(node)
+        node = Concatenator.new.run(node)
+        if @text_block
+          tb = @text_block
+          @text_block = nil
+          inline [tb, node]
+        else
+          node
+        end
+      end
+
+      def handler_missing(node)
+        fail "No handler defined for node type: #{node.type}"
+      end
+    end
+  end
+end

data/lib/origen_verilog/preprocessor/node.rb

@@ -14,6 +14,10 @@ module OrigenVerilog
       def to_s
         Writer.new.to_s(self)
       end
+
+      def parse_verilog(options = {})
+        VerilogParser.new.run(self, options)
+      end
     end
   end
 end

data/lib/origen_verilog/preprocessor/processor.rb

@@ -3,7 +3,8 @@ module OrigenVerilog
     class Processor < OrigenVerilog::Processor
       def run(ast, env)
         @env = env
-        process(ast)
+        ast = process(ast)
+        Concatenator.new.run(ast)
       end
 
       def on_include(node)
@@ -21,7 +22,8 @@ module OrigenVerilog
           puts "#{node.file}:#{node.line_number}"
           exit 1
         end
-        inline process(Parser.parse_file(file)).children
+        nodes = process(Parser.parse_file(file)).children
+        node.updated(:file, [file] + nodes)
       end
 
       def on_define(node)
@@ -45,19 +47,44 @@ module OrigenVerilog
         elsif_nodes = node.find_all(:elsif)
         else_node = node.find(:else)
         enable, *nodes = *node
+
+        # The number of lines needs to be tracked here and blank lines (nil) are injected in place
+        # of un-enabled ifdef branches so that the source file line numbers will be reported correctly
+        # later in the Verilog parse stage
+        prelines = 0
+        postlines = 0
+
         if node.type == :ifdef ? env[enable] : !env[enable]
-          inline(process_all(nodes))
+          content = process_all(nodes)
         else
-          elsif_nodes.each do |elsif_node|
-            enable, *nodes = *elsif_node
-            if env[enable]
-              return inline(process_all(nodes))
+          prelines += node.number_of_lines + 1
+        end
+
+        elsif_nodes.each do |elsif_node|
+          enable, *nodes = *elsif_node
+          if !content && env[enable]
+            content = process_all(nodes)
+          else
+            if content
+              postlines += elsif_node.number_of_lines + 1
+            else
+              prelines += elsif_node.number_of_lines + 1
             end
           end
-          if else_node
-            inline(process_all(else_node.children))
+        end
+
+        if else_node
+          if content
+            postlines += else_node.number_of_lines + 1
+          else
+            content = process_all(else_node.children)
           end
         end
+
+        prelines = node.updated(:text_block, ["\n" * prelines])
+        postlines = node.updated(:text_block, ["\n" * postlines])
+
+        inline([prelines] + (content || []) + [postlines])
       end
       alias_method :on_ifndef, :on_ifdef
 

data/lib/origen_verilog/preprocessor/verilog_parser.rb

@@ -0,0 +1,32 @@
+module OrigenVerilog
+  module Preprocessor
+    # Invokes the Verilog parser on all text_block nodes, transforming the
+    # given pre-processor output AST into a Verilog AST
+    class VerilogParser < OrigenVerilog::Processor
+      def run(node, options = {})
+        @nodes = []
+        @file = options[:file]
+        @options = options
+        process_all(node.children)
+        Verilog::Node.new(:verilog_source, @nodes, file: @file)
+      end
+
+      def on_text_block(node)
+        node = Verilog::Parser.parse(node.to_a[0], @options.merge(file: @file))
+        @nodes += node.children
+        nil
+      end
+
+      def on_file(node)
+        file, *nodes = *node
+        node = VerilogParser.new.run(node.updated(nil, nodes), @options.merge(file: file))
+        @nodes += node.children
+        nil
+      end
+
+      def handler_missing(node)
+        fail "No handler defined for node type: #{node.type}"
+      end
+    end
+  end
+end

data/lib/origen_verilog/verilog/evaluator.rb

@@ -5,6 +5,13 @@ module OrigenVerilog
         ast.updated(nil, process_all(ast.children))
       end
 
+      def on_constant_expression(node)
+        nodes = process_all(node.children)
+        nodes = nodes.map { |n| n.is_a?(Node) ? process(n.value) : n }
+        # Ruby should be close enough to Verilog to just eval the expression for most cases
+        eval(nodes.join(' '))
+      end
+
       def on_decimal_number(node)
         process(node.value)
       end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_verilog
 version: !ruby/object:Gem::Version
-  version: 0.3.1
+  version: 0.4.0
 platform: ruby
 authors:
 - Stephen McGinty
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2018-02-06 00:00:00.000000000 Z
+date: 2018-06-18 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: ast
@@ -56,9 +56,11 @@ files:
 - lib/origen_verilog/commands/parse.rb
 - lib/origen_verilog/node.rb
 - lib/origen_verilog/parser.rb
+- lib/origen_verilog/preprocessor/contatenator.rb
 - lib/origen_verilog/preprocessor/node.rb
 - lib/origen_verilog/preprocessor/parser.rb
 - lib/origen_verilog/preprocessor/processor.rb
+- lib/origen_verilog/preprocessor/verilog_parser.rb
 - lib/origen_verilog/preprocessor/writer.rb
 - lib/origen_verilog/processor.rb
 - lib/origen_verilog/top_level.rb
@@ -91,7 +93,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
       version: 1.8.11
 requirements: []
 rubyforge_project: 
-rubygems_version: 2.6.7
+rubygems_version: 2.6.14.1
 signing_key: 
 specification_version: 4
 summary: A parser and generator for Verilog (IEEE 1364)