origen_verilog 0.3.1 → 0.4.0

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checksums.yaml CHANGED
@@ -1,7 +1,7 @@
1
1
  ---
2
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  SHA1:
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- metadata.gz: 1be3a1740eb02ddf52433ffdf8d3b6eb3ca30657
4
- data.tar.gz: d0d8602e57ecb3eeb04d1dbd0919bb3d36f7a252
3
+ metadata.gz: 8b7dad778fe01bd22327effb341d610473fa6055
4
+ data.tar.gz: fb333cbca3fe65cd169c8f09649249dd513082f6
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  SHA512:
6
- metadata.gz: 7c4f3a008af2790d2479c594f5cb777fa7903fea17df2f1ad3daa1df728bf52e9ec498baaaf1ce5867c4aa7027b8ffb96c2eaa90475236af1f687d4a75de9036
7
- data.tar.gz: a2468d8aeb390439016a517c1eb5bd55707f0c2bfa1addbcc801e69a88fdfdc07650600da81194c64806406ce0a30b221be9074397120398e21017494c26a72b
6
+ metadata.gz: 407c5b505e66c4f1b351862e200ee6c328882a98f87948431d3564031f5bbd2b0d57d6c3b962870ba1f59f591ae218339cc872eeabe02e3544cc51ebaf133e7a
7
+ data.tar.gz: da51975ae2e00244dd8f2b930a85c1ae9cd301057c8b419af007d03754f9c7717484f8f0ad2ab5d94a130ba709d89a9ab898ed5c86017054308bd72030a6276a
@@ -1,7 +1,7 @@
1
1
  module OrigenVerilog
2
2
  MAJOR = 0
3
- MINOR = 3
4
- BUGFIX = 1
3
+ MINOR = 4
4
+ BUGFIX = 0
5
5
  DEV = nil
6
6
 
7
7
  VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
@@ -2094,15 +2094,15 @@ module OrigenVerilog
2094
2094
 
2095
2095
  module IfdefDirective3
2096
2096
  def to_ast
2097
- node = n :ifdef, label.text_value, *elements_to_ast(contents.elements)
2097
+ node = n :ifdef, label.text_value, *elements_to_ast(contents.elements), number_of_lines: number_of_lines(contents.elements)
2098
2098
  elsif_nodes.elements.each do |elsif_node|
2099
2099
  if elsif_node.respond_to?(:contents)
2100
- e = n :elsif, elsif_node.label.text_value, *elements_to_ast(elsif_node.contents.elements)
2100
+ e = n :elsif, elsif_node.label.text_value, *elements_to_ast(elsif_node.contents.elements), number_of_lines: number_of_lines(elsif_node.contents.elements)
2101
2101
  node = node.updated(nil, node.children + [e])
2102
2102
  end
2103
2103
  end
2104
2104
  if else_node.respond_to?(:contents)
2105
- node = node.updated(nil, node.children + [n(:else, *elements_to_ast(else_node.contents.elements))])
2105
+ node = node.updated(nil, node.children + [n(:else, *elements_to_ast(else_node.contents.elements), number_of_lines: number_of_lines(else_node.contents.elements))])
2106
2106
  end
2107
2107
  node
2108
2108
  end
@@ -2397,15 +2397,15 @@ module OrigenVerilog
2397
2397
 
2398
2398
  module IfndefDirective3
2399
2399
  def to_ast
2400
- node = n :ifndef, label.text_value, *elements_to_ast(contents.elements)
2400
+ node = n :ifndef, label.text_value, *elements_to_ast(contents.elements), number_of_lines: number_of_lines(contents.elements)
2401
2401
  elsif_nodes.elements.each do |elsif_node|
2402
2402
  if elsif_node.respond_to?(:contents)
2403
- e = n :elsif, elsif_node.label.text_value, *elements_to_ast(elsif_node.contents.elements)
2403
+ e = n :elsif, elsif_node.label.text_value, *elements_to_ast(elsif_node.contents.elements), number_of_lines: number_of_lines(elsif_node.contents.elements)
2404
2404
  node = node.updated(nil, node.children + [e])
2405
2405
  end
2406
2406
  end
2407
2407
  if else_node.respond_to?(:contents)
2408
- node = node.updated(nil, node.children + [n(:else, *elements_to_ast(else_node.contents.elements))])
2408
+ node = node.updated(nil, node.children + [n(:else, *elements_to_ast(else_node.contents.elements), number_of_lines: number_of_lines(else_node.contents.elements))])
2409
2409
  end
2410
2410
  node
2411
2411
  end
@@ -5450,46 +5450,28 @@ module OrigenVerilog
5450
5450
  end
5451
5451
 
5452
5452
  module InputDeclaration0
5453
- def S
5454
- elements[0]
5455
- end
5456
-
5457
- def net_type
5458
- elements[1]
5459
- end
5460
- end
5461
-
5462
- module InputDeclaration1
5463
- def S
5464
- elements[0]
5465
- end
5466
-
5467
- def signed
5453
+ def s1
5468
5454
  elements[1]
5469
5455
  end
5470
- end
5471
5456
 
5472
- module InputDeclaration2
5473
- def S
5474
- elements[0]
5457
+ def s2
5458
+ elements[3]
5475
5459
  end
5476
5460
 
5477
- def range
5478
- elements[1]
5461
+ def s3
5462
+ elements[5]
5479
5463
  end
5480
- end
5481
5464
 
5482
- module InputDeclaration3
5483
- def S
5484
- elements[4]
5465
+ def s4
5466
+ elements[7]
5485
5467
  end
5486
5468
 
5487
5469
  def list_of_port_identifiers
5488
- elements[5]
5470
+ elements[8]
5489
5471
  end
5490
5472
  end
5491
5473
 
5492
- module InputDeclaration4
5474
+ module InputDeclaration1
5493
5475
  def to_ast
5494
5476
  n :input_declaration, *elements_to_ast
5495
5477
  end
@@ -5516,74 +5498,47 @@ module OrigenVerilog
5516
5498
  end
5517
5499
  s0 << r1
5518
5500
  if r1
5519
- i3, s3 = index, []
5520
- r4 = _nt_S
5521
- s3 << r4
5522
- if r4
5523
- r5 = _nt_net_type
5524
- s3 << r5
5525
- end
5526
- if s3.last
5527
- r3 = instantiate_node(SyntaxNode,input, i3...index, s3)
5528
- r3.extend(InputDeclaration0)
5529
- else
5530
- @index = i3
5531
- r3 = nil
5532
- end
5533
- if r3
5534
- r2 = r3
5535
- else
5536
- r2 = instantiate_node(SyntaxNode,input, index...index)
5537
- end
5501
+ r2 = _nt_s
5538
5502
  s0 << r2
5539
5503
  if r2
5540
- i7, s7 = index, []
5541
- r8 = _nt_S
5542
- s7 << r8
5543
- if r8
5544
- r9 = _nt_signed
5545
- s7 << r9
5546
- end
5547
- if s7.last
5548
- r7 = instantiate_node(SyntaxNode,input, i7...index, s7)
5549
- r7.extend(InputDeclaration1)
5550
- else
5551
- @index = i7
5552
- r7 = nil
5553
- end
5554
- if r7
5555
- r6 = r7
5504
+ r4 = _nt_net_type
5505
+ if r4
5506
+ r3 = r4
5556
5507
  else
5557
- r6 = instantiate_node(SyntaxNode,input, index...index)
5508
+ r3 = instantiate_node(SyntaxNode,input, index...index)
5558
5509
  end
5559
- s0 << r6
5560
- if r6
5561
- i11, s11 = index, []
5562
- r12 = _nt_S
5563
- s11 << r12
5564
- if r12
5565
- r13 = _nt_range
5566
- s11 << r13
5567
- end
5568
- if s11.last
5569
- r11 = instantiate_node(SyntaxNode,input, i11...index, s11)
5570
- r11.extend(InputDeclaration2)
5571
- else
5572
- @index = i11
5573
- r11 = nil
5574
- end
5575
- if r11
5576
- r10 = r11
5577
- else
5578
- r10 = instantiate_node(SyntaxNode,input, index...index)
5579
- end
5580
- s0 << r10
5581
- if r10
5582
- r14 = _nt_S
5583
- s0 << r14
5584
- if r14
5585
- r15 = _nt_list_of_port_identifiers
5586
- s0 << r15
5510
+ s0 << r3
5511
+ if r3
5512
+ r5 = _nt_s
5513
+ s0 << r5
5514
+ if r5
5515
+ r7 = _nt_signed
5516
+ if r7
5517
+ r6 = r7
5518
+ else
5519
+ r6 = instantiate_node(SyntaxNode,input, index...index)
5520
+ end
5521
+ s0 << r6
5522
+ if r6
5523
+ r8 = _nt_s
5524
+ s0 << r8
5525
+ if r8
5526
+ r10 = _nt_range
5527
+ if r10
5528
+ r9 = r10
5529
+ else
5530
+ r9 = instantiate_node(SyntaxNode,input, index...index)
5531
+ end
5532
+ s0 << r9
5533
+ if r9
5534
+ r11 = _nt_s
5535
+ s0 << r11
5536
+ if r11
5537
+ r12 = _nt_list_of_port_identifiers
5538
+ s0 << r12
5539
+ end
5540
+ end
5541
+ end
5587
5542
  end
5588
5543
  end
5589
5544
  end
@@ -5591,8 +5546,8 @@ module OrigenVerilog
5591
5546
  end
5592
5547
  if s0.last
5593
5548
  r0 = instantiate_node(SyntaxNode,input, i0...index, s0)
5594
- r0.extend(InputDeclaration3)
5595
- r0.extend(InputDeclaration4)
5549
+ r0.extend(InputDeclaration0)
5550
+ r0.extend(InputDeclaration1)
5596
5551
  else
5597
5552
  @index = i0
5598
5553
  r0 = nil
@@ -9659,14 +9614,18 @@ module OrigenVerilog
9659
9614
  end
9660
9615
 
9661
9616
  module ListOfNetIdentifiers2
9662
- def s
9617
+ def s1
9663
9618
  elements[0]
9664
9619
  end
9665
9620
 
9666
- def net_identifier
9621
+ def s2
9667
9622
  elements[2]
9668
9623
  end
9669
9624
 
9625
+ def net_identifier
9626
+ elements[3]
9627
+ end
9628
+
9670
9629
  end
9671
9630
 
9672
9631
  module ListOfNetIdentifiers3
@@ -9731,33 +9690,37 @@ module OrigenVerilog
9731
9690
  end
9732
9691
  s7 << r9
9733
9692
  if r9
9734
- r10 = _nt_net_identifier
9693
+ r10 = _nt_s
9735
9694
  s7 << r10
9736
9695
  if r10
9737
- s11, i11 = [], index
9738
- loop do
9739
- i12, s12 = index, []
9740
- r13 = _nt_s
9741
- s12 << r13
9742
- if r13
9743
- r14 = _nt_dimension
9744
- s12 << r14
9745
- end
9746
- if s12.last
9747
- r12 = instantiate_node(SyntaxNode,input, i12...index, s12)
9748
- r12.extend(ListOfNetIdentifiers1)
9749
- else
9750
- @index = i12
9751
- r12 = nil
9752
- end
9753
- if r12
9754
- s11 << r12
9755
- else
9756
- break
9696
+ r11 = _nt_net_identifier
9697
+ s7 << r11
9698
+ if r11
9699
+ s12, i12 = [], index
9700
+ loop do
9701
+ i13, s13 = index, []
9702
+ r14 = _nt_s
9703
+ s13 << r14
9704
+ if r14
9705
+ r15 = _nt_dimension
9706
+ s13 << r15
9707
+ end
9708
+ if s13.last
9709
+ r13 = instantiate_node(SyntaxNode,input, i13...index, s13)
9710
+ r13.extend(ListOfNetIdentifiers1)
9711
+ else
9712
+ @index = i13
9713
+ r13 = nil
9714
+ end
9715
+ if r13
9716
+ s12 << r13
9717
+ else
9718
+ break
9719
+ end
9757
9720
  end
9721
+ r12 = instantiate_node(SyntaxNode,input, i12...index, s12)
9722
+ s7 << r12
9758
9723
  end
9759
- r11 = instantiate_node(SyntaxNode,input, i11...index, s11)
9760
- s7 << r11
9761
9724
  end
9762
9725
  end
9763
9726
  end
@@ -13166,15 +13129,15 @@ module OrigenVerilog
13166
13129
  end
13167
13130
 
13168
13131
  module TfInputDeclaration0
13169
- def S
13132
+ def s1
13170
13133
  elements[1]
13171
13134
  end
13172
13135
 
13173
- def s1
13136
+ def s2
13174
13137
  elements[3]
13175
13138
  end
13176
13139
 
13177
- def s2
13140
+ def s3
13178
13141
  elements[6]
13179
13142
  end
13180
13143
 
@@ -13184,7 +13147,7 @@ module OrigenVerilog
13184
13147
  end
13185
13148
 
13186
13149
  module TfInputDeclaration1
13187
- def S
13150
+ def s1
13188
13151
  elements[1]
13189
13152
  end
13190
13153
 
@@ -13192,7 +13155,7 @@ module OrigenVerilog
13192
13155
  elements[2]
13193
13156
  end
13194
13157
 
13195
- def s
13158
+ def s2
13196
13159
  elements[3]
13197
13160
  end
13198
13161
 
@@ -13229,7 +13192,7 @@ module OrigenVerilog
13229
13192
  end
13230
13193
  s1 << r2
13231
13194
  if r2
13232
- r3 = _nt_S
13195
+ r3 = _nt_s
13233
13196
  s1 << r3
13234
13197
  if r3
13235
13198
  r5 = _nt_reg
@@ -13294,7 +13257,7 @@ module OrigenVerilog
13294
13257
  end
13295
13258
  s13 << r14
13296
13259
  if r14
13297
- r15 = _nt_S
13260
+ r15 = _nt_s
13298
13261
  s13 << r15
13299
13262
  if r15
13300
13263
  r16 = _nt_task_port_type
@@ -13333,19 +13296,19 @@ module OrigenVerilog
13333
13296
  end
13334
13297
 
13335
13298
  module TfOutputDeclaration0
13336
- def S
13299
+ def s1
13337
13300
  elements[1]
13338
13301
  end
13339
13302
 
13340
- def s1
13303
+ def s2
13341
13304
  elements[3]
13342
13305
  end
13343
13306
 
13344
- def s2
13307
+ def s3
13345
13308
  elements[5]
13346
13309
  end
13347
13310
 
13348
- def s3
13311
+ def s4
13349
13312
  elements[7]
13350
13313
  end
13351
13314
 
@@ -13355,7 +13318,7 @@ module OrigenVerilog
13355
13318
  end
13356
13319
 
13357
13320
  module TfOutputDeclaration1
13358
- def S
13321
+ def s1
13359
13322
  elements[1]
13360
13323
  end
13361
13324
 
@@ -13363,7 +13326,7 @@ module OrigenVerilog
13363
13326
  elements[2]
13364
13327
  end
13365
13328
 
13366
- def s
13329
+ def s2
13367
13330
  elements[3]
13368
13331
  end
13369
13332
 
@@ -13400,7 +13363,7 @@ module OrigenVerilog
13400
13363
  end
13401
13364
  s1 << r2
13402
13365
  if r2
13403
- r3 = _nt_S
13366
+ r3 = _nt_s
13404
13367
  s1 << r3
13405
13368
  if r3
13406
13369
  r5 = _nt_reg
@@ -13469,7 +13432,7 @@ module OrigenVerilog
13469
13432
  end
13470
13433
  s14 << r15
13471
13434
  if r15
13472
- r16 = _nt_S
13435
+ r16 = _nt_s
13473
13436
  s14 << r16
13474
13437
  if r16
13475
13438
  r17 = _nt_task_port_type
@@ -13508,19 +13471,19 @@ module OrigenVerilog
13508
13471
  end
13509
13472
 
13510
13473
  module TfInoutDeclaration0
13511
- def S
13474
+ def s1
13512
13475
  elements[1]
13513
13476
  end
13514
13477
 
13515
- def s1
13478
+ def s2
13516
13479
  elements[3]
13517
13480
  end
13518
13481
 
13519
- def s2
13482
+ def s3
13520
13483
  elements[5]
13521
13484
  end
13522
13485
 
13523
- def s3
13486
+ def s4
13524
13487
  elements[7]
13525
13488
  end
13526
13489
 
@@ -13530,7 +13493,7 @@ module OrigenVerilog
13530
13493
  end
13531
13494
 
13532
13495
  module TfInoutDeclaration1
13533
- def S
13496
+ def s1
13534
13497
  elements[1]
13535
13498
  end
13536
13499
 
@@ -13538,7 +13501,7 @@ module OrigenVerilog
13538
13501
  elements[2]
13539
13502
  end
13540
13503
 
13541
- def s
13504
+ def s2
13542
13505
  elements[3]
13543
13506
  end
13544
13507
 
@@ -13575,7 +13538,7 @@ module OrigenVerilog
13575
13538
  end
13576
13539
  s1 << r2
13577
13540
  if r2
13578
- r3 = _nt_S
13541
+ r3 = _nt_s
13579
13542
  s1 << r3
13580
13543
  if r3
13581
13544
  r5 = _nt_reg
@@ -13644,7 +13607,7 @@ module OrigenVerilog
13644
13607
  end
13645
13608
  s14 << r15
13646
13609
  if r15
13647
- r16 = _nt_S
13610
+ r16 = _nt_s
13648
13611
  s14 << r16
13649
13612
  if r16
13650
13613
  r17 = _nt_task_port_type
@@ -40792,6 +40755,12 @@ module OrigenVerilog
40792
40755
 
40793
40756
  end
40794
40757
 
40758
+ module ConstantExpression3
40759
+ def to_ast
40760
+ n :constant_expression, *elements_to_ast
40761
+ end
40762
+ end
40763
+
40795
40764
  def _nt_constant_expression
40796
40765
  start_index = index
40797
40766
  if node_cache[:constant_expression].has_key?(index)
@@ -40860,6 +40829,8 @@ module OrigenVerilog
40860
40829
  if r1
40861
40830
  r1 = SyntaxNode.new(input, (index-1)...index) if r1 == true
40862
40831
  r0 = r1
40832
+ r0.extend(ConstantExpression3)
40833
+ r0.extend(ConstantExpression3)
40863
40834
  else
40864
40835
  i11, s11 = index, []
40865
40836
  r12 = _nt_constant_primary
@@ -40883,6 +40854,8 @@ module OrigenVerilog
40883
40854
  if r11
40884
40855
  r11 = SyntaxNode.new(input, (index-1)...index) if r11 == true
40885
40856
  r0 = r11
40857
+ r0.extend(ConstantExpression3)
40858
+ r0.extend(ConstantExpression3)
40886
40859
  else
40887
40860
  @index = i0
40888
40861
  r0 = nil
@@ -41681,11 +41654,11 @@ module OrigenVerilog
41681
41654
  end
41682
41655
 
41683
41656
  module ExpressionTail3
41684
- def S
41657
+ def s1
41685
41658
  elements[0]
41686
41659
  end
41687
41660
 
41688
- def s1
41661
+ def s2
41689
41662
  elements[3]
41690
41663
  end
41691
41664
 
@@ -41693,11 +41666,11 @@ module OrigenVerilog
41693
41666
  elements[4]
41694
41667
  end
41695
41668
 
41696
- def s2
41669
+ def s3
41697
41670
  elements[5]
41698
41671
  end
41699
41672
 
41700
- def s3
41673
+ def s4
41701
41674
  elements[7]
41702
41675
  end
41703
41676
 
@@ -41781,7 +41754,7 @@ module OrigenVerilog
41781
41754
  r0 = r1
41782
41755
  else
41783
41756
  i12, s12 = index, []
41784
- r13 = _nt_S
41757
+ r13 = _nt_s
41785
41758
  s12 << r13
41786
41759
  if r13
41787
41760
  if (match_len = has_terminal?("?", false, index))
@@ -48639,57 +48612,33 @@ module OrigenVerilog
48639
48612
 
48640
48613
  i0, s0 = index, []
48641
48614
  i1 = index
48642
- if (match_len = has_terminal?('inout ', false, index))
48643
- r2 = instantiate_node(SyntaxNode,input, index...(index + match_len))
48644
- @index += match_len
48645
- else
48646
- terminal_parse_failure('\'inout \'')
48647
- r2 = nil
48648
- end
48615
+ r2 = _nt_inout_declaration
48649
48616
  if r2
48650
48617
  @index = i1
48651
48618
  r1 = nil
48652
- terminal_parse_failure('\'inout \'', true)
48653
48619
  else
48654
- @terminal_failures.pop
48655
48620
  @index = i1
48656
48621
  r1 = instantiate_node(SyntaxNode,input, index...index)
48657
48622
  end
48658
48623
  s0 << r1
48659
48624
  if r1
48660
48625
  i3 = index
48661
- if (match_len = has_terminal?('input ', false, index))
48662
- r4 = instantiate_node(SyntaxNode,input, index...(index + match_len))
48663
- @index += match_len
48664
- else
48665
- terminal_parse_failure('\'input \'')
48666
- r4 = nil
48667
- end
48626
+ r4 = _nt_input_declaration
48668
48627
  if r4
48669
48628
  @index = i3
48670
48629
  r3 = nil
48671
- terminal_parse_failure('\'input \'', true)
48672
48630
  else
48673
- @terminal_failures.pop
48674
48631
  @index = i3
48675
48632
  r3 = instantiate_node(SyntaxNode,input, index...index)
48676
48633
  end
48677
48634
  s0 << r3
48678
48635
  if r3
48679
48636
  i5 = index
48680
- if (match_len = has_terminal?('output ', false, index))
48681
- r6 = instantiate_node(SyntaxNode,input, index...(index + match_len))
48682
- @index += match_len
48683
- else
48684
- terminal_parse_failure('\'output \'')
48685
- r6 = nil
48686
- end
48637
+ r6 = _nt_output_declaration
48687
48638
  if r6
48688
48639
  @index = i5
48689
48640
  r5 = nil
48690
- terminal_parse_failure('\'output \'', true)
48691
48641
  else
48692
- @terminal_failures.pop
48693
48642
  @index = i5
48694
48643
  r5 = instantiate_node(SyntaxNode,input, index...index)
48695
48644
  end
@@ -48752,11 +48701,11 @@ module OrigenVerilog
48752
48701
  end
48753
48702
 
48754
48703
  i0, s0 = index, []
48755
- if has_terminal?(@regexps[gr = '\A[a-zA-Z]'] ||= Regexp.new(gr), :regexp, index)
48704
+ if has_terminal?(@regexps[gr = '\A[a-zA-Z_]'] ||= Regexp.new(gr), :regexp, index)
48756
48705
  r1 = true
48757
48706
  @index += 1
48758
48707
  else
48759
- terminal_parse_failure('[a-zA-Z]')
48708
+ terminal_parse_failure('[a-zA-Z_]')
48760
48709
  r1 = nil
48761
48710
  end
48762
48711
  s0 << r1
@@ -22,17 +22,40 @@ module OrigenVerilog
22
22
  autoload :Node, 'origen_verilog/preprocessor/node'
23
23
  autoload :Processor, 'origen_verilog/preprocessor/processor'
24
24
  autoload :Writer, 'origen_verilog/preprocessor/writer'
25
+ autoload :Concatenator, 'origen_verilog/preprocessor/contatenator'
26
+ autoload :VerilogParser, 'origen_verilog/preprocessor/verilog_parser'
25
27
  end
26
28
 
27
29
  # Returns an AST for the given file
28
- def self.parse_file(file, options = {})
29
- top_dir = Pathname.new(file).dirname
30
+ def self.parse_file(files, options = {})
31
+ # Assume if multiple files are given, then the last one is the main one to parse, treat those
32
+ # given up front as equivalent to including them within the main file via a compiler directive
33
+ files = files.split(/\s/)
34
+ file = files.pop
35
+
36
+ top_dir = Pathname.new(file).dirname.to_s
30
37
  options[:source_dirs] ||= []
31
38
  options[:source_dirs] << top_dir unless options[:source_dirs].include?(top_dir)
32
- # Evaluates all compiler directives
33
- ast = Preprocessor::Parser.parse_file(file, options).process(options)
34
39
 
35
- # Now parse as verilog
36
- Verilog::Parser.parse(ast.to_s, options)
40
+ # Read in the file to a pre-processor AST (Verilog captured as blocks of text at this point)
41
+ ast = Preprocessor::Parser.parse_file(file, options)
42
+ unless files.empty?
43
+ files.each do |f|
44
+ ast = ast.updated(nil, [ast.updated(:include, [f])] + ast.children)
45
+ end
46
+ end
47
+
48
+ Array(options[:defines]).each do |define|
49
+ name, text = *define.split('=')
50
+ name = ast.updated(:name, [name])
51
+ nodes = [name]
52
+ nodes << ast.updated(:text, [text]) if text
53
+ ast = ast.updated(nil, [ast.updated(:define, nodes)] + ast.children)
54
+ end
55
+
56
+ # Evaluate all compiler directives
57
+ ast = ast.process(options)
58
+ # Now parse as Verilog
59
+ ast = ast.parse_verilog(options.merge(file: file))
37
60
  end
38
61
  end
@@ -2,7 +2,7 @@ require 'ast'
2
2
  require 'treetop'
3
3
  module OrigenVerilog
4
4
  class Node < ::AST::Node
5
- attr_reader :input, :interval, :file
5
+ attr_reader :input, :interval, :file, :number_of_lines
6
6
 
7
7
  # Returns the value at the root of an AST node like this:
8
8
  #
@@ -94,7 +94,7 @@ module Treetop
94
94
  properties[:input] ||= input
95
95
  properties[:interval] ||= interval
96
96
  properties[:file] ||= file
97
- Treetop.origen_verilog_parser.node.new(type, children, properties || {})
97
+ Treetop.origen_verilog_parser.node.new(type, children, properties)
98
98
  end
99
99
 
100
100
  def elements_to_ast(elmnts = elements)
@@ -107,6 +107,13 @@ module Treetop
107
107
  end.compact.flatten
108
108
  end
109
109
 
110
+ def number_of_lines(elmnts = elements)
111
+ elmnts.inject(0) do |sum, e|
112
+ lines = e.text_value.split("\n").size
113
+ sum + lines
114
+ end
115
+ end
116
+
110
117
  def file
111
118
  Treetop.origen_verilog_parser.file
112
119
  end
@@ -0,0 +1,38 @@
1
+ module OrigenVerilog
2
+ module Preprocessor
3
+ # Concatenates all text_block nodes
4
+ class Concatenator < OrigenVerilog::Processor
5
+ def run(node)
6
+ @text_block = nil
7
+ nodes = process_all(node.children)
8
+ nodes << @text_block if @text_block
9
+ node.updated(nil, nodes)
10
+ end
11
+
12
+ def on_text_block(node)
13
+ if @text_block
14
+ @text_block = @text_block.updated(:text_block, [@text_block.to_a[0] + node.to_a[0]])
15
+ else
16
+ @text_block = node
17
+ end
18
+ nil
19
+ end
20
+ alias_method :on_comment, :on_text_block
21
+
22
+ def on_file(node)
23
+ node = Concatenator.new.run(node)
24
+ if @text_block
25
+ tb = @text_block
26
+ @text_block = nil
27
+ inline [tb, node]
28
+ else
29
+ node
30
+ end
31
+ end
32
+
33
+ def handler_missing(node)
34
+ fail "No handler defined for node type: #{node.type}"
35
+ end
36
+ end
37
+ end
38
+ end
@@ -14,6 +14,10 @@ module OrigenVerilog
14
14
  def to_s
15
15
  Writer.new.to_s(self)
16
16
  end
17
+
18
+ def parse_verilog(options = {})
19
+ VerilogParser.new.run(self, options)
20
+ end
17
21
  end
18
22
  end
19
23
  end
@@ -3,7 +3,8 @@ module OrigenVerilog
3
3
  class Processor < OrigenVerilog::Processor
4
4
  def run(ast, env)
5
5
  @env = env
6
- process(ast)
6
+ ast = process(ast)
7
+ Concatenator.new.run(ast)
7
8
  end
8
9
 
9
10
  def on_include(node)
@@ -21,7 +22,8 @@ module OrigenVerilog
21
22
  puts "#{node.file}:#{node.line_number}"
22
23
  exit 1
23
24
  end
24
- inline process(Parser.parse_file(file)).children
25
+ nodes = process(Parser.parse_file(file)).children
26
+ node.updated(:file, [file] + nodes)
25
27
  end
26
28
 
27
29
  def on_define(node)
@@ -45,19 +47,44 @@ module OrigenVerilog
45
47
  elsif_nodes = node.find_all(:elsif)
46
48
  else_node = node.find(:else)
47
49
  enable, *nodes = *node
50
+
51
+ # The number of lines needs to be tracked here and blank lines (nil) are injected in place
52
+ # of un-enabled ifdef branches so that the source file line numbers will be reported correctly
53
+ # later in the Verilog parse stage
54
+ prelines = 0
55
+ postlines = 0
56
+
48
57
  if node.type == :ifdef ? env[enable] : !env[enable]
49
- inline(process_all(nodes))
58
+ content = process_all(nodes)
50
59
  else
51
- elsif_nodes.each do |elsif_node|
52
- enable, *nodes = *elsif_node
53
- if env[enable]
54
- return inline(process_all(nodes))
60
+ prelines += node.number_of_lines + 1
61
+ end
62
+
63
+ elsif_nodes.each do |elsif_node|
64
+ enable, *nodes = *elsif_node
65
+ if !content && env[enable]
66
+ content = process_all(nodes)
67
+ else
68
+ if content
69
+ postlines += elsif_node.number_of_lines + 1
70
+ else
71
+ prelines += elsif_node.number_of_lines + 1
55
72
  end
56
73
  end
57
- if else_node
58
- inline(process_all(else_node.children))
74
+ end
75
+
76
+ if else_node
77
+ if content
78
+ postlines += else_node.number_of_lines + 1
79
+ else
80
+ content = process_all(else_node.children)
59
81
  end
60
82
  end
83
+
84
+ prelines = node.updated(:text_block, ["\n" * prelines])
85
+ postlines = node.updated(:text_block, ["\n" * postlines])
86
+
87
+ inline([prelines] + (content || []) + [postlines])
61
88
  end
62
89
  alias_method :on_ifndef, :on_ifdef
63
90
 
@@ -0,0 +1,32 @@
1
+ module OrigenVerilog
2
+ module Preprocessor
3
+ # Invokes the Verilog parser on all text_block nodes, transforming the
4
+ # given pre-processor output AST into a Verilog AST
5
+ class VerilogParser < OrigenVerilog::Processor
6
+ def run(node, options = {})
7
+ @nodes = []
8
+ @file = options[:file]
9
+ @options = options
10
+ process_all(node.children)
11
+ Verilog::Node.new(:verilog_source, @nodes, file: @file)
12
+ end
13
+
14
+ def on_text_block(node)
15
+ node = Verilog::Parser.parse(node.to_a[0], @options.merge(file: @file))
16
+ @nodes += node.children
17
+ nil
18
+ end
19
+
20
+ def on_file(node)
21
+ file, *nodes = *node
22
+ node = VerilogParser.new.run(node.updated(nil, nodes), @options.merge(file: file))
23
+ @nodes += node.children
24
+ nil
25
+ end
26
+
27
+ def handler_missing(node)
28
+ fail "No handler defined for node type: #{node.type}"
29
+ end
30
+ end
31
+ end
32
+ end
@@ -5,6 +5,13 @@ module OrigenVerilog
5
5
  ast.updated(nil, process_all(ast.children))
6
6
  end
7
7
 
8
+ def on_constant_expression(node)
9
+ nodes = process_all(node.children)
10
+ nodes = nodes.map { |n| n.is_a?(Node) ? process(n.value) : n }
11
+ # Ruby should be close enough to Verilog to just eval the expression for most cases
12
+ eval(nodes.join(' '))
13
+ end
14
+
8
15
  def on_decimal_number(node)
9
16
  process(node.value)
10
17
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: origen_verilog
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.3.1
4
+ version: 0.4.0
5
5
  platform: ruby
6
6
  authors:
7
7
  - Stephen McGinty
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2018-02-06 00:00:00.000000000 Z
11
+ date: 2018-06-18 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: ast
@@ -56,9 +56,11 @@ files:
56
56
  - lib/origen_verilog/commands/parse.rb
57
57
  - lib/origen_verilog/node.rb
58
58
  - lib/origen_verilog/parser.rb
59
+ - lib/origen_verilog/preprocessor/contatenator.rb
59
60
  - lib/origen_verilog/preprocessor/node.rb
60
61
  - lib/origen_verilog/preprocessor/parser.rb
61
62
  - lib/origen_verilog/preprocessor/processor.rb
63
+ - lib/origen_verilog/preprocessor/verilog_parser.rb
62
64
  - lib/origen_verilog/preprocessor/writer.rb
63
65
  - lib/origen_verilog/processor.rb
64
66
  - lib/origen_verilog/top_level.rb
@@ -91,7 +93,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
91
93
  version: 1.8.11
92
94
  requirements: []
93
95
  rubyforge_project:
94
- rubygems_version: 2.6.7
96
+ rubygems_version: 2.6.14.1
95
97
  signing_key:
96
98
  specification_version: 4
97
99
  summary: A parser and generator for Verilog (IEEE 1364)