origen_verilog 0.3.0 → 0.3.1

checksums.yaml

@@ -1,7 +1,7 @@
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-  data.tar.gz: e15f496480ad467f7c472c1179d5d7376958b6b4
+  metadata.gz: 1be3a1740eb02ddf52433ffdf8d3b6eb3ca30657
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data/config/commands.rb

@@ -34,6 +34,10 @@ when "build"
   end
   exit 0
 
+when "parse"
+  require "origen_verilog/commands/parse"
+  exit 0
+
 ## Example of how to make a command to run unit tests, this simply invokes RSpec on
 ## the spec directory
 when "specs"
@@ -80,6 +84,7 @@ else
   # origen -h, you can do this by assigning the required text to @application_commands
   # before handing control back to Origen.
   @application_commands = <<-EOT
+ parse        Command to test/debug the verilog parser (similar to the sim:build command)
  tags         Build a tags file for this app
  build        Build/compile the latest grammar files
  specs        Run the specs (tests), -c will enable coverage

data/config/version.rb

@@ -1,7 +1,7 @@
 module OrigenVerilog
   MAJOR = 0
   MINOR = 3
-  BUGFIX = 0
+  BUGFIX = 1
   DEV = nil
 
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')

data/grammars/verilog.rb

@@ -1247,11 +1247,11 @@ module OrigenVerilog
 
         i0, s0 = index, []
         i1 = index
-        if (match_len = has_terminal?("1", false, index))
-          r2 = true
+        if (match_len = has_terminal?("100", false, index))
+          r2 = instantiate_node(SyntaxNode,input, index...(index + match_len))
           @index += match_len
         else
-          terminal_parse_failure('"1"')
+          terminal_parse_failure('"100"')
           r2 = nil
         end
         if r2
@@ -1269,11 +1269,11 @@ module OrigenVerilog
             r3 = SyntaxNode.new(input, (index-1)...index) if r3 == true
             r1 = r3
           else
-            if (match_len = has_terminal?("100", false, index))
-              r4 = instantiate_node(SyntaxNode,input, index...(index + match_len))
+            if (match_len = has_terminal?("1", false, index))
+              r4 = true
               @index += match_len
             else
-              terminal_parse_failure('"100"')
+              terminal_parse_failure('"1"')
               r4 = nil
             end
             if r4

data/lib/origen_verilog/commands/parse.rb

@@ -0,0 +1,68 @@
+require 'optparse'
+require 'origen_verilog'
+
+options = { source_dirs: [] }
+
+# App options are options that the application can supply to extend this command
+app_options = @application_options || []
+opt_parser = OptionParser.new do |opts|
+  opts.banner = <<-EOT
+Parse the given top-level verilog file and convert the top-level module to an Origen top-level
+model.
+Usage: origen parse TOP_LEVEL_RTL_FILE [options]
+  EOT
+  opts.on('-t', '--top NAME', String, 'Specify the top-level Verilog module name if OrigenSim can\'t work it out') { |t| options[:top_level_name] = t }
+  opts.on('-s', '--source_dir PATH', 'Directories to look for include files in (the directory containing the top-level is already considered)') do |path|
+    options[:source_dirs] << path
+  end
+  opts.on('-d', '--debugger', 'Enable the debugger') {  options[:debugger] = true }
+  app_options.each do |app_option|
+    opts.on(*app_option) {}
+  end
+  opts.separator ''
+  opts.on('-h', '--help', 'Show this message') { puts opts; exit 0 }
+end
+
+opt_parser.parse! ARGV
+
+unless ARGV.size > 0
+  puts 'You must supply a path to the top-level RTL file'
+  exit 1
+end
+rtl_top = ARGV.first
+unless File.exist?(rtl_top)
+  puts "File does not exist: #{rtl_top}"
+  exit 1
+end
+
+ast = OrigenVerilog.parse_file(rtl_top)
+
+unless ast
+  puts 'Sorry, but the given top-level RTL file failed to parse'
+  exit 1
+end
+
+candidates = ast.top_level_modules
+candidates = ast.modules if candidates.empty?
+
+if candidates.size == 0
+  puts "Sorry, couldn't find any Verilog module declarations in that file"
+  exit 1
+elsif candidates.size > 1
+  if options[:top_level_name]
+    mod = candidates.find { |c| c.name == options[:top_level_name] }
+  end
+  unless mod
+    puts "Sorry, couldn't work out what the top-level module is, please help by running again and specifying it via the --top switch with one of the following names:"
+    candidates.each do |c|
+      puts "  #{c.name}"
+    end
+    exit 1
+  end
+else
+  mod = candidates.first
+end
+
+rtl_top_module = mod.name
+
+mod.to_top_level # Creates dut

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_verilog
 version: !ruby/object:Gem::Version
-  version: 0.3.0
+  version: 0.3.1
 platform: ruby
 authors:
 - Stephen McGinty
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2018-01-15 00:00:00.000000000 Z
+date: 2018-02-06 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: ast
@@ -53,6 +53,7 @@ files:
 - grammars/preprocessor.rb
 - grammars/verilog.rb
 - lib/origen_verilog.rb
+- lib/origen_verilog/commands/parse.rb
 - lib/origen_verilog/node.rb
 - lib/origen_verilog/parser.rb
 - lib/origen_verilog/preprocessor/node.rb
@@ -90,7 +91,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
       version: 1.8.11
 requirements: []
 rubyforge_project: 
-rubygems_version: 2.6.8
+rubygems_version: 2.6.7
 signing_key: 
 specification_version: 4
 summary: A parser and generator for Verilog (IEEE 1364)