origen_verilog 0.3.0 → 0.3.1

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checksums.yaml CHANGED
@@ -1,7 +1,7 @@
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data/config/commands.rb CHANGED
@@ -34,6 +34,10 @@ when "build"
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  end
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  exit 0
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+ when "parse"
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+ require "origen_verilog/commands/parse"
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+ exit 0
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+
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  ## Example of how to make a command to run unit tests, this simply invokes RSpec on
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  ## the spec directory
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  when "specs"
@@ -80,6 +84,7 @@ else
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  # origen -h, you can do this by assigning the required text to @application_commands
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  # before handing control back to Origen.
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  @application_commands = <<-EOT
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+ parse Command to test/debug the verilog parser (similar to the sim:build command)
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  tags Build a tags file for this app
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  build Build/compile the latest grammar files
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  specs Run the specs (tests), -c will enable coverage
data/config/version.rb CHANGED
@@ -1,7 +1,7 @@
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  module OrigenVerilog
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  MAJOR = 0
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  MINOR = 3
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- BUGFIX = 0
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+ BUGFIX = 1
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  DEV = nil
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  VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
data/grammars/verilog.rb CHANGED
@@ -1247,11 +1247,11 @@ module OrigenVerilog
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  i0, s0 = index, []
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  i1 = index
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- if (match_len = has_terminal?("1", false, index))
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- r2 = true
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+ if (match_len = has_terminal?("100", false, index))
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+ r2 = instantiate_node(SyntaxNode,input, index...(index + match_len))
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  @index += match_len
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  else
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- terminal_parse_failure('"1"')
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+ terminal_parse_failure('"100"')
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  r2 = nil
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  end
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  if r2
@@ -1269,11 +1269,11 @@ module OrigenVerilog
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  r3 = SyntaxNode.new(input, (index-1)...index) if r3 == true
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  r1 = r3
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  else
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- if (match_len = has_terminal?("100", false, index))
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- r4 = instantiate_node(SyntaxNode,input, index...(index + match_len))
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+ if (match_len = has_terminal?("1", false, index))
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+ r4 = true
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  @index += match_len
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  else
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- terminal_parse_failure('"100"')
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+ terminal_parse_failure('"1"')
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  r4 = nil
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  end
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  if r4
@@ -0,0 +1,68 @@
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+ require 'optparse'
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+ require 'origen_verilog'
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+
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+ options = { source_dirs: [] }
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+
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+ # App options are options that the application can supply to extend this command
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+ app_options = @application_options || []
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+ opt_parser = OptionParser.new do |opts|
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+ opts.banner = <<-EOT
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+ Parse the given top-level verilog file and convert the top-level module to an Origen top-level
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+ model.
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+ Usage: origen parse TOP_LEVEL_RTL_FILE [options]
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+ EOT
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+ opts.on('-t', '--top NAME', String, 'Specify the top-level Verilog module name if OrigenSim can\'t work it out') { |t| options[:top_level_name] = t }
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+ opts.on('-s', '--source_dir PATH', 'Directories to look for include files in (the directory containing the top-level is already considered)') do |path|
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+ options[:source_dirs] << path
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+ end
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+ opts.on('-d', '--debugger', 'Enable the debugger') { options[:debugger] = true }
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+ app_options.each do |app_option|
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+ opts.on(*app_option) {}
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+ end
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+ opts.separator ''
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+ opts.on('-h', '--help', 'Show this message') { puts opts; exit 0 }
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+ end
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+
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+ opt_parser.parse! ARGV
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+
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+ unless ARGV.size > 0
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+ puts 'You must supply a path to the top-level RTL file'
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+ exit 1
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+ end
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+ rtl_top = ARGV.first
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+ unless File.exist?(rtl_top)
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+ puts "File does not exist: #{rtl_top}"
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+ exit 1
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+ end
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+
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+ ast = OrigenVerilog.parse_file(rtl_top)
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+
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+ unless ast
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+ puts 'Sorry, but the given top-level RTL file failed to parse'
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+ exit 1
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+ end
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+
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+ candidates = ast.top_level_modules
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+ candidates = ast.modules if candidates.empty?
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+
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+ if candidates.size == 0
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+ puts "Sorry, couldn't find any Verilog module declarations in that file"
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+ exit 1
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+ elsif candidates.size > 1
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+ if options[:top_level_name]
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+ mod = candidates.find { |c| c.name == options[:top_level_name] }
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+ end
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+ unless mod
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+ puts "Sorry, couldn't work out what the top-level module is, please help by running again and specifying it via the --top switch with one of the following names:"
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+ candidates.each do |c|
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+ puts " #{c.name}"
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+ end
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+ exit 1
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+ end
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+ else
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+ mod = candidates.first
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+ end
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+
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+ rtl_top_module = mod.name
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+
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+ mod.to_top_level # Creates dut
metadata CHANGED
@@ -1,14 +1,14 @@
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  --- !ruby/object:Gem::Specification
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  name: origen_verilog
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  version: !ruby/object:Gem::Version
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- version: 0.3.0
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+ version: 0.3.1
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  platform: ruby
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  authors:
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  - Stephen McGinty
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2018-01-15 00:00:00.000000000 Z
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+ date: 2018-02-06 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: ast
@@ -53,6 +53,7 @@ files:
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  - grammars/preprocessor.rb
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  - grammars/verilog.rb
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  - lib/origen_verilog.rb
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+ - lib/origen_verilog/commands/parse.rb
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  - lib/origen_verilog/node.rb
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  - lib/origen_verilog/parser.rb
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  - lib/origen_verilog/preprocessor/node.rb
@@ -90,7 +91,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
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  version: 1.8.11
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  requirements: []
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  rubyforge_project:
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- rubygems_version: 2.6.8
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+ rubygems_version: 2.6.7
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  signing_key:
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  specification_version: 4
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  summary: A parser and generator for Verilog (IEEE 1364)