origen_verilog 0.3.0 → 0.3.1
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/config/commands.rb +5 -0
- data/config/version.rb +1 -1
- data/grammars/verilog.rb +6 -6
- data/lib/origen_verilog/commands/parse.rb +68 -0
- metadata +4 -3
checksums.yaml
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@@ -1,7 +1,7 @@
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---
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SHA1:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 1be3a1740eb02ddf52433ffdf8d3b6eb3ca30657
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data.tar.gz: d0d8602e57ecb3eeb04d1dbd0919bb3d36f7a252
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 7c4f3a008af2790d2479c594f5cb777fa7903fea17df2f1ad3daa1df728bf52e9ec498baaaf1ce5867c4aa7027b8ffb96c2eaa90475236af1f687d4a75de9036
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data.tar.gz: a2468d8aeb390439016a517c1eb5bd55707f0c2bfa1addbcc801e69a88fdfdc07650600da81194c64806406ce0a30b221be9074397120398e21017494c26a72b
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data/config/commands.rb
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@@ -34,6 +34,10 @@ when "build"
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end
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exit 0
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when "parse"
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require "origen_verilog/commands/parse"
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exit 0
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## Example of how to make a command to run unit tests, this simply invokes RSpec on
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## the spec directory
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when "specs"
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@@ -80,6 +84,7 @@ else
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# origen -h, you can do this by assigning the required text to @application_commands
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# before handing control back to Origen.
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@application_commands = <<-EOT
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parse Command to test/debug the verilog parser (similar to the sim:build command)
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tags Build a tags file for this app
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build Build/compile the latest grammar files
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specs Run the specs (tests), -c will enable coverage
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data/config/version.rb
CHANGED
data/grammars/verilog.rb
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@@ -1247,11 +1247,11 @@ module OrigenVerilog
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i0, s0 = index, []
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i1 = index
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if (match_len = has_terminal?("
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r2 =
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if (match_len = has_terminal?("100", false, index))
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r2 = instantiate_node(SyntaxNode,input, index...(index + match_len))
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@index += match_len
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else
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terminal_parse_failure('"
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terminal_parse_failure('"100"')
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r2 = nil
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end
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if r2
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@@ -1269,11 +1269,11 @@ module OrigenVerilog
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r3 = SyntaxNode.new(input, (index-1)...index) if r3 == true
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r1 = r3
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else
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if (match_len = has_terminal?("
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r4 =
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if (match_len = has_terminal?("1", false, index))
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r4 = true
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@index += match_len
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else
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terminal_parse_failure('"
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terminal_parse_failure('"1"')
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r4 = nil
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end
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if r4
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@@ -0,0 +1,68 @@
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require 'optparse'
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require 'origen_verilog'
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options = { source_dirs: [] }
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# App options are options that the application can supply to extend this command
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app_options = @application_options || []
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opt_parser = OptionParser.new do |opts|
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opts.banner = <<-EOT
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Parse the given top-level verilog file and convert the top-level module to an Origen top-level
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model.
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Usage: origen parse TOP_LEVEL_RTL_FILE [options]
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EOT
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opts.on('-t', '--top NAME', String, 'Specify the top-level Verilog module name if OrigenSim can\'t work it out') { |t| options[:top_level_name] = t }
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opts.on('-s', '--source_dir PATH', 'Directories to look for include files in (the directory containing the top-level is already considered)') do |path|
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options[:source_dirs] << path
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end
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opts.on('-d', '--debugger', 'Enable the debugger') { options[:debugger] = true }
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app_options.each do |app_option|
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opts.on(*app_option) {}
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end
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opts.separator ''
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opts.on('-h', '--help', 'Show this message') { puts opts; exit 0 }
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end
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opt_parser.parse! ARGV
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unless ARGV.size > 0
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puts 'You must supply a path to the top-level RTL file'
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exit 1
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end
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rtl_top = ARGV.first
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unless File.exist?(rtl_top)
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puts "File does not exist: #{rtl_top}"
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exit 1
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end
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ast = OrigenVerilog.parse_file(rtl_top)
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unless ast
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puts 'Sorry, but the given top-level RTL file failed to parse'
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exit 1
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end
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candidates = ast.top_level_modules
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candidates = ast.modules if candidates.empty?
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if candidates.size == 0
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puts "Sorry, couldn't find any Verilog module declarations in that file"
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exit 1
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elsif candidates.size > 1
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if options[:top_level_name]
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mod = candidates.find { |c| c.name == options[:top_level_name] }
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end
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unless mod
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puts "Sorry, couldn't work out what the top-level module is, please help by running again and specifying it via the --top switch with one of the following names:"
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candidates.each do |c|
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puts " #{c.name}"
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end
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exit 1
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end
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else
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mod = candidates.first
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end
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rtl_top_module = mod.name
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mod.to_top_level # Creates dut
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metadata
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@@ -1,14 +1,14 @@
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--- !ruby/object:Gem::Specification
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name: origen_verilog
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version: !ruby/object:Gem::Version
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version: 0.3.
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version: 0.3.1
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platform: ruby
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authors:
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- Stephen McGinty
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autorequire:
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bindir: bin
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cert_chain: []
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date: 2018-
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date: 2018-02-06 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: ast
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@@ -53,6 +53,7 @@ files:
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- grammars/preprocessor.rb
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- grammars/verilog.rb
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- lib/origen_verilog.rb
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- lib/origen_verilog/commands/parse.rb
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- lib/origen_verilog/node.rb
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- lib/origen_verilog/parser.rb
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- lib/origen_verilog/preprocessor/node.rb
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version: 1.8.11
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requirements: []
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rubyforge_project:
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rubygems_version: 2.6.
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rubygems_version: 2.6.7
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signing_key:
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specification_version: 4
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summary: A parser and generator for Verilog (IEEE 1364)
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