origen_swd 0.4.0 → 0.5.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
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-  data.tar.gz: 7975842c9f9a94a54f7cb8840479e068ac479bdb
+  metadata.gz: e19e934c3c7bbb7092cad11d2d69b97be46ee52e
+  data.tar.gz: 07ff3368c8d0e9ed1904a81602d8d0a52c7a1399
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+  data.tar.gz: 5460db3c0c1388a17f0f5eb1e049f898330c2d56fb7f5c97a151d351580ab41d5d88277cfa2ee96df16abe19ea07e3a887e89ff6e1067a7d1a63c44fd94cd888

data/config/commands.rb

@@ -24,6 +24,10 @@ when "examples"
   # Pattern generator tests
   ARGV = %w(example -t debug -r approved)
   load "#{Origen.top}/lib/origen/commands/generate.rb"
+  ARGV = %w(example_api -t debug -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
+  ARGV = %w(example_reg -t debug -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
     
   if Origen.app.stats.changed_files == 0 &&
      Origen.app.stats.new_files == 0 &&

data/config/version.rb

@@ -1,6 +1,6 @@
 module OrigenSWD
   MAJOR = 0
-  MINOR = 4
+  MINOR = 5
   BUGFIX = 0
   DEV = nil
 

data/lib/origen_swd/driver.rb

@@ -4,74 +4,305 @@ module OrigenSWD
   #   :swd_dio
   #
   class Driver
+    REQUIRED_PINS = [:swd_clk, :swd_dio]
+
+    include Origen::Registers
+
     # Returns the parent object that instantiated the driver, could be
     # either a DUT object or a protocol abstraction
     attr_reader :owner
+    attr_accessor :trn
 
     # Initialize class variables
-    # owner - parent object
-    # options - any miscellaneous custom arguments
-    # Returns nothing.
     #
-    # Examples
+    # @param [Object] owner Parent object
+    # @param [Hash] options Options to customize the operation
     #
+    # @example
+    #   # Create new SWD::Driver object
     #   DUT.new.swd
     #
     def initialize(owner, options = {})
       @owner = owner
+      # validate_pins
+
       @current_apaddr = 0
       @orundetect = 0
+      @trn = 0
+    end
+
+    # Read data from Debug Port or Access Port
+    #
+    # @param [Integer] ap_dp A single bit indicating whether the Debug Port or the Access Port
+    #   Register is to be accessed.  This bit is 0 for an DPACC access, or 1 for a APACC access
+    # @param [Integer, Origen::Register::Reg, Origen::Register::BitCollection, Origen::Register::Bit] reg_or_val
+    #   Value to be shifted. If a reg/bit collection is supplied this can be pre-marked for
+    #   read, store or overlay and which will result in the requested action being applied to
+    #   the cycles corresponding to those bits only (don't care cycles will be generated for the others).
+    # @param [Hash] options Options to customize the operation
+    def read(ap_dp, reg_or_val, options = {})
+      addr = reg_or_val.respond_to?(:address) ? reg_or_val.address : reg_or_val
+      send_header(ap_dp, 1, addr)       # send read-specific header (rnw = 1)
+      receive_acknowledgement
+      receive_payload(reg_or_val, options)
+    end
+
+    # Write data to Debug Port or Access Port
+    #
+    # @param [Integer] ap_dp A single bit indicating whether the Debug Port or the Access Port Register
+    #   is to be accessed.  This bit is 0 for an DPACC access, or 1 for a APACC access
+    # @param [Integer, Origen::Register::Reg, Origen::Register::BitCollection, Origen::Register::Bit] reg_or_val
+    #   Value to be shifted. If a reg/bit collection is supplied this can be pre-marked for
+    #   read, store or overlay and which will result in the requested action being applied to
+    #   the cycles corresponding to those bits only (don't care cycles will be generated for the others).
+    # @param [Integer] wdata Data to be written
+    # @param [Hash] options Options to customize the operation
+    def write(ap_dp, reg_or_val, wdata, options = {})
+      addr = reg_or_val.respond_to?(:address) ? reg_or_val.address : reg_or_val
+      send_header(ap_dp, 0, addr)       # send write-specific header (rnw = 0)
+      receive_acknowledgement
+
+      if reg_or_val.respond_to?(:data)
+        reg_or_val.data = wdata
+      else
+        reg_or_val = wdata
+      end
+      send_payload(reg_or_val, options)
     end
 
     # Sends data stream with SWD protocol
-    # data - data to be sent
-    # size - the length of data
-    # options - any miscellaneous custom arguments
-    # options[:overlay] - string for pattern label to facilitate pattern overlay
-    # Returns nothing.
+    #
+    # @param [Integer] data Data to be sent
+    # @param [Integer] size The length of data
+    # @param [Hash] options Options to customize the operation
+    # @option options [String] :overlay String for pattern label to
+    #   facilitate pattern overlay
     def send_data(data, size, options = {})
+      # Warn caller that this method is being deprecated
+      msg = 'Use swd.write(ap_dp, reg_or_val, wdata, options = {}) instead of send_data(data, size, options = {})'
+      Origen.deprecate msg
       if options.key?(:overlay)
         $tester.label(options[:overlay])
         size.times do |bit|
-          owner.pin(:swd_clk).drive(1)
+          swd_clk.drive(1)
           $tester.label("// SWD Data Pin #{bit}")
-          owner.pin(:swd_dio).drive(data[bit])
+          swd_dio.drive(data[bit])
           $tester.cycle
         end
-        owner.pin(:swd_dio).dont_care
+        swd_dio.dont_care
       else
         size.times do |bit|
-          owner.pin(:swd_clk).drive(1)
-          owner.pin(:swd_dio).drive(data[bit])
+          swd_clk.drive(1)
+          swd_dio.drive(data[bit])
           $tester.cycle
         end
-        owner.pin(:swd_dio).dont_care
+        swd_dio.dont_care
       end
     end
 
     # Recieves data stream with SWD protocol
-    # size - the length of data
-    # options - any miscellaneous custom arguments
-    # options[:compare_data] - data to be compared, only compared if options is set
-    # Returns nothing.
+    #
+    # @param [Integer] size The length of data
+    # @param [Hash] options Options to customize the operation
+    # @option options [String] :compare_data Data to be compared, only compared
+    #   if options is set
     def get_data(size, options = {})
-      should_store = $dut.pin(:swd_dio).is_to_be_stored?
-      owner.pin(:swd_dio).dont_care
+      # Warn caller that this method is being deprecated
+      msg = 'Use swd.read(ap_dp, reg_or_val, options = {}) instead of get_data(size, options = {})'
+      Origen.deprecate msg
+      should_store = swd_dio.is_to_be_stored?
+      swd_dio.dont_care
       size.times do |bit|
         $tester.store_next_cycle($dut.pin(:swd_dio)) if should_store
-        $dut.pin(:swd_dio).assert(options[:compare_data][bit]) if options.key?(:compare_data)
+        swd_dio.assert(options[:compare_data][bit]) if options.key?(:compare_data)
         $tester.cycle
       end
     end
 
     # Sends specified number of '0' bits
-    # size - the length of data
-    # Returns nothing.
+    #
+    # @param [Integer] size The length of data
     def swd_dio_to_0(size)
-      owner.pin(:swd_dio).drive(0)
+      swd_dio.drive(0)
       size.times do |bit|
         $tester.cycle
       end
     end
+
+    private
+
+    # Send SWD Packet header
+    #   ------------------------------------------------------------------------
+    #   | Start | APnDP |   1   | ADDR[2] | ADDR[3] | Parity |  Stop  |  Park  |
+    #   ------------------------------------------------------------------------
+    #
+    # @param [Integer] apndp A single bit indicating whether the Debug Port or the Access Port
+    #   Register is to be accessed.  This bit is 0 for an DPACC access, or 1 for a APACC access
+    # @param [Integer] rnw A single bit, indicating whether the access is a read or a write.
+    #   This bit is 0 for a write access, or 1 for a read access.
+    # @param [Integer] address Address of register that is being accessed
+    def send_header(apndp, rnw, address)
+      addr = address >> 2
+      parity  = apndp ^ rnw ^ (addr >> 3) ^ (addr >> 2) & (0x01) ^ (addr >> 1) & (0x01) ^ addr & 0x01
+
+      cc 'Header phase'
+      swd_clk.drive(1)
+      cc 'Send Start Bit'
+      swd_dio.drive!(1)                                   # send start bit (always 1)
+      cc 'Send APnDP Bit (DP or AP Access Register Bit)'
+      swd_dio.drive!(apndp)                               # send apndp bit
+      cc 'Send RnW Bit (read or write bit)'
+      swd_dio.drive!(rnw)                                 # send rnw bit
+      cc 'Send Address Bits (2 bits)'
+      swd_dio.drive!(addr[0])                             # send address[2] bit
+      swd_dio.drive!(addr[1])                             # send address[3] bit
+      cc 'Send Parity Bit'
+      swd_dio.drive!(parity[0])                           # send parity bit
+      cc 'Send Stop Bit'
+      swd_dio.drive!(0)                                   # send stop bit
+      cc 'Send Park Bit'
+      swd_dio.drive!(1)                                   # send park bit
+      swd_dio.dont_care
+    end
+
+    # Waits appropriate number of cycles for the acknowledgement phase
+    def receive_acknowledgement
+      cc 'Acknowledge Response phase'
+      wait_trn
+      swd_dio.dont_care
+      $tester.cycle(repeat: 3)
+    end
+
+    # Waits for TRN time delay
+    def wait_trn
+      swd_dio.drive(1)
+      $tester.cycle(repeat: trn + 1)
+    end
+
+    # Get (read) the data payload
+    #
+    # @param [Integer, Origen::Register::Reg, Origen::Register::BitCollection, Origen::Register::Bit] reg_or_val
+    #   Value to be read. If a reg/bit collection is supplied this can be pre-marked for
+    #   read, store or overlay and which will result in the requested action being applied to
+    #   the cycles corresponding to those bits only (don't care cycles will be generated for the others).
+    # @option options [String] :overlay String for pattern label to
+    #   facilitate pattern overlay
+    def receive_payload(reg_or_val, options)
+      cc 'Read Data Payload phase'
+
+      cc 'SWD 32-Bit Read Data Start'
+      options[:read] = true
+      shift_payload(reg_or_val, options)
+
+      cc 'SWD 32-Bit Read Data End'
+      cc 'Get Read Parity Bit'
+      swd_dio.dont_care
+      $tester.cycle
+      cc 'Send Read ACK bits'
+      wait_trn
+    end
+
+    # Send (write) the data payload
+    #
+    # @param [Integer, Origen::Register::Reg, Origen::Register::BitCollection, Origen::Register::Bit] reg_or_val
+    #   Value to be written. If a reg/bit collection is supplied this can be pre-marked for
+    #   read, store or overlay and which will result in the requested action being applied to
+    #   the cycles corresponding to those bits only (don't care cycles will be generated for the others).
+    # @option options [String] :overlay String for pattern label to
+    #   facilitate pattern overlay
+    def send_payload(reg_or_val, options)
+      cc 'Write Data Payload phase'
+      cc 'Send ACK Bits'
+      wait_trn
+
+      cc 'SWD 32-Bit Write Start'
+      options[:read] = false
+      shift_payload(reg_or_val, options)
+
+      cc 'Send Write Parity Bit'
+      wdata = reg_or_val.respond_to?(:data) ? reg_or_val.data : reg_or_val
+      parity_bit = swd_xor_calc(32, wdata)
+      swd_dio.drive!(parity_bit)
+    end
+
+    # Shift the data payload
+    #
+    # @param [Integer, Origen::Register::Reg, Origen::Register::BitCollection, Origen::Register::Bit] reg_or_val
+    #   Value to be shifted. If a reg/bit collection is supplied this can be pre-marked for
+    #   read, store or overlay and which will result in the requested action being applied to
+    #   the cycles corresponding to those bits only (don't care cycles will be generated for the others).
+    # @option options [String] :overlay String for pattern label to
+    #   facilitate pattern overlay
+    def shift_payload(reg_or_val, options)
+      cc options[:arm_debug_comment] if options.key?(:arm_debug_comment)
+      size = 32    # SWD only used to write to DP and AP registers of ARM Debugger (32 bits)
+      contains_bits = (contains_bits?(reg_or_val) || is_a_bit?(reg_or_val))
+      if options.key?(:arm_debug_overlay)
+        options[:overlay] = options[:arm_debug_overlay]
+        options[:overlay_label] = options[:arm_debug_overlay]
+      end
+      if options.key?(:overlay)
+        if options[:overlay_label].nil?
+          options[:overlay_label] = options[:overlay]
+          $tester.label(options[:overlay_label]) if options.key?(:overlay)
+        end
+      end
+      swd_clk.drive(1)
+      size.times do |i|
+        if options[:read]
+          # If it's a register support bit-wise reads
+          if contains_bits
+            if reg_or_val[i].is_to_be_stored?
+              Origen.tester.store_next_cycle(swd_dio)
+              swd_dio.dont_care if Origen.tester.j750?
+            elsif reg_or_val[i].has_overlay?
+              $tester.label(reg_or_val[i].overlay_str)
+            elsif reg_or_val[i].is_to_be_read?
+              swd_dio.assert(reg_or_val[i] ? reg_or_val[i] : 0)
+            elsif options.key?(:compare_data)
+              swd_dio.assert(reg_or_val[i] ? reg_or_val[i] : 0)
+            else
+              swd_dio.dont_care
+            end
+          else
+            if options.key?(:compare_data)
+              swd_dio.assert(reg_or_val[i] ? reg_or_val[i] : 0)
+            else
+              swd_dio.dont_care
+            end
+          end
+          $tester.cycle
+        else
+          $tester.label("// SWD Data Pin #{i}") if options.key?(:overlay) && !Origen.mode.simulation?
+          swd_dio.drive!(reg_or_val[i])
+        end
+      end
+      # Clear read and similar flags to reflect that the request has just
+      # been fulfilled
+      reg_or_val.clear_flags if reg_or_val.respond_to?(:clear_flags)
+      swd_dio.dont_care
+    end
+
+    # Calculate exclusive OR
+    #
+    # @param [Integer] size The number of bits in the number
+    # @param [Integer] number The number being operated on
+    def swd_xor_calc(size, number)
+      xor = 0
+      size.times do |bit|
+        xor ^= (number >> bit) & 0x01
+      end
+      xor
+    end
+
+    # Provided shortname access to top-level SWD clock pin
+    def swd_clk
+      owner.pin(:swd_clk)
+    end
+
+    # Provided shortname access to top-level SWD data I/P pin
+    def swd_dio
+      owner.pin(:swd_dio)
+    end
   end
 end

data/lib/origen_swd/dut.rb

@@ -11,23 +11,31 @@ module OrigenSWD
     include Origen::Pins
 
     # Initializes simple dut model with test register and required swd pins
-    # options - any miscellaneous custom arguments
-    # Returns nothing.
     #
-    # Examples
+    # @param [Hash] options Options to customize the operation
     #
+    # @example
     #   $dut = OrigenSWD::DUT.new
     #
     def initialize(options = {})
-      add_reg :test, 0x0, 32, data: { pos: 0, bits: 32 },
-                              bit:  { pos: 0 }
+      # Sample DPACC register
+      add_reg :test, 0x04, 32, data: { pos: 0, bits: 32 },
+                               bit:  { pos: 2 }
+
+      # Sample DPACC register
+      add_reg :select, 0x08, 32, data: { pos: 0, bits: 32 }
+
+      # Sample APACC register
+      add_reg :stat, 0x00, 32, data: { pos: 0, bits: 32 }
+      add_reg :control, 0x01, 32, data: { pos: 0, bits: 32 }
+
       add_pin :swd_clk
       add_pin :swd_dio
     end
 
     # Add any custom startup business here.
-    # options - any miscellaneous custom arguments
-    # Returns nothing.
+    #
+    # @param [Hash] options Options to customize the operation
     def startup(options = {})
       $tester.set_timeset('swd', 40)
     end

data/pattern/example_api.rb

@@ -0,0 +1,37 @@
+Pattern.create do
+  DP = 0
+  AP = 1
+  ap_dp      = 1
+  address    = 0x00002020
+  wdata      = 0xAAAA5555
+
+
+  $dut.swd.write(ap_dp, address, wdata, overlay: 'write_ovl')
+  cc 'SWD DIO to 0 for 10 cycles'
+  $dut.swd.swd_dio_to_0(10)
+  $dut.swd.read(ap_dp, address)
+  $dut.swd.swd_dio_to_0(10)
+  $dut.swd.read(ap_dp, address, compare_data: wdata)
+  $dut.swd.swd_dio_to_0(10)
+
+  #$dut.reg(:select).data = 0x01000000
+  $dut.swd.write(DP, $dut.reg(:select), 0x01000000, arm_debug_overlay: 'select_reg')
+  $dut.swd.swd_dio_to_0(10)
+  $dut.swd.read(DP, $dut.reg(:select))
+  $dut.swd.swd_dio_to_0(10)
+
+  $dut.swd.write(DP, $dut.reg(:stat), 0x00000032)
+  $dut.swd.swd_dio_to_0(10)
+  $dut.swd.write(DP, $dut.reg(:control), 0x00000010)
+  $dut.swd.swd_dio_to_0(10)
+  $dut.swd.read(DP, $dut.reg(:control), r_mask: 'store')
+  $dut.swd.swd_dio_to_0(10)
+  $dut.swd.read(DP, $dut.reg(:control), compare_data: 0x00000010)
+  $dut.swd.swd_dio_to_0(10)
+
+  $dut.swd.read(DP, $dut.reg(:control), compare_data: 0x00000010)
+  $dut.swd.swd_dio_to_0(10)
+  $dut.swd.read(DP, $dut.reg(:control), compare_data: 0x00000010)
+  $dut.swd.swd_dio_to_0(10)
+
+end

data/pattern/example_reg.rb

@@ -0,0 +1,42 @@
+Pattern.create do
+
+  swd = $dut.swd
+  reg = $dut.reg(:test)
+
+  def test(msg)
+    ss "Test - #{msg}"
+  end
+
+  test "Write to DR register"
+  reg.write(0xFF01FF01)
+  swd.write(0, reg, 0xFF01FF01)
+
+  test "Write to DR register with overlay"
+  reg.overlay("write_overlay")
+  swd.write(0, reg, 0xFF01FF01)
+    
+  test "Write to DR register with single bit overlay"
+  reg.overlay(nil)
+  reg.bit(:bit).overlay("write_overlay")
+  swd.write(0, reg, 0xFF01FF01)
+
+
+  test "Read full DR register"
+  cc "Full register (32 bits)"
+  reg.read
+  swd.read(0, reg)
+
+  test "Read single bit out of DR register"
+  reg.bit(:bit).read
+  swd.read(0, reg)
+
+  test "Store full DR register"
+  cc "Full register (32 bits)"
+  reg.store
+  swd.read(0, reg)
+
+  test "Store single bit out of DR register"
+  reg.bit(:bit).store
+  swd.read(0, reg)
+
+end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_swd
 version: !ruby/object:Gem::Version
-  version: 0.4.0
+  version: 0.5.0
 platform: ruby
 authors:
 - Ronnie Lajaunie
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2015-08-19 00:00:00.000000000 Z
+date: 2015-08-24 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen
@@ -55,6 +55,8 @@ files:
 - lib/origen_swd/driver.rb
 - lib/origen_swd/dut.rb
 - pattern/example.rb
+- pattern/example_api.rb
+- pattern/example_reg.rb
 - templates/web/index.md.erb
 - templates/web/layouts/_basic.html.erb
 - templates/web/partials/_navbar.html.erb