origen_spi 0.1.1 → 0.2.0

data/lib/tasks/origen_spi.rake

@@ -1,6 +1,6 @@
-# You can define any Rake tasks to support your application here (or in any file
-# ending in .rake in this directory).
-#
-# Rake (Ruby Make) is very useful for creating build scripts, see this short video
-# for a quick introduction:
-# http://railscasts.com/episodes/66-custom-rake-tasks
+# You can define any Rake tasks to support your application here (or in any file
+# ending in .rake in this directory).
+#
+# Rake (Ruby Make) is very useful for creating build scripts, see this short video
+# for a quick introduction:
+# http://railscasts.com/episodes/66-custom-rake-tasks

data/pattern/clear_flags_test.rb

@@ -1,18 +1,18 @@
-Pattern.create do
-  tester.set_timeset 'tp0', 20
-  dut.pin(:ss).drive 1
-  dut.pin(:sclk).drive 0
-  dut.pin(:mosi).drive 0
-  dut.pin(:miso).dont_care
-  
-  tester.cycle
-
-  out_data = Origen::Registers::Reg.dummy(12).write 7
-  in_data = Origen::Registers::Reg.dummy(12).read 0x5a5
-  cc 'shifting 12-bits lsb first, 0x7 out, 0x5a5 in'
-  dut.spi.shift master_out: out_data, master_in: in_data
-
-  tester.cycle
-  cc 'shifting in same register, should be no compares'
-  dut.spi.shift master_in: in_data
+Pattern.create do
+  tester.set_timeset 'tp0', 20
+  dut.pin(:ss).drive 1
+  dut.pin(:sclk).drive 0
+  dut.pin(:mosi).drive 0
+  dut.pin(:miso).dont_care
+  
+  tester.cycle
+
+  out_data = Origen::Registers::Reg.dummy(12).write 7
+  in_data = Origen::Registers::Reg.dummy(12).read 0x5a5
+  cc 'shifting 12-bits lsb first, 0x7 out, 0x5a5 in'
+  dut.spi.shift master_out: out_data, master_in: in_data
+
+  tester.cycle
+  cc 'shifting in same register, should be no compares'
+  dut.spi.shift master_in: in_data
 end

data/pattern/clock_test.rb

@@ -1,39 +1,39 @@
-Pattern.create do
-  tester.set_timeset 'tp0', 20
-  dut.pin(:ss).drive 1
-  dut.pin(:sclk).drive 0
-  dut.pin(:mosi).drive 0
-  dut.pin(:miso).dont_care
-  
-  tester.cycle
-  dut.spi.sclk_cycle
-  tester.cycle
-  
-  cc 'change multiple to 2'
-  dut.spi.clk_multiple = 2
-  dut.spi.sclk_cycle
-  tester.cycle
-  
-  cc 'change multiple to 80'
-  dut.spi.clk_multiple = 80
-  dut.spi.sclk_cycle
-  tester.cycle
-  
-  cc 'change clock format and repeat'
-  dut.pin(:sclk).drive 1
-  dut.spi.clk_format = :rh
-  dut.spi.clk_multiple = 1
-  dut.spi.sclk_cycle
-  tester.cycle
-
-  cc 'change multiple to 2'
-  dut.spi.clk_multiple = 2
-  dut.spi.sclk_cycle
-  tester.cycle
-  
-  cc 'change multiple to 80'
-  dut.spi.clk_multiple = 80
-  dut.spi.sclk_cycle
-  tester.cycle
-  
+Pattern.create do
+  tester.set_timeset 'tp0', 20
+  dut.pin(:ss).drive 1
+  dut.pin(:sclk).drive 0
+  dut.pin(:mosi).drive 0
+  dut.pin(:miso).dont_care
+  
+  tester.cycle
+  dut.spi.sclk_cycle
+  tester.cycle
+  
+  cc 'change multiple to 2'
+  dut.spi.clk_multiple = 2
+  dut.spi.sclk_cycle
+  tester.cycle
+  
+  cc 'change multiple to 80'
+  dut.spi.clk_multiple = 80
+  dut.spi.sclk_cycle
+  tester.cycle
+  
+  cc 'change clock format and repeat'
+  dut.pin(:sclk).drive 1
+  dut.spi.clk_format = :rh
+  dut.spi.clk_multiple = 1
+  dut.spi.sclk_cycle
+  tester.cycle
+
+  cc 'change multiple to 2'
+  dut.spi.clk_multiple = 2
+  dut.spi.sclk_cycle
+  tester.cycle
+  
+  cc 'change multiple to 80'
+  dut.spi.clk_multiple = 80
+  dut.spi.sclk_cycle
+  tester.cycle
+  
 end

data/pattern/keep_ss_active.rb

@@ -1,25 +1,25 @@
-Pattern.create do
-  tester.set_timeset 'tp0', 20
-  dut.pin(:ss).drive 1
-  dut.pin(:sclk).drive 0
-  dut.pin(:mosi).drive 0
-  dut.pin(:miso).dont_care
-  
-  tester.cycle
-
-  out_data = Origen::Registers::Reg.dummy(12).write 7
-  in_data = Origen::Registers::Reg.dummy(12).read 0x5a5
-  cc 'shifting 12-bits lsb first, 0x7 out, 0x5a5 in -- keeping ss active'
-  dut.spi.shift master_out: out_data, master_in: in_data, keep_ss_active: true
-  
-  cc 'cycle with ss active'
-  tester.cycle
-
-  cc 'shifting 12-bits lsb first, 0x7 out, 0x5a5 in -- allow ss inactive'
-  in_data.read
-  dut.spi.shift master_out: out_data, master_in: in_data
-  
-  cc 'cycle with ss inactive'
-  tester.cycle
-
+Pattern.create do
+  tester.set_timeset 'tp0', 20
+  dut.pin(:ss).drive 1
+  dut.pin(:sclk).drive 0
+  dut.pin(:mosi).drive 0
+  dut.pin(:miso).dont_care
+  
+  tester.cycle
+
+  out_data = Origen::Registers::Reg.dummy(12).write 7
+  in_data = Origen::Registers::Reg.dummy(12).read 0x5a5
+  cc 'shifting 12-bits lsb first, 0x7 out, 0x5a5 in -- keeping ss active'
+  dut.spi.shift master_out: out_data, master_in: in_data, keep_ss_active: true
+  
+  cc 'cycle with ss active'
+  tester.cycle
+
+  cc 'shifting 12-bits lsb first, 0x7 out, 0x5a5 in -- allow ss inactive'
+  in_data.read
+  dut.spi.shift master_out: out_data, master_in: in_data
+  
+  cc 'cycle with ss inactive'
+  tester.cycle
+
 end

data/pattern/overlay_test.rb

@@ -1,18 +1,18 @@
-Pattern.create do
-  tester.set_timeset 'tp0', 20
-  dut.pin(:ss).drive 1
-  dut.pin(:sclk).drive 0
-  dut.pin(:mosi).drive 0
-  dut.pin(:miso).dont_care
-  
-  tester.cycle
-  tester.overlay_style = :label
-  out_data = Origen::Registers::Reg.dummy(12).write 7
-  out_data.bits[3..0].overlay 'heres_the_label'
-  dut.spi.shift master_out: out_data
-  
-  cc 'repeat test reversing bit order'
-  dut.spi.data_order = :msb0
-  out_data.bits[3..0].overlay 'heres_the_other_label'
-  dut.spi.shift master_out: out_data
+Pattern.create do
+  tester.set_timeset 'tp0', 20
+  dut.pin(:ss).drive 1
+  dut.pin(:sclk).drive 0
+  dut.pin(:mosi).drive 0
+  dut.pin(:miso).dont_care
+  
+  tester.cycle
+  tester.overlay_style = :label
+  out_data = Origen::Registers::Reg.dummy(12).write 7
+  out_data.bits[3..0].overlay 'heres_the_label'
+  dut.spi.shift master_out: out_data
+  
+  cc 'repeat test reversing bit order'
+  dut.spi.data_order = :msb0
+  out_data.bits[3..0].overlay 'heres_the_other_label'
+  dut.spi.shift master_out: out_data
 end

data/pattern/shift_test.rb

@@ -1,67 +1,67 @@
-Pattern.create do
-  tester.set_timeset 'tp0', 20
-  dut.pin(:ss).drive 1
-  dut.pin(:sclk).drive 0
-  dut.pin(:mosi).drive 0
-  dut.pin(:miso).dont_care
-  
-  tester.cycle
-
-  out_data = Origen::Registers::Reg.dummy(12).write 7
-  in_data = Origen::Registers::Reg.dummy(12).read 0x5a5
-  cc 'shifting 12-bits lsb first, 0x7 out, 0x5a5 in'
-  dut.spi.shift master_out: out_data, master_in: in_data
-  
-  tester.cycle
-  
-  cc 'repeat 12-bits lsb first, 0x7 out, 0x5a5 in; clock multiple = 4'
-  out_data.write 7
-  in_data.read 0x5a5
-  dut.spi.clk_multiple = 4
-  dut.spi.shift master_out: out_data, master_in: in_data
-  
-  tester.cycle
-  
-  cc 'repeat 12-bits, 0x7 out, 0x5a5 in; clock multiple = 4, with msb first, move miso compare to cycle 3'
-  out_data.write 7
-  in_data.read 0x5a5
-  dut.spi.data_order = :msb0
-  dut.spi.miso_compare_cycle = 3
-  dut.spi.shift master_out: out_data, master_in: in_data
-
-  tester.cycle
-  
-  cc 'Now check bit masking'
-  cc 'shift 0xa5a, 12-bits, msb first, multiple = 1, clk format :rh, all bits masked'
-  dut.spi.clk_format = :rh
-  dut.spi.clk_multiple = 1
-  dut.spi.shift master_out: 0xa5a, size: 12
-  
-  tester.cycle
-  
-  cc 'repeat same, comparing for LLLL_XXXX_HHHH, clock back to :rl'
-  dut.spi.clk_format = :rl
-  in_data.write 0xf
-  in_data.bits[11..8].read
-  in_data.bits[7..4].clear_flags
-  in_data.bits[3..0].read
-  dut.spi.shift master_out: 0xa5a, master_in: in_data
-  
-  tester.cycle
-  
-  cc 'test capture'
-  in_data.bits[11..8].read
-  in_data.bits[7..4].store
-  in_data.bits[3..0].read
-  dut.spi.shift master_out: 0xa5a, master_in: in_data
-  
-  tester.cycle
-  
-  # cc 'test overlay, label should appear at bit 3'
-  # out_data.write 0xa5a
-  # out_data.bits[3..0].overlay 'heres_the_label'
-  # tester.overlay_style = :label
-  # dut.spi.shift master_out: out_data
-  
-  # tester.cycle
+Pattern.create do
+  tester.set_timeset 'tp0', 20
+  dut.pin(:ss).drive 1
+  dut.pin(:sclk).drive 0
+  dut.pin(:mosi).drive 0
+  dut.pin(:miso).dont_care
+  
+  tester.cycle
+
+  out_data = Origen::Registers::Reg.dummy(12).write 7
+  in_data = Origen::Registers::Reg.dummy(12).read 0x5a5
+  cc 'shifting 12-bits lsb first, 0x7 out, 0x5a5 in'
+  dut.spi.shift master_out: out_data, master_in: in_data
+  
+  tester.cycle
+  
+  cc 'repeat 12-bits lsb first, 0x7 out, 0x5a5 in; clock multiple = 4'
+  out_data.write 7
+  in_data.read 0x5a5
+  dut.spi.clk_multiple = 4
+  dut.spi.shift master_out: out_data, master_in: in_data
+  
+  tester.cycle
+  
+  cc 'repeat 12-bits, 0x7 out, 0x5a5 in; clock multiple = 4, with msb first, move miso compare to cycle 3'
+  out_data.write 7
+  in_data.read 0x5a5
+  dut.spi.data_order = :msb0
+  dut.spi.miso_compare_cycle = 3
+  dut.spi.shift master_out: out_data, master_in: in_data
+
+  tester.cycle
+  
+  cc 'Now check bit masking'
+  cc 'shift 0xa5a, 12-bits, msb first, multiple = 1, clk format :rh, all bits masked'
+  dut.spi.clk_format = :rh
+  dut.spi.clk_multiple = 1
+  dut.spi.shift master_out: 0xa5a, size: 12
+  
+  tester.cycle
+  
+  cc 'repeat same, comparing for LLLL_XXXX_HHHH, clock back to :rl'
+  dut.spi.clk_format = :rl
+  in_data.write 0xf
+  in_data.bits[11..8].read
+  in_data.bits[7..4].clear_flags
+  in_data.bits[3..0].read
+  dut.spi.shift master_out: 0xa5a, master_in: in_data
+  
+  tester.cycle
+  
+  cc 'test capture'
+  in_data.bits[11..8].read
+  in_data.bits[7..4].store
+  in_data.bits[3..0].read
+  dut.spi.shift master_out: 0xa5a, master_in: in_data
+  
+  tester.cycle
+  
+  # cc 'test overlay, label should appear at bit 3'
+  # out_data.write 0xa5a
+  # out_data.bits[3..0].overlay 'heres_the_label'
+  # tester.overlay_style = :label
+  # dut.spi.shift master_out: out_data
+  
+  # tester.cycle
 end

data/templates/web/index.md.erb

@@ -1,87 +1,87 @@
-% render "layouts/basic.html" do
-
-%# HTML tags can be embedded in mark down files if you want to do specific custom
-%# formatting like this, but in most cases that is not required.
-<h1><%= Origen.app.namespace %> <span style="font-size: 14px">(<%= Origen.app.version %>)</span></h1>
-
-### Purpose
-
-This plugin implements SPI protocol with the tester acting as the master. There are 4 pins standard to SPI, 
-however only sclk is required by this plugin. Any pins that aren't provided are ignored. This plugin seeks
-to be very flexible given that the SPI standard is itself very flexible.
-
-### How To Install
-
-In your Gemfile add:
-
-~~~ruby
-gem "<%= Origen.app.name %>"
-~~~
-
-or if your application is a plugin, then add this to your <code>.gemspec</code>
-
-~~~ruby
-spec.add_runtime_dependency "<%= Origen.app.name %>", ">= <%= Origen.app.version %>"
-~~~
-
-__NOTE:__  In the case of a plugin, you will also need to <code>require '<%= Origen.app.name %>'</code> somewhere in your environment.
-
-
-### How To Use
-
-The spi driver is intended to be instantiated as a sub_block. The configuration can be passed in as a hash and / or 
-can be changed after instantiation. See API for more details.
-
-~~~ruby
-        sub_block :spi, class_name:   'OrigenSpi::Driver',
-                        sclk_pin:     dut.pin(:sclk),
-                        mosi_pin:     dut.pin(:mosi),
-                        miso_pin:     dut.pin(:miso),
-                        ss_pin:       dut.pin(:ss),
-                        # :rl - return low - input data changes while sclk is low and is latched on rising edge
-                        clk_format:   :rl,
-                        # drive state of 0 activates the slave port
-                        ss_active:    0,
-                        # wait time after ss_active and before any sclk activity
-                        clk_wait_time: {time_in_cycles: 2},
-                        # number of sclks per tester.cycle
-                        clk_multiple: 1,
-                        data_order:   :lsb0
-~~~
-
-~~~ruby
-  # configuration can be changed after instantiation like this
-  dut.spi.clk_multiple = 80
-  dut.spi.miso_compare_cycle = 79
-  dut.spi.ss_pin = nil
-~~~
-
-Once the driver is instantiated shift operations can be performed by calls to the shift method (overlay/store/masking etc. is handled):
-
-~~~ruby
-  # shift out, masking input compares
-  dut.spi.shift master_out: 0xFF, size: 32
-  
-  # shift out, register - size doesn't need to be passed when register is provided
-  dut.spi.shift master_out: dut.my_reg
-  
-  # shift in read examples:
-  dut.spi.shift master_in: 0xFF, size: 32
-  
-  # provide a register to mask or store (mark the bits appropriately)
-  dut.spi.shift master_in: dut.my_reg
-  
-  # simultaneous shift in/out
-  dut.spi.shift master_out: some_value_or_reg, master_in: some_other_value_or_reg
-~~~
-
-
-### How To Setup a Development Environment
-
-To setup a development environment:
-
-~~~
-  git clone https://github.com/Origen-SDK/origen_spi.git
-~~~
-
-% end
+% render "layouts/basic.html" do
+
+%# HTML tags can be embedded in mark down files if you want to do specific custom
+%# formatting like this, but in most cases that is not required.
+<h1><%= Origen.app.namespace %> <span style="font-size: 14px">(<%= Origen.app.version %>)</span></h1>
+
+### Purpose
+
+This plugin implements SPI protocol with the tester acting as the master. There are 4 pins standard to SPI, 
+however only sclk is required by this plugin. Any pins that aren't provided are ignored. This plugin seeks
+to be very flexible given that the SPI standard is itself very flexible.
+
+### How To Install
+
+In your Gemfile add:
+
+~~~ruby
+gem "<%= Origen.app.name %>"
+~~~
+
+or if your application is a plugin, then add this to your <code>.gemspec</code>
+
+~~~ruby
+spec.add_runtime_dependency "<%= Origen.app.name %>", ">= <%= Origen.app.version %>"
+~~~
+
+__NOTE:__  In the case of a plugin, you will also need to <code>require '<%= Origen.app.name %>'</code> somewhere in your environment.
+
+
+### How To Use
+
+The spi driver is intended to be instantiated as a sub_block. The configuration can be passed in as a hash and / or 
+can be changed after instantiation. See API for more details.
+
+~~~ruby
+        sub_block :spi, class_name:   'OrigenSpi::Driver',
+                        sclk_pin:     dut.pin(:sclk),
+                        mosi_pin:     dut.pin(:mosi),
+                        miso_pin:     dut.pin(:miso),
+                        ss_pin:       dut.pin(:ss),
+                        # :rl - return low - input data changes while sclk is low and is latched on rising edge
+                        clk_format:   :rl,
+                        # drive state of 0 activates the slave port
+                        ss_active:    0,
+                        # wait time after ss_active and before any sclk activity
+                        clk_wait_time: {time_in_cycles: 2},
+                        # number of sclks per tester.cycle
+                        clk_multiple: 1,
+                        data_order:   :lsb0
+~~~
+
+~~~ruby
+  # configuration can be changed after instantiation like this
+  dut.spi.clk_multiple = 80
+  dut.spi.miso_compare_cycle = 79
+  dut.spi.ss_pin = nil
+~~~
+
+Once the driver is instantiated shift operations can be performed by calls to the shift method (overlay/store/masking etc. is handled):
+
+~~~ruby
+  # shift out, masking input compares
+  dut.spi.shift master_out: 0xFF, size: 32
+  
+  # shift out, register - size doesn't need to be passed when register is provided
+  dut.spi.shift master_out: dut.my_reg
+  
+  # shift in read examples:
+  dut.spi.shift master_in: 0xFF, size: 32
+  
+  # provide a register to mask or store (mark the bits appropriately)
+  dut.spi.shift master_in: dut.my_reg
+  
+  # simultaneous shift in/out
+  dut.spi.shift master_out: some_value_or_reg, master_in: some_other_value_or_reg
+~~~
+
+
+### How To Setup a Development Environment
+
+To setup a development environment:
+
+~~~
+  git clone https://github.com/Origen-SDK/origen_spi.git
+~~~
+
+% end