origen_spi 0.1.0 → 0.1.1

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checksums.yaml CHANGED
@@ -1,7 +1,7 @@
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data/config/commands.rb CHANGED
@@ -39,13 +39,19 @@ when "examples", "test"
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  status = 0
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  ARGV = %w(pattern/clock_test.rb -t default.rb -e default.rb -r approved)
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- load "#{Origen.top}/lib/origen/commands/generate.rb"# #ARGV = %w(some_pattern -t debug -r approved)
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+ load "#{Origen.top}/lib/origen/commands/generate.rb"
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  ARGV = %w(pattern/shift_test.rb -t default.rb -e default.rb -r approved)
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- load "#{Origen.top}/lib/origen/commands/generate.rb"# #ARGV = %w(some_pattern -t debug -r approved)
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+ load "#{Origen.top}/lib/origen/commands/generate.rb"
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  ARGV = %w(pattern/overlay_test.rb -t default.rb -e default.rb -r approved)
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- load "#{Origen.top}/lib/origen/commands/generate.rb"# #ARGV = %w(some_pattern -t debug -r approved)
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+ load "#{Origen.top}/lib/origen/commands/generate.rb"
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+
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+ ARGV = %w(pattern/keep_ss_active.rb -t default.rb -e default.rb -r approved)
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+ load "#{Origen.top}/lib/origen/commands/generate.rb"
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+
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+ ARGV = %w(pattern/clear_flags_test.rb -t default.rb -e default.rb -r approved)
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+ load "#{Origen.top}/lib/origen/commands/generate.rb"
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  if Origen.app.stats.changed_files == 0 &&
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  Origen.app.stats.new_files == 0 &&
data/config/version.rb CHANGED
@@ -1,7 +1,7 @@
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  module OrigenSpi
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  MAJOR = 0
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  MINOR = 1
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- BUGFIX = 0
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+ BUGFIX = 1
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  DEV = nil
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  VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
@@ -233,7 +233,8 @@ module OrigenSpi
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  # spi_instance.shift master_in: in_cmp_reg
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  def shift(options = {})
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  options = {
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- master_out: 0
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+ master_out: 0,
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+ keep_ss_active: false
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  }.merge(options)
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  validate_settings
@@ -290,7 +291,11 @@ module OrigenSpi
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  @sclk_pin.drive @clk_format == :rl ? 0 : 1
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  @miso_pin.dont_care unless @miso_pin.nil?
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  @mosi_pin.drive 0 unless @mosi_pin.nil?
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- @ss_pin.drive @ss_active == 1 ? 0 : 1 unless @ss_pin.nil?
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+ @ss_pin.drive @ss_active == 1 ? 0 : 1 unless @ss_pin.nil? || options[:keep_ss_active]
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+
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+ # clear flags if registers were provided
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+ options[:master_out].clear_flags if options[:master_out].respond_to?(:clear_flags)
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+ options[:master_in].clear_flags if options[:master_in].respond_to?(:clear_flags)
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  end
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  # Internal method
@@ -0,0 +1,18 @@
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+ Pattern.create do
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+ tester.set_timeset 'tp0', 20
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+ dut.pin(:ss).drive 1
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+ dut.pin(:sclk).drive 0
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+ dut.pin(:mosi).drive 0
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+ dut.pin(:miso).dont_care
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+
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+ tester.cycle
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+
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+ out_data = Origen::Registers::Reg.dummy(12).write 7
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+ in_data = Origen::Registers::Reg.dummy(12).read 0x5a5
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+ cc 'shifting 12-bits lsb first, 0x7 out, 0x5a5 in'
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+ dut.spi.shift master_out: out_data, master_in: in_data
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+
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+ tester.cycle
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+ cc 'shifting in same register, should be no compares'
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+ dut.spi.shift master_in: in_data
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+ end
@@ -0,0 +1,25 @@
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+ Pattern.create do
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+ tester.set_timeset 'tp0', 20
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+ dut.pin(:ss).drive 1
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+ dut.pin(:sclk).drive 0
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+ dut.pin(:mosi).drive 0
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+ dut.pin(:miso).dont_care
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+
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+ tester.cycle
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+
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+ out_data = Origen::Registers::Reg.dummy(12).write 7
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+ in_data = Origen::Registers::Reg.dummy(12).read 0x5a5
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+ cc 'shifting 12-bits lsb first, 0x7 out, 0x5a5 in -- keeping ss active'
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+ dut.spi.shift master_out: out_data, master_in: in_data, keep_ss_active: true
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+
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+ cc 'cycle with ss active'
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+ tester.cycle
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+
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+ cc 'shifting 12-bits lsb first, 0x7 out, 0x5a5 in -- allow ss inactive'
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+ in_data.read
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+ dut.spi.shift master_out: out_data, master_in: in_data
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+
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+ cc 'cycle with ss inactive'
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+ tester.cycle
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+
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+ end
@@ -15,12 +15,16 @@ Pattern.create do
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  tester.cycle
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  cc 'repeat 12-bits lsb first, 0x7 out, 0x5a5 in; clock multiple = 4'
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+ out_data.write 7
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+ in_data.read 0x5a5
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  dut.spi.clk_multiple = 4
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  dut.spi.shift master_out: out_data, master_in: in_data
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  tester.cycle
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  cc 'repeat 12-bits, 0x7 out, 0x5a5 in; clock multiple = 4, with msb first, move miso compare to cycle 3'
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+ out_data.write 7
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+ in_data.read 0x5a5
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  dut.spi.data_order = :msb0
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  dut.spi.miso_compare_cycle = 3
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  dut.spi.shift master_out: out_data, master_in: in_data
@@ -46,7 +50,9 @@ Pattern.create do
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  tester.cycle
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  cc 'test capture'
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+ in_data.bits[11..8].read
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  in_data.bits[7..4].store
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+ in_data.bits[3..0].read
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  dut.spi.shift master_out: 0xa5a, master_in: in_data
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  tester.cycle
@@ -56,6 +56,25 @@ can be changed after instantiation. See API for more details.
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  dut.spi.ss_pin = nil
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  ~~~
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+ Once the driver is instantiated shift operations can be performed by calls to the shift method (overlay/store/masking etc. is handled):
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+
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+ ~~~ruby
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+ # shift out, masking input compares
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+ dut.spi.shift master_out: 0xFF, size: 32
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+
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+ # shift out, register - size doesn't need to be passed when register is provided
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+ dut.spi.shift master_out: dut.my_reg
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+
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+ # shift in read examples:
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+ dut.spi.shift master_in: 0xFF, size: 32
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+
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+ # provide a register to mask or store (mark the bits appropriately)
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+ dut.spi.shift master_in: dut.my_reg
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+
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+ # simultaneous shift in/out
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+ dut.spi.shift master_out: some_value_or_reg, master_in: some_other_value_or_reg
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+ ~~~
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+
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  ### How To Setup a Development Environment
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metadata CHANGED
@@ -1,14 +1,14 @@
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  --- !ruby/object:Gem::Specification
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  name: origen_spi
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  version: !ruby/object:Gem::Version
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- version: 0.1.0
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+ version: 0.1.1
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  platform: ruby
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  authors:
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  - Paul DeRouen
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2017-12-18 00:00:00.000000000 Z
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+ date: 2018-08-02 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: origen
@@ -53,7 +53,9 @@ files:
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  - lib/origen_spi.rb
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  - lib/origen_spi/driver.rb
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  - lib/tasks/origen_spi.rake
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+ - pattern/clear_flags_test.rb
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  - pattern/clock_test.rb
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+ - pattern/keep_ss_active.rb
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  - pattern/overlay_test.rb
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  - pattern/shift_test.rb
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  - templates/web/index.md.erb