origen_sim 0.20.1 → 0.20.2

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checksums.yaml CHANGED
@@ -1,7 +1,7 @@
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@@ -1,7 +1,7 @@
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  module OrigenSim
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  MAJOR = 0
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  MINOR = 20
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- BUGFIX = 1
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+ BUGFIX = 2
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  DEV = nil
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  VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
@@ -1084,10 +1084,12 @@ PLI_INT32 bridge_on_miscompare(PLI_BYTE8 * user_dat) {
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  vpi_free_object(argv);
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- if (received) {
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+ if (received == 1 || received == 0) {
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  origen_log(LOG_ERROR, "Miscompare on pin %s, expected %d received %d", pin_name, expected, received);
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+ } else if (received == -2) {
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+ origen_log(LOG_ERROR, "Miscompare on pin %s, expected %d received Z", pin_name, expected);
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  } else {
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- origen_log(LOG_ERROR, "Miscompare on pin %s, expected %d received X or Z", pin_name, expected);
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+ origen_log(LOG_ERROR, "Miscompare on pin %s, expected %d received X", pin_name, expected);
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  }
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  error_count++;
@@ -1116,11 +1118,7 @@ PLI_INT32 bridge_on_miscompare(PLI_BYTE8 * user_dat) {
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  strcpy((*miscompare).pin_name, pin_name);
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  (*miscompare).cycle = cycle_count;
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  (*miscompare).expected = expected;
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- if (received) {
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- (*miscompare).received = received;
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- } else {
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- (*miscompare).received = -1;
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- }
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+ (*miscompare).received = received;
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  }
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  transaction_error_count++;
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  }
@@ -10,27 +10,25 @@ module OrigenSim
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  @last_message_at = Time.now
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  super do
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  begin
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- line = ''
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+ line = nil
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  while @continue
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  loop do
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  out = @socket.gets
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- if out.nil?
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- line += ''
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- break
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- end
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+ break if out.nil?
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- unless line.empty?
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+ unless !line || line.empty?
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  # If there's already stuff in the current line,
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  # remove the VPI cruft and leave just the remainder of the message.
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  out = out.split(' ', 2)[-1]
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  end
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+ line ||= ''
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  if out.chomp.end_with?(OrigenSim::Simulator::MULTIPART_LOGGER_TOKEN)
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  # Part of a multipart message. Add this to the current line
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  # and grab the next piece.
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  line += out.chomp.gsub(OrigenSim::Simulator::MULTIPART_LOGGER_TOKEN, '')
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  else
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- # Either a single message or a the end of a multi-part message.
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+ # Either a single message or the end of a multi-part message.
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  # Add this to the line break to print the output to the console.
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  line += out
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  break
@@ -71,7 +69,7 @@ module OrigenSim
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  end
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  end
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  end
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- line = ''
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+ line = nil
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  @last_message_at = Time.now
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  end
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  end
@@ -328,7 +328,7 @@ module OrigenSim
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  end
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  diffs.each do |position, received, expected|
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- if received == -1
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+ if received == -1 || received == -2
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  reg_or_val[position].unknown = true
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  else
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  reg_or_val[position].data = received
@@ -377,7 +377,7 @@ module OrigenSim
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  if actual_data_available
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  actual = reg_or_val
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  diffs.each do |position, received, expected|
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- if received == -1
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+ if received == -1 || received == -2
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  actual = '?' * reg_or_val.to_s(16).size
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  break
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  elsif received == 1
@@ -0,0 +1,19 @@
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+ # This pattern is expected to fail, use it to visually inspect that OrigenSim's
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+ # error reporting is working
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+ Pattern.create do
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+ ss "Test a register-level miscompare"
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+ dut.cmd.write!(0x1234_5678)
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+ dut.cmd.read!(0x1233_5678)
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+
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+ ss "Test a bit-level miscompare, expect 1"
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+ dut.ana_test.write!(0)
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+ dut.ana_test.bgap_out.read!(1)
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+ ss "Test a bit-level miscompare, expect 0"
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+ dut.ana_test.bgap_out.write!(1)
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+ dut.ana_test.bgap_out.read!(0)
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+
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+ if tester.sim?
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+ ss "Test reading an X register value, expect LSB nibble to be 0"
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+ dut.x_reg[3..0].read!(0)
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+ end
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+ end
@@ -184,9 +184,6 @@ Pattern.create do
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  unless dut.parallel_read.data == 0x7707_7077
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  OrigenSim.error "PARALLEL_READ register did not sync from simulation"
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  end
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-
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- #ss "Test reading an X register value"
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- #dut.x_reg.read!(0)
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  end
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  ss "Do some operations with the counter, just for fun"
@@ -62,7 +62,12 @@ module pin_driver(pin, sync);
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  // pin compare failure logger
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  always @(posedge error) begin
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  //$display("!4![%t] Miscompare on pin %s, expected %d received %d", $time, pin_name, data[0], pin);
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- $bridge_on_miscompare(pin_name, data[0], pin);
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+ if (pin == 1'b0 || pin == 1'b1)
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+ $bridge_on_miscompare(pin_name, data[0], pin);
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+ else if (pin == 1'bz)
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+ $bridge_on_miscompare(pin_name, data[0], -2);
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+ else
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+ $bridge_on_miscompare(pin_name, data[0], -1);
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  end
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  // SMcG - needs more work, causes non-genuine fails in OrigenSim test case
metadata CHANGED
@@ -1,14 +1,14 @@
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  --- !ruby/object:Gem::Specification
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  name: origen_sim
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  version: !ruby/object:Gem::Version
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- version: 0.20.1
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+ version: 0.20.2
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  platform: ruby
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  authors:
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  - Stephen McGinty
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2019-05-28 00:00:00.000000000 Z
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+ date: 2019-05-30 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: origen
@@ -99,6 +99,7 @@ files:
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  - lib/origen_sim_dev/ip.rb
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  - lib/tasks/origen_sim.rake
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  - pattern/concurrent_ip.rb
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+ - pattern/fails.rb
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  - pattern/ip1_test.rb
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  - pattern/ip2_test.rb
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  - pattern/test.rb