origen_sim 0.20.1 → 0.20.2

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checksums.yaml CHANGED
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@@ -1,7 +1,7 @@
1
1
  module OrigenSim
2
2
  MAJOR = 0
3
3
  MINOR = 20
4
- BUGFIX = 1
4
+ BUGFIX = 2
5
5
  DEV = nil
6
6
 
7
7
  VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
@@ -1084,10 +1084,12 @@ PLI_INT32 bridge_on_miscompare(PLI_BYTE8 * user_dat) {
1084
1084
 
1085
1085
  vpi_free_object(argv);
1086
1086
 
1087
- if (received) {
1087
+ if (received == 1 || received == 0) {
1088
1088
  origen_log(LOG_ERROR, "Miscompare on pin %s, expected %d received %d", pin_name, expected, received);
1089
+ } else if (received == -2) {
1090
+ origen_log(LOG_ERROR, "Miscompare on pin %s, expected %d received Z", pin_name, expected);
1089
1091
  } else {
1090
- origen_log(LOG_ERROR, "Miscompare on pin %s, expected %d received X or Z", pin_name, expected);
1092
+ origen_log(LOG_ERROR, "Miscompare on pin %s, expected %d received X", pin_name, expected);
1091
1093
  }
1092
1094
 
1093
1095
  error_count++;
@@ -1116,11 +1118,7 @@ PLI_INT32 bridge_on_miscompare(PLI_BYTE8 * user_dat) {
1116
1118
  strcpy((*miscompare).pin_name, pin_name);
1117
1119
  (*miscompare).cycle = cycle_count;
1118
1120
  (*miscompare).expected = expected;
1119
- if (received) {
1120
- (*miscompare).received = received;
1121
- } else {
1122
- (*miscompare).received = -1;
1123
- }
1121
+ (*miscompare).received = received;
1124
1122
  }
1125
1123
  transaction_error_count++;
1126
1124
  }
@@ -10,27 +10,25 @@ module OrigenSim
10
10
  @last_message_at = Time.now
11
11
  super do
12
12
  begin
13
- line = ''
13
+ line = nil
14
14
  while @continue
15
15
  loop do
16
16
  out = @socket.gets
17
- if out.nil?
18
- line += ''
19
- break
20
- end
17
+ break if out.nil?
21
18
 
22
- unless line.empty?
19
+ unless !line || line.empty?
23
20
  # If there's already stuff in the current line,
24
21
  # remove the VPI cruft and leave just the remainder of the message.
25
22
  out = out.split(' ', 2)[-1]
26
23
  end
27
24
 
25
+ line ||= ''
28
26
  if out.chomp.end_with?(OrigenSim::Simulator::MULTIPART_LOGGER_TOKEN)
29
27
  # Part of a multipart message. Add this to the current line
30
28
  # and grab the next piece.
31
29
  line += out.chomp.gsub(OrigenSim::Simulator::MULTIPART_LOGGER_TOKEN, '')
32
30
  else
33
- # Either a single message or a the end of a multi-part message.
31
+ # Either a single message or the end of a multi-part message.
34
32
  # Add this to the line break to print the output to the console.
35
33
  line += out
36
34
  break
@@ -71,7 +69,7 @@ module OrigenSim
71
69
  end
72
70
  end
73
71
  end
74
- line = ''
72
+ line = nil
75
73
  @last_message_at = Time.now
76
74
  end
77
75
  end
@@ -328,7 +328,7 @@ module OrigenSim
328
328
  end
329
329
 
330
330
  diffs.each do |position, received, expected|
331
- if received == -1
331
+ if received == -1 || received == -2
332
332
  reg_or_val[position].unknown = true
333
333
  else
334
334
  reg_or_val[position].data = received
@@ -377,7 +377,7 @@ module OrigenSim
377
377
  if actual_data_available
378
378
  actual = reg_or_val
379
379
  diffs.each do |position, received, expected|
380
- if received == -1
380
+ if received == -1 || received == -2
381
381
  actual = '?' * reg_or_val.to_s(16).size
382
382
  break
383
383
  elsif received == 1
@@ -0,0 +1,19 @@
1
+ # This pattern is expected to fail, use it to visually inspect that OrigenSim's
2
+ # error reporting is working
3
+ Pattern.create do
4
+ ss "Test a register-level miscompare"
5
+ dut.cmd.write!(0x1234_5678)
6
+ dut.cmd.read!(0x1233_5678)
7
+
8
+ ss "Test a bit-level miscompare, expect 1"
9
+ dut.ana_test.write!(0)
10
+ dut.ana_test.bgap_out.read!(1)
11
+ ss "Test a bit-level miscompare, expect 0"
12
+ dut.ana_test.bgap_out.write!(1)
13
+ dut.ana_test.bgap_out.read!(0)
14
+
15
+ if tester.sim?
16
+ ss "Test reading an X register value, expect LSB nibble to be 0"
17
+ dut.x_reg[3..0].read!(0)
18
+ end
19
+ end
@@ -184,9 +184,6 @@ Pattern.create do
184
184
  unless dut.parallel_read.data == 0x7707_7077
185
185
  OrigenSim.error "PARALLEL_READ register did not sync from simulation"
186
186
  end
187
-
188
- #ss "Test reading an X register value"
189
- #dut.x_reg.read!(0)
190
187
  end
191
188
 
192
189
  ss "Do some operations with the counter, just for fun"
@@ -62,7 +62,12 @@ module pin_driver(pin, sync);
62
62
  // pin compare failure logger
63
63
  always @(posedge error) begin
64
64
  //$display("!4![%t] Miscompare on pin %s, expected %d received %d", $time, pin_name, data[0], pin);
65
- $bridge_on_miscompare(pin_name, data[0], pin);
65
+ if (pin == 1'b0 || pin == 1'b1)
66
+ $bridge_on_miscompare(pin_name, data[0], pin);
67
+ else if (pin == 1'bz)
68
+ $bridge_on_miscompare(pin_name, data[0], -2);
69
+ else
70
+ $bridge_on_miscompare(pin_name, data[0], -1);
66
71
  end
67
72
 
68
73
  // SMcG - needs more work, causes non-genuine fails in OrigenSim test case
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: origen_sim
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.20.1
4
+ version: 0.20.2
5
5
  platform: ruby
6
6
  authors:
7
7
  - Stephen McGinty
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2019-05-28 00:00:00.000000000 Z
11
+ date: 2019-05-30 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: origen
@@ -99,6 +99,7 @@ files:
99
99
  - lib/origen_sim_dev/ip.rb
100
100
  - lib/tasks/origen_sim.rake
101
101
  - pattern/concurrent_ip.rb
102
+ - pattern/fails.rb
102
103
  - pattern/ip1_test.rb
103
104
  - pattern/ip2_test.rb
104
105
  - pattern/test.rb