origen_sim 0.9.0 → 0.10.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA1:
-  metadata.gz: f670da6bba360fa76ac30b10cd097cde48d6353a
-  data.tar.gz: 07a1c407163212fd4fd04b45336ff399751155e2
+  metadata.gz: 3b31bfc2f252031780f05373507dbbb75db36300
+  data.tar.gz: fb37cfeb67cde82e1f829630b36ea6752e581189
 SHA512:
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+  data.tar.gz: 865533e70e134f220837accecdbefa616f1df14f8cf185bc3584a923e3c5af4afe2d5a3b7662221de125b0b45c5eb975569bfe51da679dc442d10e4c5f38e0df

data/config/application.rb

@@ -57,7 +57,9 @@ class OrigenSimApplication < Origen::Application
 
   # An example of how to set application specific LSF parameters
   #config.lsf.project = "msg.te"
-  
+  config.lsf.queue = ENV["ORIGEN_LSF_QUEUE"] if ENV["ORIGEN_LSF_QUEUE"]
+  config.lsf.resource = ENV["ORIGEN_LSF_RESOURCE"] if ENV["ORIGEN_LSF_RESOURCE"]
+
   # An example of how to specify a prefix to add to all generated patterns
   #config.pattern_prefix = "nvm"
 

data/config/shared_commands.rb

@@ -5,9 +5,12 @@ when 'generate'
   $use_fast_probe_depth = false
   @application_options << ["--fast", "Fast simulation, minimum probe depth"]
   $use_fast_probe_depth = ARGV.include?('--fast')
+
   @application_options << ["--sim_capture", "Update sim captures (ignored when not running a simulation)"]
   Origen.app!.update_sim_captures = ARGV.include?('--sim_capture')
 
+  @application_options << ["--flow NAME", "Simulate multiple patterns back-back within a single simulation with the given name", ->(options, name) { OrigenSim.flow = name }]
+
 when "sim:ci", "origen_sim:ci"
   require "#{Origen.root!}/lib/origen_sim/commands/ci"
   exit 0

data/config/version.rb

@@ -1,6 +1,6 @@
 module OrigenSim
   MAJOR = 0
-  MINOR = 9
+  MINOR = 10
   BUGFIX = 0
   DEV = nil
 

data/lib/origen_sim/commands/build.rb

@@ -3,7 +3,7 @@ require 'origen_sim'
 require_relative '../../../config/version'
 require 'origen_verilog'
 
-options = { source_dirs: [], testbench_name: 'origen' }
+options = { source_dirs: [], testbench_name: 'origen', defines: [] }
 
 # App options are options that the application can supply to extend this command
 app_options = @application_options || []
@@ -22,6 +22,9 @@ Usage: origen sim:build TOP_LEVEL_VERILOG_FILE [options]
   opts.on('-s', '--source_dir PATH', 'Directories to look for include files in (the directory containing the top-level is already considered)') do |path|
     options[:source_dirs] << path
   end
+  opts.on('--define MACRO', 'Specify a compiler define') do |macro|
+    options[:defines] << macro
+  end
   opts.on('-d', '--debugger', 'Enable the debugger') {  options[:debugger] = true }
   app_options.each do |app_option|
     opts.on(*app_option) {}
@@ -32,21 +35,30 @@ end
 
 opt_parser.parse! ARGV
 
+def _exit_fail_
+  if $_testing_build_return_dut_
+    return nil
+  else
+    exit 1
+  end
+end
+
 unless ARGV.size > 0
   puts 'You must supply a path to the top-level RTL file'
-  exit 1
+  _exit_fail_
 end
-rtl_top = ARGV.first
+files = ARGV.first
+rtl_top = files.split(/\s+/).last
 unless File.exist?(rtl_top)
   puts "File does not exist: #{rtl_top}"
-  exit 1
+  _exit_fail_
 end
 
-ast = OrigenVerilog.parse_file(rtl_top)
+ast = OrigenVerilog.parse_file(files, options)
 
 unless ast
   puts 'Sorry, but the given top-level RTL file failed to parse'
-  exit 1
+  _exit_fail_
 end
 
 candidates = ast.top_level_modules
@@ -54,7 +66,7 @@ candidates = ast.modules if candidates.empty?
 
 if candidates.size == 0
   puts "Sorry, couldn't find any Verilog module declarations in that file"
-  exit 1
+  _exit_fail_
 elsif candidates.size > 1
   if options[:top_level_name]
     mod = candidates.find { |c| c.name == options[:top_level_name] }
@@ -64,7 +76,7 @@ elsif candidates.size > 1
     candidates.each do |c|
       puts "  #{c.name}"
     end
-    exit 1
+    _exit_fail_
   end
 else
   mod = candidates.first
@@ -74,104 +86,110 @@ rtl_top_module = mod.name
 
 mod.to_top_level # Creates dut
 
-output_directory = options[:output] || Origen.config.output_directory
-
-Origen.app.runner.launch action:            :compile,
-                         files:             "#{Origen.root!}/templates/rtl_v/origen.v.erb",
-                         output:            output_directory,
-                         check_for_changes: false,
-                         quiet:             true,
-                         options:           { vendor: :cadence, top: dut.name, incl: options[:incl_files] }
-
-Origen.app.runner.launch action:            :compile,
-                         files:             "#{Origen.root!}/ext",
-                         output:            output_directory,
-                         check_for_changes: false,
-                         quiet:             true,
-                         options:           options
-
-dut.export(rtl_top_module, dir: "#{output_directory}", namespace: nil)
-
-puts
-puts
-puts 'Testbench and VPI extension created!'
-puts
-puts 'This file can be imported into an Origen top-level DUT model to define the pins:'
-puts
-puts "  #{output_directory}/#{rtl_top_module}.rb"
-puts
-puts 'See below for what to do now to create an Origen-enabled simulation object for your particular simulator:'
-puts
-puts '-----------------------------------------------------------'
-puts 'Cadence Incisive (irun)'
-puts '-----------------------------------------------------------'
-puts
-puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
-puts
-puts "  #{output_directory}/origen.v \\"
-puts "  #{output_directory}/*.c \\"
-puts '  -ccargs "-std=c99" \\'
-puts '  -top origen \\'
-puts '  -elaborate  \\'
-puts '  -snapshot origen \\'
-puts '  -access +rw \\'
-puts '  -timescale 1ns/1ns'
-puts
-puts 'Here is an example which may work for the file you just parsed (add additional -incdir options at the end if required):'
-puts
-puts "  #{ENV['ORIGEN_SIM_IRUN'] || 'irun'} #{rtl_top} #{output_directory}/origen.v #{output_directory}/*.c -ccargs \"-std=c99\" -top origen -elaborate -snapshot origen -access +rw -timescale 1ns/1ns -incdir #{Pathname.new(rtl_top).dirname}"
-puts
-puts 'Copy the following directory (produced by irun) to simulation/<target>/cadence/. within your Origen application:'
-puts
-puts '  INCA_libs'
-puts
-puts '-----------------------------------------------------------'
-puts 'Synopsys VCS'
-puts '-----------------------------------------------------------'
-puts
-puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
-puts
-puts "  #{output_directory}/origen.v \\"
-puts "  #{output_directory}/brdige.c \\"
-puts "  #{output_directory}/client.c \\"
-puts '  -CFLAGS "-std=c99" \\'
-puts '  +vpi \\'
-puts "  -use_vpiobj #{output_directory}/origen.c \\"
-puts '  +define+ORIGEN_VPD=1 \\'
-puts '  -debug_access+all \\'
-puts '  -PP \\'
-puts '  -timescale=1ns/1ns'
-puts
-puts 'Here is an example which may work for the file you just parsed (add additional -incdir options at the end if required):'
-puts
-puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} #{output_directory}/origen.v #{output_directory}/bridge.c #{output_directory}/client.c -CFLAGS \"-std=c99\" +vpi -use_vpiobj #{output_directory}/origen.c -timescale=1ns/1ns  +define+ORIGEN_VPD=1 +incdir+#{Pathname.new(rtl_top).dirname} -debug_access+all -PP"
-puts
-puts 'Copy the following files (produced by vcs) to simulation/<target>/synopsys/. within your Origen application:'
-puts
-puts '  simv'
-puts '  simv.daidir'
-puts
-puts '-----------------------------------------------------------'
-puts 'Icarus Verilog'
-puts '-----------------------------------------------------------'
-puts
-puts 'Compile the VPI extension using the following command:'
-puts
-puts "  cd #{output_directory} && #{ENV['ORIGEN_SIM_IVERILOG_VPI'] || 'iverilog-vpi'} *.c --name=origen && cd #{Pathname.pwd}"
-puts
-puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
-puts
-puts "  #{output_directory}/origen.v \\"
-puts '  -o origen.vvp \\'
-puts '  -DORIGEN_VCD'
-puts
-puts 'Here is an example which may work for the file you just parsed (add additional source dirs with more -I options at the end if required):'
-puts
-puts "  #{ENV['ORIGEN_SIM_IVERILOG'] || 'iverilog'} #{rtl_top} #{output_directory}/origen.v -o origen.vvp -DICARUS -I #{Pathname.new(rtl_top).dirname}"
-puts
-puts 'Copy the following files (produced by iverilog) to simulation/<target>/icarus/. within your Origen application:'
-puts
-puts "  #{output_directory}/origen.vpi"
-puts '  origen.vvp'
-puts
-puts
+if $_testing_build_return_dut_
+  dut
+
+else
+
+  output_directory = options[:output] || Origen.config.output_directory
+
+  Origen.app.runner.launch action:            :compile,
+                           files:             "#{Origen.root!}/templates/rtl_v/origen.v.erb",
+                           output:            output_directory,
+                           check_for_changes: false,
+                           quiet:             true,
+                           options:           { vendor: :cadence, top: dut.name, incl: options[:incl_files] }
+
+  Origen.app.runner.launch action:            :compile,
+                           files:             "#{Origen.root!}/ext",
+                           output:            output_directory,
+                           check_for_changes: false,
+                           quiet:             true,
+                           options:           options
+
+  dut.export(rtl_top_module, dir: "#{output_directory}", namespace: nil)
+
+  puts
+  puts
+  puts 'Testbench and VPI extension created!'
+  puts
+  puts 'This file can be imported into an Origen top-level DUT model to define the pins:'
+  puts
+  puts "  #{output_directory}/#{rtl_top_module}.rb"
+  puts
+  puts 'See below for what to do now to create an Origen-enabled simulation object for your particular simulator:'
+  puts
+  puts '-----------------------------------------------------------'
+  puts 'Cadence Incisive (irun)'
+  puts '-----------------------------------------------------------'
+  puts
+  puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
+  puts
+  puts "  #{output_directory}/origen.v \\"
+  puts "  #{output_directory}/*.c \\"
+  puts '  -ccargs "-std=c99" \\'
+  puts '  -top origen \\'
+  puts '  -elaborate  \\'
+  puts '  -snapshot origen \\'
+  puts '  -access +rw \\'
+  puts '  -timescale 1ns/1ns'
+  puts
+  puts 'Here is an example which may work for the file you just parsed (add additional -incdir options at the end if required):'
+  puts
+  puts "  #{ENV['ORIGEN_SIM_IRUN'] || 'irun'} #{rtl_top} #{output_directory}/origen.v #{output_directory}/*.c -ccargs \"-std=c99\" -top origen -elaborate -snapshot origen -access +rw -timescale 1ns/1ns -incdir #{Pathname.new(rtl_top).dirname}"
+  puts
+  puts 'Copy the following directory (produced by irun) to simulation/<target>/cadence/. within your Origen application:'
+  puts
+  puts '  INCA_libs'
+  puts
+  puts '-----------------------------------------------------------'
+  puts 'Synopsys VCS'
+  puts '-----------------------------------------------------------'
+  puts
+  puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
+  puts
+  puts "  #{output_directory}/origen.v \\"
+  puts "  #{output_directory}/brdige.c \\"
+  puts "  #{output_directory}/client.c \\"
+  puts '  -CFLAGS "-std=c99" \\'
+  puts '  +vpi \\'
+  puts "  -use_vpiobj #{output_directory}/origen.c \\"
+  puts '  +define+ORIGEN_VPD=1 \\'
+  puts '  -debug_access+all \\'
+  puts '  -PP \\'
+  puts '  -timescale=1ns/1ns'
+  puts
+  puts 'Here is an example which may work for the file you just parsed (add additional -incdir options at the end if required):'
+  puts
+  puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} #{output_directory}/origen.v #{output_directory}/bridge.c #{output_directory}/client.c -CFLAGS \"-std=c99\" +vpi -use_vpiobj #{output_directory}/origen.c -timescale=1ns/1ns  +define+ORIGEN_VPD=1 +incdir+#{Pathname.new(rtl_top).dirname} -debug_access+all -PP"
+  puts
+  puts 'Copy the following files (produced by vcs) to simulation/<target>/synopsys/. within your Origen application:'
+  puts
+  puts '  simv'
+  puts '  simv.daidir'
+  puts
+  puts '-----------------------------------------------------------'
+  puts 'Icarus Verilog'
+  puts '-----------------------------------------------------------'
+  puts
+  puts 'Compile the VPI extension using the following command:'
+  puts
+  puts "  cd #{output_directory} && #{ENV['ORIGEN_SIM_IVERILOG_VPI'] || 'iverilog-vpi'} *.c --name=origen && cd #{Pathname.pwd}"
+  puts
+  puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
+  puts
+  puts "  #{output_directory}/origen.v \\"
+  puts '  -o origen.vvp \\'
+  puts '  -DORIGEN_VCD'
+  puts
+  puts 'Here is an example which may work for the file you just parsed (add additional source dirs with more -I options at the end if required):'
+  puts
+  puts "  #{ENV['ORIGEN_SIM_IVERILOG'] || 'iverilog'} #{rtl_top} #{output_directory}/origen.v -o origen.vvp -DORIGEN_VCD -I #{Pathname.new(rtl_top).dirname}"
+  puts
+  puts 'Copy the following files (produced by iverilog) to simulation/<target>/icarus/. within your Origen application:'
+  puts
+  puts "  #{output_directory}/origen.vpi"
+  puts '  origen.vvp'
+  puts
+  puts
+end

data/lib/origen_sim/heartbeat.rb

@@ -0,0 +1,21 @@
+require 'thread'
+module OrigenSim
+  class Heartbeat < Thread
+    attr_reader :socket
+
+    def initialize(socket)
+      @socket = socket
+      @continue = true
+      super do
+        while @continue
+          socket.write("OK\n")
+          sleep 5
+        end
+      end
+    end
+
+    def stop
+      @continue = false
+    end
+  end
+end

data/lib/origen_sim/origen/application/runner.rb

@@ -0,0 +1,19 @@
+require 'origen/application/runner'
+module Origen
+  class Application
+    class Runner
+      # When multiple patterns are requested via the command line with the LSF option,
+      # Origen will split it into separate jobs for each pattern. However, if the --flow
+      # option is also supplied in that case, then the user will want all the patterns to
+      # execute as a single job on the LSF, this hack to Origen makes that happen.
+      alias_method :orig_expand_lists_and_directories, :expand_lists_and_directories
+      def expand_lists_and_directories(files, options = {})
+        if (options[:lsf] && OrigenSim.flow) && !Origen.running_remotely?
+          Array(Array(files).join(' '))
+        else
+          orig_expand_lists_and_directories(files, options)
+        end
+      end
+    end
+  end
+end

data/lib/origen_sim/simulation.rb

@@ -0,0 +1,157 @@
+require 'socket'
+require 'io/wait'
+require 'origen_sim/heartbeat'
+module OrigenSim
+  # Responsible for managing each individual simulation that is run in an
+  # Origen thread e.g. If multiple patterns are run in separate simulations, then one
+  # instance of this class will exist for each one.
+  #
+  # It is primarily responsible for all communications with the simulation and capturing
+  # log output and errors.
+  class Simulation
+    attr_reader :view_wave_command, :id
+
+    attr_accessor :logged_errors, :error_count, :failed_to_start, :completed_cleanly
+    attr_accessor :pid, :stderr_logged_errors
+    # Returns the communication socket used for sending commands to the Origen VPI running
+    # in the simulation process
+    attr_reader :socket
+
+    def initialize(id, view_wave_command)
+      @id = id
+      @view_wave_command = view_wave_command
+      @completed_cleanly = false
+      @failed_to_start = false
+      @logged_errors = false
+      @stderr_logged_errors = false
+      @error_count = 0
+      @socket_ids = {}
+
+      @server = UNIXServer.new(socket_id) # Socket used to send Origen -> Verilog commands
+      @server_stdout = UNIXServer.new(socket_id(:stdout))
+      @server_stderr = UNIXServer.new(socket_id(:stderr))
+      @server_heartbeat = UNIXServer.new(socket_id(:heartbeat))
+    end
+
+    def failed?(in_progress = false)
+      failed = stderr_logged_errors || logged_errors || failed_to_start || error_count > 0
+      if in_progress
+        failed
+      else
+        failed || !completed_cleanly
+      end
+    end
+
+    def log_results(in_progress = false)
+      if failed?(in_progress)
+        if failed_to_start
+          Origen.log.error 'The simulation failed to start!'
+        else
+          if in_progress
+            Origen.log.error "The simulation has #{error_count} error#{error_count > 1 ? 's' : ''}!" if error_count > 0
+          else
+            Origen.log.error "The simulation failed with #{error_count} errors!" if error_count > 0
+          end
+          Origen.log.error 'The simulation log reported errors!' if logged_errors
+          Origen.log.error 'The simulation stderr reported errors!' if stderr_logged_errors
+          Origen.log.error 'The simulation exited early!' unless completed_cleanly || in_progress
+        end
+      else
+        if in_progress
+          Origen.log.success 'The simulation is passing!'
+        else
+          Origen.log.success 'The simulation passed!'
+        end
+      end
+    end
+
+    # Provide a heartbeat to let the parallel Ruby process in charge of the simulator
+    # know that the master Origen process is still alive. If the Origen process crashes and leaves
+    # the simulator running, the child process will automatically reap it after a couple of missed
+    # heartbeats.
+    def start_heartbeat
+      @heartbeat = @server_heartbeat.accept
+      @pid = @heartbeat.gets.chomp.to_i
+      @heartbeat_thread = Heartbeat.new(@heartbeat)
+    end
+
+    def stop_heartbeat
+      @heartbeat_thread.stop
+    end
+
+    # Open the communication channels with the simulator
+    def open
+      start_heartbeat
+      @stdout = @server_stdout.accept
+      @stderr = @server_stderr.accept
+      @socket = @server.accept
+      @opened = true
+    end
+
+    # Close all communication channels with the simulator
+    def close
+      return unless @opened
+      stop_heartbeat
+      @heartbeat.close
+      @socket.close
+      @stderr.close
+      @stdout.close
+      File.unlink(socket_id(:heartbeat)) if File.exist?(socket_id(:heartbeat))
+      File.unlink(socket_id) if File.exist?(socket_id)
+      File.unlink(socket_id(:stderr)) if File.exist?(socket_id(:stderr))
+      File.unlink(socket_id(:stdout)) if File.exist?(socket_id(:stdout))
+    end
+
+    def read_sim_output
+      while @stdout.ready?
+        line = @stdout.gets.chomp
+        if OrigenSim.error_strings.any? { |s| line =~ /#{s}/ } &&
+           !OrigenSim.error_string_exceptions.any? { |s| line =~ /#{s}/ }
+          @logged_errors = true
+          Origen.log.error "(STDOUT): #{line}"
+        else
+          if OrigenSim.verbose? ||
+             OrigenSim.log_strings.any? { |s| line =~ /#{s}/ }
+            Origen.log.info line
+          else
+            Origen.log.debug line
+          end
+        end
+      end
+      while @stderr.ready?
+        line = @stderr.gets.chomp
+        if OrigenSim.fail_on_stderr && !line.empty? &&
+           !OrigenSim.stderr_string_exceptions.any? { |s| line =~ /#{s}/ }
+          # We're failing on stderr, so print its results and log as errors if its not an exception.
+          @stderr_logged_errors = true
+          Origen.log.error "(STDERR): #{line}"
+        elsif OrigenSim.verbose?
+          # We're not failing on stderr, or the string in stderr is an exception.
+          # Print the string as regular output if verbose is set, otherwise just ignore.
+          Origen.log.info line
+        end
+      end
+    end
+
+    # Returns true if the simulation is running
+    def running?
+      return false unless pid
+      begin
+        Process.getpgid(pid)
+        true
+      rescue Errno::ESRCH
+        false
+      end
+    end
+
+    def socket_id(type = nil)
+      @socket_ids[type] ||= "/tmp/#{socket_number}#{type}.sock"
+    end
+
+    private
+
+    def socket_number
+      @socket_number ||= (Process.pid.to_s + Time.now.to_f.to_s).sub('.', '')
+    end
+  end
+end

data/lib/origen_sim/simulator.rb

@@ -1,5 +1,4 @@
-require 'socket'
-require 'io/wait'
+require 'origen_sim/simulation'
 module OrigenSim
   # Responsible for managing and communicating with the simulator
   # process, a single instance of this class is instantiated as
@@ -9,13 +8,17 @@ module OrigenSim
 
     VENDORS = [:icarus, :cadence, :synopsys, :generic]
 
-    attr_reader :socket, :failed, :configuration, :stderr, :stdout, :heartbeat
+    attr_reader :configuration
     alias_method :config, :configuration
-    # Returns the PID of the simulator process
-    attr_reader :pid
+    # The instance of OrigenSim::Simulation for the current simulation
+    attr_reader :simulation
+    # Returns an array containing all instances of OrigenSim::Simulation that were created
+    # in the order that they were created
+    attr_reader :simulations
 
     def initialize
-      @socket_ids = {}
+      @simulations = []
+      @simulation_open = false
     end
 
     # When set to true the simulator will log all messages it receives, note that
@@ -140,7 +143,7 @@ module OrigenSim
       end
     end
 
-    def wave_dir
+    def wave_dir(subdir = nil)
       @wave_dir ||= begin
         d = "#{Origen.root}/waves/#{id}"
         FileUtils.mkdir_p(d)
@@ -198,17 +201,17 @@ module OrigenSim
         cmd += " -M#{compiled_dir} -morigen #{compiled_dir}/origen.vvp +socket+#{socket_id}"
 
       when :cadence
-        input_file = "#{tmp_dir}/#{id}.tcl"
+        input_file = "#{tmp_dir}/#{wave_file_basename}.tcl"
         if !File.exist?(input_file) || config_changed?
           Origen.app.runner.launch action:            :compile,
                                    files:             "#{Origen.root!}/templates/probe.tcl.erb",
                                    output:            tmp_dir,
                                    check_for_changes: false,
                                    quiet:             true,
-                                   options:           { dir: wave_dir, force: config[:force], setup: config[:setup], depth: :all },
-                                   output_file_name:  "#{id}.tcl"
+                                   options:           { dir: wave_dir, wave_file: wave_file_basename, force: config[:force], setup: config[:setup], depth: :all },
+                                   output_file_name:  "#{wave_file_basename}.tcl"
         end
-        input_file_fast = "#{tmp_dir}/#{id}_fast.tcl"
+        input_file_fast = "#{tmp_dir}/#{wave_file_basename}_fast.tcl"
         if !File.exist?(input_file_fast) || config_changed?
           fast_probe_depth = config[:fast_probe_depth] || 1
           Origen.app.runner.launch action:            :compile,
@@ -216,8 +219,8 @@ module OrigenSim
                                    output:            tmp_dir,
                                    check_for_changes: false,
                                    quiet:             true,
-                                   options:           { dir: wave_dir, force: config[:force], setup: config[:setup], depth: fast_probe_depth },
-                                   output_file_name:  "#{id}_fast.tcl"
+                                   options:           { dir: wave_dir, wave_file: wave_file_basename, force: config[:force], setup: config[:setup], depth: fast_probe_depth },
+                                   output_file_name:  "#{wave_file_basename}_fast.tcl"
         end
         save_config_signature
         wave_dir  # Ensure this exists since it won't be referenced above if the input file is already generated
@@ -228,7 +231,7 @@ module OrigenSim
         cmd += " -nclibdirpath #{compiled_dir}"
 
       when :synopsys
-        cmd = "#{compiled_dir}/simv +socket+#{socket_id} -vpd_file origen.vpd"
+        cmd = "#{compiled_dir}/simv +socket+#{socket_id} -vpd_file #{wave_file_basename}.vpd"
 
       when :generic
         # Generic tester requires that a generic_run_command option/block be provided.
@@ -269,6 +272,18 @@ module OrigenSim
       cmd
     end
 
+    def wave_file_basename
+      if OrigenSim.flow
+        OrigenSim.flow.to_s
+      else
+        if Origen.app.current_job
+          @last_wafe_file_basename = Pathname.new(Origen.app.current_job.output_file).basename('.*').to_s
+        else
+          @last_wafe_file_basename
+        end
+      end
+    end
+
     def view_wave_command
       cmd = nil
       case config[:vendor]
@@ -277,7 +292,7 @@ module OrigenSim
         cmd = "cd #{edir} && "
         cmd += configuration[:gtkwave] || 'gtkwave'
         dir = Pathname.new(wave_dir).relative_path_from(edir.expand_path)
-        cmd += " #{dir}/origen.vcd "
+        cmd += " #{dir}/#{wave_file_basename}/dump.vcd "
         f = Pathname.new(wave_config_file).relative_path_from(edir.expand_path)
         cmd += " --save #{f} &"
 
@@ -286,7 +301,7 @@ module OrigenSim
         cmd = "cd #{edir} && "
         cmd += configuration[:simvision] || 'simvision'
         dir = Pathname.new(wave_dir).relative_path_from(edir.expand_path)
-        cmd += " #{dir}/#{id}.dsn #{dir}/#{id}.trn"
+        cmd += " #{dir}/#{wave_file_basename}/#{wave_file_basename}.dsn #{dir}/#{wave_file_basename}/#{wave_file_basename}.trn"
         f = Pathname.new(wave_config_file).relative_path_from(edir.expand_path)
         cmd += " -input #{f} &"
 
@@ -295,7 +310,7 @@ module OrigenSim
         cmd = "cd #{edir} && "
         cmd += configuration[:dve] || 'dve'
         dir = Pathname.new(wave_dir).relative_path_from(edir.expand_path)
-        cmd += " -vpd #{dir}/origen.vpd"
+        cmd += " -vpd #{dir}/#{wave_file_basename}.vpd"
         f = Pathname.new(wave_config_file).relative_path_from(edir.expand_path)
         cmd += " -session #{f}"
         cmd += ' &'
@@ -320,31 +335,29 @@ module OrigenSim
 
     def run_dir
       case config[:vendor]
-      when :icarus, :synopsys
+      when :icarus
+        d = File.join(wave_dir, wave_file_basename)
+        FileUtils.mkdir_p(d)
+        d
+      when :synopsys
         wave_dir
       else
         tmp_dir
       end
     end
 
+    def simulation_open?
+      @simulation_open
+    end
+
     # Starts up the simulator process
     def start
+      @simulation_open = true
+      @simulation = Simulation.new(wave_file_basename, view_wave_command)
+      simulations << @simulation
+
       fetch_simulation_objects
 
-      # Socket used for Origen -> Verilog commands
-      server = UNIXServer.new(socket_id)
-      # Socket used to capture stdout from the simulator
-      stdout_socket_id = socket_id(:stdout)
-      # Socket used to capture stderr from the simulator
-      stderr_socket_id = socket_id(:stderr)
-      # Socket used to provide a heartbeat to let the Ruby process in charge of the simulator
-      # know that the mast Origen process is still alive. If the Origen process crashes and leaves
-      # the simulator running, the child process will automatically reap it after a couple of missed
-      # heartbeats
-      heartbeat_socket_id = socket_id(:heartbeat)
-      server_stdout = UNIXServer.new(stdout_socket_id)
-      server_stderr = UNIXServer.new(stderr_socket_id)
-      server_heartbeat = UNIXServer.new(heartbeat_socket_id)
       cmd = run_cmd + ' & echo \$!'
 
       launch_simulator = %(
@@ -355,9 +368,19 @@ module OrigenSim
 
         pid = nil
 
-        stdout_socket = UNIXSocket.new('#{stdout_socket_id}')
-        stderr_socket = UNIXSocket.new('#{stderr_socket_id}')
-        heartbeat = UNIXSocket.new('#{heartbeat_socket_id}')
+        def kill_simulation(pid)
+          begin
+            # If the process already finished, then we will see an Errno exception.
+            # It does not harm anything, but looks ugly, so catch it here and ignore.
+            Process.kill('KILL', pid)
+          rescue Errno::ESRCH => e
+          end
+          exit!
+        end
+
+        stdout_socket = UNIXSocket.new('#{simulation.socket_id(:stdout)}')
+        stderr_socket = UNIXSocket.new('#{simulation.socket_id(:stderr)}')
+        heartbeat = UNIXSocket.new('#{simulation.socket_id(:heartbeat)}')
 
         begin
 
@@ -372,6 +395,14 @@ module OrigenSim
                 missed_heartbeats = 0
                 loop do
                   sleep 5
+
+                  # If the socket read hangs, count that as a reason to shutdown
+                  socket_read = false
+                  Thread.new do
+                    sleep 1
+                    kill_simulation(pid) unless socket_read
+                  end
+
                   if heartbeat.ready?
                     while heartbeat.ready? do
                       heartbeat.gets
@@ -380,9 +411,9 @@ module OrigenSim
                   else
                     missed_heartbeats += 1
                   end
+                  socket_read = true
                   if missed_heartbeats > 1
-                    Process.kill('KILL', pid)
-                    exit!(1)
+                    kill_simulation(pid)
                   end
                 end
               end
@@ -404,14 +435,7 @@ module OrigenSim
 
         ensure
           # Make sure this process never finishes and leaves the simulator running
-          begin
-            # If the process already finished, then we will see an Errno exception.
-            # It does not harm anything, but looks ugly, so catch it here and ignore.
-            Process.kill('KILL', pid) if pid
-            0
-          rescue Errno::ESRCH => e
-            0
-          end
+          kill_simulation(pid) if pid
         end
       )
 
@@ -419,34 +443,19 @@ module OrigenSim
       Process.detach(simulator_parent_process)
 
       timeout_connection(config[:startup_timeout] || 60) do
-        @heartbeat = server_heartbeat.accept
-        @pid = heartbeat.gets.chomp.to_i
-
-        # Send a heartbeat to the child process running the simulator every 5 seconds
-        Thread.new do
-          loop do
-            heartbeat.write("OK\n")
-            sleep 5
-          end
-        end
+        simulation.open # This will block until the simulation process responds
 
-        @stdout = server_stdout.accept
-        @stderr = server_stderr.accept
-        @socket = server.accept
-        @connection_established = true
+        @connection_established = true # Cancels timeout_connection
         if @connection_timed_out
-          @failed_to_start = true
-          Origen.log.error 'Simulator failed to respond'
-          @failed = true
-          exit
+          simulation.failed_to_start = true
+          exit  # Assume it is not worth trying another pattern in this case, some kind of environment/config issue
         end
       end
       data = get
       unless data.strip == 'READY!'
-        @failed_to_start = true
-        fail "The simulator didn't start properly!"
+        simulation.failed_to_start = true
+        exit  # Assume it is not worth trying another pattern in this case, some kind of environment/config issue
       end
-      @enabled = true
       # Tick the simulation on, this seems to be required since any VPI puts operations before
       # the simulation has started are not applied.
       # Note that this is not setting a tester timeset, so the application will still have to
@@ -456,64 +465,64 @@ module OrigenSim
       Origen.listeners_for(:simulation_startup).each(&:simulation_startup)
     end
 
-    # Returns true if the simulator process is running
-    def running?
-      return false unless pid
-      begin
-        Process.getpgid(pid)
-        true
-      rescue Errno::ESRCH
-        false
-      end
-    end
-
     # Send the given message string to the simulator
     def put(msg)
-      socket.write(msg + "\n") if socket
+      simulation.socket.write(msg + "\n")
     end
 
     # Get a message from the simulator, will block until one
     # is received
     def get
-      socket.readline
+      simulation.socket.readline
     end
 
-    # This will be called at the end of every pattern, make
-    # sure the simulator is not running behind before potentially
-    # moving onto another pattern
-    def pattern_generated(path)
-      sync_up if simulation_tester?
-      @simulation_completed_cleanly = true
+    # At the start of a test program flow generation/simulation
+    def on_flow_start(options)
+      if simulation_tester? && options[:top_level]
+        OrigenSim.flow = Origen.interface.flow.name
+        start
+        @pattern_count = 0
+      end
+    end
+
+    # At the end of a test program flow generation/simulation
+    def on_flow_end(options)
+      if simulation_tester? && options[:top_level]
+        stop
+      end
     end
 
     # Called before every pattern is generated, but we only use it the
     # first time it is called to kick off the simulator process if the
     # current tester is an OrigenSim::Tester
     def before_pattern(name)
-      @simulation_completed_cleanly = false
       if simulation_tester?
-        unless @enabled
-          # When running pattern back-to-back, only want to launch the simulator the
-          # first time
-          unless socket
-            start
-          end
+        if OrigenSim.flow || !simulation
+          # When running patterns back-to-back, only want to launch the simulator the first time
+          start unless simulation
+        else
+          stop
+          start
         end
         # Set the current pattern name in the simulation
         put("a^#{name.sub(/\..*/, '')}")
         @pattern_count ||= 0
-        if @pattern_count > 0
-          c = error_count
-          if c > 0
-            Origen.log.error "The simulation currently has #{c} error(s)!"
-          else
-            Origen.log.success 'There are no simulation errors yet!'
-          end
+        # If running a flow, give the user some feedback about pass/fail status after
+        # each individual pattern has completed
+        if @pattern_count > 0 && OrigenSim.flow
+          simulation.log_results(true)
         end
         @pattern_count += 1
       end
     end
 
+    # This will be called at the end of every pattern, make
+    # sure the simulator is not running behind before potentially
+    # moving onto another pattern
+    def pattern_generated(path)
+      sync_up if simulation_tester?
+    end
+
     def write_comment(comment)
       # Not sure what the limiting factor here is, the comment memory in the test bench should
       # be able to handle 1024 / 8 length strings, but any bigger than this hangs the simulation
@@ -590,7 +599,7 @@ module OrigenSim
 
     def cycle(number_of_cycles)
       put("3^#{number_of_cycles}")
-      read_sim_output
+      simulation.read_sim_output
     end
 
     # Blocks the Origen process until the simulator indicates that it has
@@ -601,37 +610,12 @@ module OrigenSim
       unless data.strip == 'OK!'
         fail 'Origen and the simulator are out of sync!'
       end
-      read_sim_output
+      simulation.read_sim_output
     end
 
-    def read_sim_output
-      while stdout.ready?
-        line = stdout.gets.chomp
-        if OrigenSim.error_strings.any? { |s| line =~ /#{s}/ } &&
-           !OrigenSim.error_string_exceptions.any? { |s| line =~ /#{s}/ }
-          @simulator_logged_errors = true
-          Origen.log.error "(STDOUT): #{line}"
-        else
-          if OrigenSim.verbose? ||
-             OrigenSim.log_strings.any? { |s| line =~ /#{s}/ }
-            Origen.log.info line
-          else
-            Origen.log.debug line
-          end
-        end
-      end
-      while stderr.ready?
-        line = stderr.gets.chomp
-        if OrigenSim.fail_on_stderr && !OrigenSim.stderr_string_exceptions.any? { |s| line =~ /#{s}/ }
-          # We're failing on stderr, so print its results and log as errors if its not an exception.
-          @stderr_logged_errors = true
-          Origen.log.error "(STDERR): #{line}"
-        elsif OrigenSim.verbose?
-          # We're not failing on stderr, or the string in stderr is an exception.
-          # Print the string as regular output if verbose is set, otherwise just ignore.
-          Origen.log.info line
-        end
-      end
+    def error(message)
+      simulation.logged_errors = true
+      Origen.log.error message
     end
 
     # Returns the current simulation error count
@@ -732,62 +716,71 @@ module OrigenSim
 
     # Stop the simulator
     def stop
+      @simulation_open = false
+      simulation.read_sim_output
+      simulation.error_count = error_count
       Origen.listeners_for(:simulation_shutdown).each(&:simulation_shutdown)
       ended = Time.now
       end_simulation
       # Give the simulator time to shut down
-      sleep 0.1 while running?
-      socket.close if socket
-      stderr.close if stderr
-      stdout.close if stdout
-      heartbeat.close if heartbeat
-      File.unlink(socket_id) if File.exist?(socket_id)
-      File.unlink(socket_id(:stderr)) if File.exist?(socket_id(:stderr))
-      File.unlink(socket_id(:stdout)) if File.exist?(socket_id(:stdout))
-      File.unlink(socket_id(:heartbeat)) if File.exist?(socket_id(:heartbeat))
+      sleep 0.1 while simulation.running?
+      simulation.close
+      simulation.completed_cleanly = true
+      simulation.log_results unless Origen.current_command == 'interactive'
     end
 
     def on_origen_shutdown
-      if @enabled
+      unless simulations.empty?
+        failed = false
+        # Stop the current simulation, this is done with the rescue wrapper so that the rest
+        # of the shutdown continues if we got in here via a CTRL-C, in which case the simulator
+        # is probably already dead
+        begin
+          stop if simulation_open?
+        rescue
+          simulation.completed_cleanly = false
+        end
         unless @interactive_mode
-          Origen.log.debug 'Shutting down simulator...'
-          unless @failed_to_start
-            c = error_count
-            if c > 0 || @simulator_logged_errors || @stderr_logged_errors
-              @failed = true
-              Origen.log.error "The simulation failed with #{c} errors!" if c > 0
-              Origen.log.error 'The simulation log reported errors!' if @simulator_logged_errors
-              Origen.log.error 'The simulation stderr reported errors!' if @stderr_logged_errors
-            elsif !@simulation_completed_cleanly
-              @failed = true
-              Origen.log.error 'The simulation exited early!'
+          if simulations.size == 1
+            failed = simulation.failed?
+          else
+            failed_simulation_count = simulations.count(&:failed?)
+            if failed_simulation_count > 0
+              Origen.log.error "#{failed_simulation_count} of #{simulations.size} simulations failed!"
+              failed = true
             end
           end
-        end
-        stop
-        unless @interactive_mode
           if failed
             Origen.app.stats.report_fail
           else
             Origen.app.stats.report_pass
           end
         end
-        if view_wave_command
-          puts
+        puts
+        if simulations.size == 1
           puts 'To view the simulation run the following command:'
           puts
-          puts "  #{view_wave_command}"
+          puts "  #{simulation.view_wave_command}"
+        else
+          puts 'To view the simulations run the following commands:'
           puts
+          simulations.each do |simulation|
+            if simulation.failed?
+              puts "  #{simulation.view_wave_command}".red
+            else
+              puts "  #{simulation.view_wave_command}"
+            end
+          end
+        end
+        puts
+        unless @interactive_mode
+          failed ? exit(1) : exit(0)
         end
       end
     end
 
-    def socket_id(type = nil)
-      @socket_ids[type] ||= "/tmp/#{socket_number}#{type}.sock"
-    end
-
-    def socket_number
-      @socket_number ||= (Process.pid.to_s + Time.now.to_f.to_s).sub('.', '')
+    def socket_id
+      simulation.socket_id
     end
 
     def simulation_tester?
@@ -796,6 +789,7 @@ module OrigenSim
 
     def timeout_connection(wait_in_s)
       @connection_timed_out = false
+      @connection_established = false
       t = Thread.new do
         sleep wait_in_s
         # If the Verilog process has not established a connection yet, then make one to

data/lib/origen_sim.rb

@@ -4,6 +4,7 @@ require 'origen_testers'
 require 'origen_sim/origen_testers/api'
 require 'origen_sim/origen/pins/pin'
 require 'origen_sim/origen/top_level'
+require 'origen_sim/origen/application/runner'
 module OrigenSim
   # THIS FILE SHOULD ONLY BE USED TO LOAD RUNTIME DEPENDENCIES
   # If this plugin has any development dependencies (e.g. dummy DUT or other models that are only used
@@ -46,7 +47,15 @@ module OrigenSim
   end
 
   def self.verbose?
-    !!(@verbose || Origen.debugger_enabled?)
+    !!(@verbose || Origen.debugger_enabled? || Origen.running_remotely?)
+  end
+
+  def self.flow=(val)
+    @flow = val
+  end
+
+  def self.flow
+    @flow
   end
 
   def self.error_strings
@@ -100,5 +109,9 @@ module OrigenSim
   def self.fail_on_stderr
     defined?(@fail_on_stderr) ? @fail_on_stderr : true
   end
+
+  def self.error(message)
+    simulator.error(message)
+  end
 end
 OrigenSim.__instantiate_simulator__

data/pattern/test.rb

@@ -45,12 +45,12 @@ Pattern.create do
 
   if tester.sim?
     sim = tester.simulator
-    capture_value = sim.peek("origen.pins.tdo.memory").to_i
+    capture_value = sim.peek("origen.pins.tdo.memory").to_i[31..0]
     unless capture_value == 0x11662244 # 0x2244_6688 reversed
       if capture_value
-        fail "Captured #{capture_value.to_hex} instead of 0x11662244!"
+        OrigenSim.error "Captured #{capture_value.to_hex} instead of 0x11662244!"
       else
-        fail "Nothing captured instead of 0x11662244!"
+        OrigenSim.error "Nothing captured instead of 0x11662244!"
       end
     end
 
@@ -58,7 +58,7 @@ Pattern.create do
     dut.cmd.write(0) # Make Origen forget the actual value
     dut.cmd.sync
     unless dut.cmd.data == 0x2244_6688
-      fail "CMD register did not sync from simulation"
+      OrigenSim.error "CMD register did not sync from simulation"
     end
 
     ss "Test sync of a register via a parallel interface"
@@ -68,7 +68,7 @@ Pattern.create do
     dut.pins(:dout).dont_care
     dut.parallel_read.sync
     unless dut.parallel_read.data == 0x7707_7077
-      fail "PARALLEL_READ register did not sync from simulation"
+      OrigenSim.error "PARALLEL_READ register did not sync from simulation"
     end
   end
 

data/pattern/test2.rb

@@ -0,0 +1 @@
+pattern/test.rb

data/program/p1.rb

@@ -2,9 +2,9 @@ Flow.create do
 
   test :test
 
-  test :test
+  test :test2
 
   test :test
 
-  test :test
+  test :test2
 end

data/program/p2.rb

@@ -0,0 +1 @@
+program/p1.rb

data/templates/probe.tcl.erb

@@ -1,4 +1,4 @@
-database -open waves -into <%= options[:dir] %> -default -event
+database -open waves -into <%= options[:dir] %>/<%= options[:wave_file] %> -default -event
 probe -create -shm origen -depth <%= options[:depth] %> -database waves
 #probe -create -assertions -transaction origen -depth all -database waves
 

data/templates/rtl_v/origen.v.erb

@@ -157,7 +157,7 @@ module origen;
     //$display("********************************");
     //$display("Creating origen.vcd...");
     //$display("********************************");
-    $dumpfile("origen.vcd");
+    //$dumpfile("origen.vcd");
     $dumpvars(0,origen);
   end
 `endif

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_sim
 version: !ruby/object:Gem::Version
-  version: 0.9.0
+  version: 0.10.0
 platform: ruby
 authors:
 - Stephen McGinty
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2018-06-01 00:00:00.000000000 Z
+date: 2018-06-18 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen
@@ -44,14 +44,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.3.1
+        version: '0.4'
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.3.1
+        version: '0.4'
 description: 
 email:
 - stephen.f.mcginty@gmail.com
@@ -81,15 +81,20 @@ files:
 - lib/origen_sim/commands/pack.rb
 - lib/origen_sim/flow.rb
 - lib/origen_sim/generator.rb
+- lib/origen_sim/heartbeat.rb
+- lib/origen_sim/origen/application/runner.rb
 - lib/origen_sim/origen/pins/pin.rb
 - lib/origen_sim/origen/top_level.rb
 - lib/origen_sim/origen_testers/api.rb
+- lib/origen_sim/simulation.rb
 - lib/origen_sim/simulator.rb
 - lib/origen_sim/tester.rb
 - lib/origen_sim_dev/dut.rb
 - lib/tasks/origen_sim.rake
 - pattern/test.rb
+- pattern/test2.rb
 - program/p1.rb
+- program/p2.rb
 - templates/empty.gtkw
 - templates/empty.svcf
 - templates/empty.tcl
@@ -118,7 +123,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
       version: 1.8.11
 requirements: []
 rubyforge_project: 
-rubygems_version: 2.6.7
+rubygems_version: 2.6.14.1
 signing_key: 
 specification_version: 4
 summary: Plugin that provides a testbench environment to simulate Origen test patterns