origen_sim 0.7.0 → 0.8.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA1:
-  metadata.gz: f60a5e099e0edaf4c0c769034d2eb9dd2cef4660
-  data.tar.gz: b89dd7aa4de98bd80bd7b130158ef0c5a2f0acc1
+  metadata.gz: 07feeaf38e2cacb8a570887c9bfc2acd38b26956
+  data.tar.gz: 693b70230e195a5b0fd49c586ec16f5116fe7d0d
 SHA512:
-  metadata.gz: 17cb26ed22d5098edcdc59a2e5ee23e35a8b36b4b9b2b6959990bd151880da02a925719286a46b9d9dc20711a1640dbab809fbb01de5139ae7f5845c97a8bc52
-  data.tar.gz: c30220fbebb6a393bdc5ff05e80d51401aa40b7ac031f69c56fa14c7ee673b2111851682e46967b767afaa72ae0299c517c32fd3ff1616ab5fd5a32ec5195a70
+  metadata.gz: 295d5c1df56f7341fa5e60b35b902169d92d21c482a2bee4452827d84e847697975e218aa4eb86e07d10d79e0939bee3d4e2a58ede7a347c8599fb26733ac7b9
+  data.tar.gz: e51c858045564989fa53ce7bc281d70afc887e5312f81908e44463a303c93d0c65d5a61cb15095a12892e7d3ff4dc3002bb5565f0735a3c37284298889500f7e

data/config/version.rb

@@ -1,6 +1,6 @@
 module OrigenSim
   MAJOR = 0
-  MINOR = 7
+  MINOR = 8
   BUGFIX = 0
   DEV = nil
 

data/ext/bridge.c

@@ -30,7 +30,7 @@ typedef struct Pin {
 } Pin;
 
 typedef struct Event {
-  int time;
+  uint64_t time;
   char data;
 } Event;
 
@@ -62,7 +62,7 @@ static void bridge_capture_pin(char*);
 static void bridge_stop_capture_pin(char*);
 static void bridge_dont_care_pin(char*);
 static void bridge_register_wave_events(void);
-static void bridge_register_wave_event(int, int, int, int);
+static void bridge_register_wave_event(int, int, int, uint64_t);
 static void bridge_enable_drive_wave(Pin*);
 static void bridge_disable_drive_wave(Pin*);
 static void bridge_enable_compare_wave(Pin*);
@@ -160,7 +160,7 @@ static void bridge_register_wave_events() {
       int x = 0;
 
       while (drive_waves[i].events[x].data != 'T' && x < MAX_WAVE_EVENTS) {
-        int time;
+        uint64_t time;
 
         time = drive_waves[i].events[x].time;
 
@@ -180,7 +180,7 @@ static void bridge_register_wave_events() {
       int x = 0;
 
       while (compare_waves[i].events[x].data != 'T' && x < MAX_WAVE_EVENTS) {
-        int time;
+        uint64_t time;
 
         time = compare_waves[i].events[x].time;
 
@@ -260,9 +260,9 @@ static void bridge_clear_waves_and_pins() {
 }
 
 
-static void bridge_set_period(char * p_in_ns) {
-  int p = (int) strtol(p_in_ns, NULL, 10);
-  period_in_ps = p * 1000;
+static void bridge_set_period(char * p_in_ps_str) {
+  uint64_t p = (uint64_t) strtol(p_in_ps_str, NULL, 10);
+  period_in_ps = p;
   bridge_clear_waves_and_pins();
 }
 
@@ -472,8 +472,7 @@ PLI_INT32 bridge_apply_wave_event_cb(p_cb_data data) {
 
 
 /// Registers a callback to apply the given wave during this cycle
-static void bridge_register_wave_event(int wave_ix, int event_ix, int compare, int delay_in_ns) {
-  uint64_t delay_in_ps = delay_in_ns * 1000;
+static void bridge_register_wave_event(int wave_ix, int event_ix, int compare, uint64_t delay_in_ps) {
   s_cb_data call;
   s_vpi_time time;
 
@@ -565,7 +564,7 @@ PLI_INT32 bridge_wait_for_msg(p_cb_data data) {
         bridge_define_pin(arg1, arg2, arg3, arg4);
         break;
       // Set Period
-      //   1^100
+      //   1^100000
       case '1' :
         arg1 = strtok(NULL, "^");
         bridge_set_period(arg1);
@@ -757,7 +756,7 @@ static void end_simulation() {
   v.value.str = "1";
   vpi_put_value(handle, &v, NULL, vpiNoDelay);
   // Corner case during testing, the timeset may not have been set yet
-  bridge_set_period("1");
+  bridge_set_period("1000");
   // Do a cycle so that the simulation sees the edge on origen.finish
   bridge_cycle();
 }

data/lib/origen_sim/commands/build.rb

@@ -88,7 +88,7 @@ Origen.app.runner.launch action:            :compile,
                          check_for_changes: false,
                          quiet:             true
 
-dut.export(rtl_top_module, file_path: "#{output_directory}")
+dut.export(rtl_top_module, dir: "#{output_directory}", namespace: nil)
 
 puts
 puts

data/lib/origen_sim/simulator.rb

@@ -367,12 +367,14 @@ module OrigenSim
     # moving onto another pattern
     def pattern_generated(path)
       sync_up if simulation_tester?
+      @simulation_completed_cleanly = true
     end
 
     # Called before every pattern is generated, but we only use it the
     # first time it is called to kick off the simulator process if the
     # current tester is an OrigenSim::Tester
     def before_pattern(name)
+      @simulation_completed_cleanly = false
       if simulation_tester?
         unless @enabled
           # When running pattern back-to-back, only want to launch the simulator the
@@ -438,14 +440,14 @@ module OrigenSim
 
     def wave_to_str(wave)
       wave.evaluated_events.map do |time, data|
-        time = time * (config[:time_factor] || 1)
+        time = time * time_conversion_factor * (config[:time_factor] || 1)
         if data == :x
           data = 'X'
         elsif data == :data
           data = wave.drive? ? 'D' : 'C'
         end
         if data == 'C'
-          "#{time}_#{data}_#{time + (config[:time_factor] || 1)}_X"
+          "#{time}_#{data}_#{time + (time_conversion_factor * (config[:time_factor] || 1))}_X"
         else
           "#{time}_#{data}"
         end
@@ -466,8 +468,8 @@ module OrigenSim
     end
 
     def set_period(period_in_ns)
-      period_in_ns = period_in_ns * (config[:time_factor] || 1)
-      put("1^#{period_in_ns}")
+      period_in_ps = period_in_ns * time_conversion_factor * (config[:time_factor] || 1)
+      put("1^#{period_in_ps}")
     end
 
     def cycle(number_of_cycles)
@@ -536,7 +538,7 @@ module OrigenSim
       # deal with it here to ensure cross simulator compatibility.
 
       # http://rubular.com/r/eTVGzrYmXQ
-      if net =~ /(.*)\[(\d+):?(\.\.)?(\d*)\]$/
+      if !config[:vendor] == :synopsys && net =~ /(.*)\[(\d+):?(\.\.)?(\d*)\]$/
         path = Regexp.last_match(1)
         msb = Regexp.last_match(2).to_i
         lsb = Regexp.last_match(4)
@@ -606,6 +608,9 @@ module OrigenSim
             if c > 0
               @failed = true
               Origen.log.error "The simulation failed with #{c} errors!"
+            elsif !@simulation_completed_cleanly
+              @failed = true
+              Origen.log.error 'The simulation exited early!'
             end
           end
         end
@@ -688,6 +693,11 @@ module OrigenSim
 
     private
 
+    # Pre 0.8.0 the simulator represented the time in ns instead of ps
+    def time_conversion_factor
+      @time_conversion_factor ||= dut_version < '0.8.0' ? 1 : 1000
+    end
+
     def clean(net)
       if net =~ /^dut\./
         "origen.#{net}"

data/lib/origen_sim/tester.rb

@@ -23,7 +23,13 @@ module OrigenSim
         @sync_cycles = 0
         yield
       end
-      @sync_pins.map { |pin| simulator.peek("origen.pins.#{pin.id}.sync_memory[#{@sync_cycles - 1}:0]") }
+      @sync_pins.map do |pin|
+        if @sync_cycles.size == 1
+          simulator.peek("origen.pins.#{pin.id}.sync_memory[0]")
+        else
+          simulator.peek("origen.pins.#{pin.id}.sync_memory[#{@sync_cycles - 1}:0]")
+        end
+      end
     end
 
     # Start the simulator
@@ -100,8 +106,8 @@ module OrigenSim
         end
       end
       if simulator.sync_active?
+        @sync_cycles += 1
         pins.each do |pin|
-          @sync_cycles += 1
           @sync_pins << pin unless @sync_pins.include?(pin)
         end
       end

data/lib/origen_sim_dev/dut.rb

@@ -59,6 +59,17 @@ module OrigenSimDev
         reg.bits 5..2, :p3
         reg.bits 9..6, :p4
       end
+
+      # Reg for testing parallel read/sync when this one is read the data will
+      # be read out via dout rather than JTAG
+      add_reg :parallel_read, 0x18 do |reg|
+        reg.bits 30..28, :b1
+        reg.bits 26..24, :b2
+        reg.bits 18..16, :b3
+        reg.bits 14..12, :b4
+        reg.bits 6..4, :b5
+        reg.bits 2..0, :b6
+      end
     end
 
     def interactive_startup
@@ -90,14 +101,27 @@ module OrigenSimDev
     end
 
     def read_register(reg, options = {})
-      jtag.write_ir(0x8, size: 4)
-      dr.rg_enable.write(1)
-      dr.rg_read.write(1)
-      dr.rg_addr.write(reg.address)
-      jtag.write_dr(dr)
-      dr.rg_enable.write(0)
-      dr.rg_data.copy_all(reg)
-      jtag.read_dr(dr)
+      # Special read for this register to test sync'ing over a parallel
+      if reg.id == :parallel_read
+        pins = []
+        reg.shift_out_with_index do |bit, i|
+          if bit.is_to_be_stored?
+            pins << dut.pins(:dout)[i]
+          end
+        end
+        tester.store_next_cycle(*pins.reverse)
+        1.cycle
+        dut.pins(:dout).dont_care
+      else
+        jtag.write_ir(0x8, size: 4)
+        dr.rg_enable.write(1)
+        dr.rg_read.write(1)
+        dr.rg_addr.write(reg.address)
+        jtag.write_dr(dr)
+        dr.rg_enable.write(0)
+        dr.rg_data.copy_all(reg)
+        jtag.read_dr(dr)
+      end
     end
   end
 end

data/pattern/test.rb

@@ -60,6 +60,16 @@ Pattern.create do
     unless dut.cmd.data == 0x2244_6688
       fail "CMD register did not sync from simulation"
     end
+
+    ss "Test sync of a register via a parallel interface"
+    dut.parallel_read.write(0)
+    dut.data_out.write!(0x7707_7077)
+    dut.pins(:dout).assert!(0x7707_7077)
+    dut.pins(:dout).dont_care
+    dut.parallel_read.sync
+    unless dut.parallel_read.data == 0x7707_7077
+      fail "PARALLEL_READ register did not sync from simulation"
+    end
   end
 
   ss "Do some operations with the counter, just for fun"

data/templates/rtl_v/origen.v.erb

@@ -167,13 +167,11 @@ module origen;
   begin
     $vcdplusfile("origen.vpd");
     $vcdpluson;
+    $vcdplusmemon;
   end
 `endif
     
   always @(posedge finish) begin
-`ifdef ORIGEN_VPD 
-    $vcdplusoff;
-`endif
     //$display("********************************");
     //$display("Finishing simulation...");
     //$display("********************************");

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_sim
 version: !ruby/object:Gem::Version
-  version: 0.7.0
+  version: 0.8.0
 platform: ruby
 authors:
 - Stephen McGinty
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2018-02-06 00:00:00.000000000 Z
+date: 2018-04-06 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: '0.29'
+        version: '0.32'
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: '0.29'
+        version: '0.32'
 - !ruby/object:Gem::Dependency
   name: origen_testers
   requirement: !ruby/object:Gem::Requirement