origen_sim 0.5.0

data/lib/origen_sim.rb

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+require 'origen'
+require_relative '../config/application.rb'
+require 'origen_testers'
+require 'origen_sim/origen_testers/api'
+require 'origen_sim/origen/pins/pin'
+require 'origen_sim/origen/top_level'
+module OrigenSim
+  # THIS FILE SHOULD ONLY BE USED TO LOAD RUNTIME DEPENDENCIES
+  # If this plugin has any development dependencies (e.g. dummy DUT or other models that are only used
+  # for testing), then these should be loaded from config/boot.rb
+
+  # Example of how to explicitly require a file
+  # require "origen_sim/my_file"
+
+  autoload :Simulator, 'origen_sim/simulator'
+  autoload :Tester, 'origen_sim/tester'
+  autoload :Generator, 'origen_sim/generator'
+
+  def self.__instantiate_simulator__
+    @simulator ||= Simulator.new
+  end
+
+  def self.simulator
+    @simulator
+  end
+end
+OrigenSim.__instantiate_simulator__

data/lib/origen_sim_dev/dut.rb

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+module OrigenSimDev
+  class DUT
+    include Origen::TopLevel
+    include OrigenJTAG
+
+    JTAG_CONFIG = {
+      tclk_format: :rl
+    }
+
+    def initialize(options = {})
+      add_pin :tck, reset: :drive_lo
+      add_pin :tdi, reset: :drive_lo
+      add_pin :tdo
+      add_pin :tms, reset: :drive_lo
+      add_pin :rstn, reset: :drive_lo
+      add_pin :trstn, reset: :drive_lo
+      add_pin_alias :tclk, :tck
+      add_pin :dout, size: 32
+      add_pin :din_port, size: 32, rtl_name: 'din', reset: :drive_lo
+      add_pin :p1, tie_off: 0
+      add_pin :p2, tie_off: 1
+      add_pin :p3, size: 4, tie_off: 0
+      add_pin :p4, size: 4, tie_off: 1
+      add_pin :v1, rtl_name: 'nc'
+      add_pin :v2, rtl_name: :nc
+
+      timeset :func do |t|
+        # Generate a clock pulse on TCK
+        t.wave :tck do |w|
+          w.drive 0, at: 0
+          w.drive :data, at: 'period / 2'
+        end
+      end
+
+      add_reg :dr, 0x0, size: 66 do |reg|
+        reg.bit 65, :rg_enable
+        reg.bit 64, :rg_read
+        reg.bits 63..32, :rg_addr
+        reg.bits 31..0, :rg_data
+      end
+
+      add_reg :ctrl, 0x0 do |reg|
+        reg.bit 0, :rg_enable
+        reg.bit 1, :rg_reset
+      end
+
+      add_reg :cmd, 0x4
+
+      add_reg :count, 0x8
+
+      add_reg :data_out, 0xC
+
+      add_reg :data_in, 0x10
+
+      add_reg :p, 0x14 do |reg|
+        reg.bits 0, :p1
+        reg.bits 1, :p2
+        reg.bits 5..2, :p3
+        reg.bits 9..6, :p4
+      end
+    end
+
+    def interactive_startup
+      if tester.sim?
+        tester.start
+        startup
+      end
+    end
+
+    def startup(options = {})
+      tester.set_timeset('func', 100)
+
+      dut.pin(:rstn).drive!(1)
+      10.cycles
+      dut.pin(:tck).drive!(1)
+      10.cycles
+      dut.pin(:trstn).drive!(1)
+      10.cycles
+    end
+
+    def write_register(reg, options = {})
+      jtag.write_ir(0x8, size: 4)
+      dr.rg_enable.write(1)
+      dr.rg_read.write(0)
+      dr.rg_addr.write(reg.address)
+      dr.rg_data.write(reg.data)
+      jtag.write_dr(dr)
+    end
+
+    def read_register(reg, options = {})
+      jtag.write_ir(0x8, size: 4)
+      dr.rg_enable.write(1)
+      dr.rg_read.write(1)
+      dr.rg_addr.write(reg.address)
+      jtag.write_dr(dr)
+      dr.rg_enable.write(0)
+      dr.rg_data.copy_all(reg)
+      jtag.read_dr(dr)
+    end
+  end
+end

data/lib/tasks/origen_sim.rake

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+# You can define any Rake tasks to support your application here (or in any file
+# ending in .rake in this directory).
+#
+# Rake (Ruby Make) is very useful for creating build scripts, see this short video
+# for a quick introduction:
+# http://railscasts.com/episodes/66-custom-rake-tasks

data/pattern/test.rb

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+Pattern.create do
+  IDCODE = 0b0010
+  DEBUG  = 0b1000
+
+  ss "Some basic shift operations to verify functionality"
+  dut.jtag.write_ir(0x0, size: 4)
+  dut.jtag.read_ir(0x0, size: 4)
+  dut.jtag.write_ir(0xA, size: 4)
+  dut.jtag.read_ir(0xA, size: 4)
+  dut.jtag.write_ir(0xE, size: 4)
+  dut.jtag.read_ir(0xE, size: 4)
+
+  ss "Switch to slower timeset"
+  tester.set_timeset("func", 200)
+
+  dut.jtag.write_ir(0x5, size: 4)
+  dut.jtag.read_ir(0x5, size: 4)
+
+  ss "Read the IDCODE value"
+  dut.jtag.write_ir(IDCODE, size: 4)
+  dut.jtag.read_dr(0x149511C3, size: 32)
+
+  ss "Now try and shift in an out of the device DR"
+  dut.jtag.write_ir(0x0, size: 4)
+  dut.jtag.write_dr(0x1111_2222_3333_4444, size: 66)
+  # Should not have been applied when not selected
+  dut.jtag.read_dr(0, size: 66)
+
+  dut.jtag.write_ir(DEBUG, size: 4)
+  dut.jtag.write_dr(0x1111_2222_3333_4444, size: 66)
+  dut.jtag.read_dr(0x1111_2222_3333_4444, size: 66)
+
+  ss "Now try and read and write a register"
+  dut.cmd.write!(0x1234_5678)
+  dut.cmd.read!(0x1234_5678)
+
+  tester.simulator.poke("dut.cmd", 0x1122_3344)
+  dut.cmd.read!(0x1122_3344)
+
+  ss "Test storing a register"
+  dut.cmd.write!(0x2244_6688)
+  dut.cmd.store!
+
+  capture_value = tester.simulator.peek("origen.pins.tdo.memory")
+  unless capture_value == 0x11662244 # 0x2244_6688 reversed
+    if capture_value
+      fail "Captured #{capture_value.to_hex} instead of 0x11662244!"
+    else
+      fail "Nothing captured instead of 0x11662244!"
+    end
+  end
+
+  ss "Test sync of a register"
+  dut.cmd.write(0) # Make Origen forget the actual value
+  dut.cmd.sync
+  unless dut.cmd.data == 0x2244_6688
+    fail "CMD register did not sync from simulation"
+  end
+
+  ss "Do some operations with the counter, just for fun"
+  dut.ctrl.write!(0b11) # Reset the counter
+  dut.count.read!(0x0)
+  dut.ctrl.write!(0b1)  # Start counting
+  100.cycles
+  dut.ctrl.write!(0b0)  # Stop counting
+  dut.count.read!(0xAB)
+
+  ss "Verify that pin group read/write works"
+  dut.pins(:din_port).drive!(0x1234_5678)
+  dut.data_in.read!(0x1234_5678)
+
+  dut.data_out.write!(0)
+  dut.pins(:dout).assert!(0)
+  dut.pins(:dout).dont_care
+  dut.data_out.write!(0x5555_AAAA)
+  dut.pins(:dout).assert!(0x5555_AAAA)
+  dut.pins(:dout).dont_care
+
+  ss "Verify that tying off pins works"
+  dut.p.p1.assert!(0)
+  dut.p.p2.assert!(1)
+  dut.p.p3.assert!(0)
+  dut.p.p4.assert!(0xF)
+end

data/program/p1.rb

@@ -0,0 +1,10 @@
+Flow.create do
+
+  test :test
+
+  test :test
+
+  test :test
+
+  test :test
+end

data/templates/empty.svcf

@@ -0,0 +1,100 @@
+#
+# Preferences
+#
+preferences set plugin-enable-svdatabrowser-new 1
+preferences set toolbar-SimControl-WaveWindow {
+  usual
+  position -row 1 -pos 4 -anchor e
+}
+preferences set plugin-enable-groupscope 0
+preferences set sb-display-values 1
+preferences set plugin-enable-interleaveandcompare 0
+preferences set plugin-enable-waveformfrequencyplot 0
+preferences set toolbar-WaveZoom-WaveWindow {
+  usual
+  position -row 1 -pos 3 -anchor w
+}
+preferences set whats-new-dont-show-at-startup 1
+#
+# Groups
+#
+catch {group new -name Debug -overlay 0}
+catch {group new -name {Group 2} -overlay 0}
+catch {group new -name DUT -overlay 0}
+group using Debug
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+    [subst  {[format {origen.debug.pattern[1023:0]}]} ] \
+    [subst  {[format {origen.debug.comments[1023:0]}]} ] \
+    [subst  {[format {origen.debug.errors[31:0]}]} ]
+group using {Group 2}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group using DUT
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+
+#
+# Mnemonic Maps
+#
+mmap new -reuse -name {Boolean as Logic} -radix %b -contents {{%c=FALSE -edgepriority 1 -shape low}
+{%c=TRUE -edgepriority 1 -shape high}}
+mmap new -reuse -name {Example Map} -radix %x -contents {{%b=11???? -bgcolor orange -label REG:%x -linecolor yellow -shape bus}
+{%x=1F -bgcolor red -label ERROR -linecolor white -shape EVENT}
+{%x=2C -bgcolor red -label ERROR -linecolor white -shape EVENT}
+{%x=* -label %x -linecolor gray -shape bus}}
+
+#
+# Waveform windows
+#
+if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1604x996+38+65}] != ""} {
+    window geometry "Waveform 1" 1604x996+38+65
+}
+window target "Waveform 1" on
+waveform using {Waveform 1}
+waveform sidebar select designbrowser
+waveform set \
+    -primarycursor TimeA \
+    -signalnames name \
+    -signalwidth 175 \
+    -units ns \
+    -valuewidth 75
+waveform baseline set -time 0
+
+
+set groupId0 [waveform add -groups Debug]
+set gpGlist0 [waveform hierarchy contents $groupId0]
+set gpID0 [lindex $gpGlist0 0]
+foreach {name attrs} [subst  {
+    {[format {origen.debug.pattern[1023:0]}]} {-radix %a}
+    {[format {origen.debug.comments[1023:0]}]} {-radix %a}
+    {[format {origen.debug.errors[31:0]}]} {}
+}] childcmds {
+    {}
+    {}
+    {}
+} {
+    set expected [ join [waveform signals -format path $gpID0] ]
+    if {[string equal $name $expected] || $name == "cdivider"} {
+        if {$attrs != ""} {
+            eval waveform format $gpID0 $attrs
+        }
+        if { $childcmds != ""} {
+            eval $childcmds
+        }
+    }
+    set gpGlist0 [lrange $gpGlist0 1 end]
+    set gpID0 [lindex $gpGlist0 0]
+}
+
+
+set groupId0 [waveform add -groups DUT]
+
+

data/templates/probe.tcl.erb

@@ -0,0 +1,15 @@
+database -open waves -into <%= options[:dir] %> -default -event
+probe -create -shm origen -depth all -database waves
+#probe -create -assertions -transaction origen -depth all -database waves
+
+% Hash(options[:force]).each do |net, value|
+%   net = net.to_s.strip.sub(/^(origen\.|origen\.dut\.|\.)/, '')
+force origen.dut.<%= net %> <%= value %>
+% end
+
+% (options[:setup] || '').split("\n").each do |line|
+<%= line.strip.gsub(" dut", " origen.dut") %>
+% end
+
+run
+exit

data/templates/rtl_v/origen.v.erb

@@ -0,0 +1,194 @@
+%#`include "<%= options[:top] %>"
+
+`timescale 1ns/1ns
+
+// 0 - Data
+// 1 - Reserved 
+//
+// 0 - Drive
+//
+// 0 - Compare
+//
+// 0 - Force data 0
+// 1 - Force data 1
+module pin_driver(error, pin, sync);
+  parameter init_drive = 2; // Which means don't drive initially, set to 0 or 1 to drive
+
+  output reg error;
+  inout pin;
+  input sync;
+
+  reg [1:0] data = 0;
+  reg [1:0] force_data = 0;
+  reg compare = 0;
+  reg drive = 0;
+  reg capture = 0;
+  //reg [1023:0] memory = 0;
+  reg [127:0] memory = 0;
+  reg [127:0] memory_reversed = 0;
+  reg [127:0] sync_memory = 0;
+
+  wire drive_data = force_data[0] ? 0 : (force_data[1] ? 1 : data[0]);
+
+  assign pin = drive ? drive_data : 1'bz;
+
+  // Debug signal to show the expected data in the waves
+  wire expect_data = compare ? data[0] : 1'bz;
+
+  always @(*) begin
+    error = (compare && !capture) ? (pin == data[0] ? 0 : 1) : 0;
+  end
+
+  always @(posedge capture) begin
+    if (sync == 1) begin
+      sync_memory[127:1] <= sync_memory[126:0];
+      sync_memory[0] <= pin;
+    end else begin
+      memory[127:1] <= memory[126:0];
+      memory[0] <= pin;
+      memory_reversed[126:0] <= memory_reversed[127:1];
+      memory_reversed[127] <= pin;
+    end
+  end
+
+  initial begin
+    if (init_drive == 1) begin
+      drive = 1;
+      data[0] = 1;
+    end else if (init_drive == 0) begin
+      drive = 1;
+      data[0] = 0;
+    end
+  end
+
+endmodule
+
+module pin_drivers(errors, <%= dut.rtl_pins.map { |n, p, o| "#{p.id}_o" unless p.tie_off }.compact.join(', ') %>);
+
+% dut.rtl_pins.each do |name, pin, options|
+%   unless pin.tie_off
+  output <%= pin.id %>_o;
+%   end
+% end
+
+% dut.rtl_pins.each do |name, pin, options|
+%   unless pin.tie_off
+  wire <%= pin.id %>_err;
+%   end
+% end
+
+  output reg [31:0] errors = 0;
+  reg sync = 0;
+
+  always @(
+
+% dut.rtl_pins.each_with_index do |(name, pin, options), i|
+%   unless pin.tie_off
+%     if i == 0
+    posedge <%= pin.id %>_err
+%     else
+    or posedge <%= pin.id %>_err
+%     end
+%   end
+% end
+  ) begin
+    errors[31:0] = errors[31:0] + 1;
+  end
+
+% dut.rtl_pins.each do |name, pin, options|
+%   unless pin.tie_off
+  pin_driver <%= pin.driving? ? "#(#{pin.value}) " : '' %><%= pin.id %>(.pin(<%= pin.id %>_o), .error(<%= pin.id %>_err), .sync(sync));
+%   end 
+% end
+
+endmodule
+
+
+module debug(errors);
+
+  input [31:0] errors;
+
+  reg [1023:0] pattern = 0;
+  reg [1023:0] comments = 0;
+
+  reg handshake;
+
+endmodule
+
+module origen;
+
+  reg finish = 0;
+
+% dut.rtl_pins.each do |name, pin, options|
+%   unless pin.tie_off
+  wire <%= pin.id %>;
+%   end
+% end
+
+  wire [31:0] errors;
+
+  pin_drivers pins (
+% dut.rtl_pins.each_with_index do |(name, pin, options), i|
+%   unless pin.tie_off
+    .<%= pin.id %>_o(<%= pin.id %>),
+%   end
+% end
+    .errors(errors)
+  );
+
+  // Create wires to tie off DUT signals, initially this was done by hardcoded values when instantiating
+  // below, however the simulator didn't like that if the target pin was defined as an inout
+% dut.rtl_pins.each do |name, pin, options|
+%   if options[:group]
+%     if pin.group_index == 0
+%       if pin.primary_group.tie_off
+  wire [<%= pin.primary_group.size - 1 %>:0] <%= pin.rtl_name %>;
+  assign <%= pin.rtl_name %> = <%= "#{pin.primary_group.size}'b#{pin.tie_off.to_s * pin.primary_group.size}" %>;
+%       end
+%     end
+%   else
+%     if pin.tie_off
+  wire <%= pin.rtl_name %>;
+  assign <%= pin.rtl_name %> = 1'b<%= pin.tie_off %>;
+%     end
+%   end
+% end
+
+
+  // Instantiate the DUT
+  <%= options[:top].sub(/\..*/, '') %> dut (
+% dut.rtl_pins.each_with_index do |(name, pin, options), i|
+%   if options[:group]
+%     if pin.group_index == 0
+%       if pin.primary_group.tie_off
+    .<%= pin.rtl_name %>(<%= pin.rtl_name %>)<%= i == (dut.rtl_pins.size - 1) ? '' : ',' %>
+%       else
+    .<%= pin.rtl_name %>({
+%         pin.primary_group.each_with_index do |pin, i|
+      <%= pin.id %><%= i == (pin.primary_group.size - 1) ? '' : ',' %>
+%         end
+    })<%= i == (dut.rtl_pins.size - 1) ? '' : ',' %>
+%       end
+%     end
+%   else
+    .<%= pin.rtl_name %>(<%= pin.tie_off ? pin.rtl_name : pin.id %>)<%= i == (dut.rtl_pins.size - 1) ? '' : ',' %>
+%   end
+% end
+  );
+
+  debug debug (
+    .errors(errors)
+  );
+
+% if options[:vendor] == :icarus  
+  initial
+  begin
+    $dumpfile("dut.vcd");
+    $dumpvars(0,origen);
+  end
+% end
+    
+  always @(posedge finish) begin
+    $finish(2);
+  end
+endmodule

data/templates/web/index.md.erb

@@ -0,0 +1,37 @@
+% render "layouts/basic.html" do
+
+%# HTML tags can be embedded in mark down files if you want to do specific custom
+%# formatting like this, but in most cases that is not required.
+<h1><%= Origen.app.namespace %> <span style="font-size: 14px">(<%= Origen.app.version %>)</span></h1>
+
+### Purpose
+
+This plugin...
+
+### How To Install
+
+In your Gemfile add:
+
+~~~ruby
+gem "<%= Origen.app.name %>"
+~~~
+
+or if your application is a plugin, then add this to your <code>.gemspec</code>
+
+~~~ruby
+spec.add_runtime_dependency "<%= Origen.app.name %>", ">= <%= Origen.app.version %>"
+~~~
+
+__NOTE:__  In the case of a plugin, you will also need to <code>require '<%= Origen.app.name %>'</code> somewhere in your environment.
+
+
+### How To Use
+
+Add quickstart documentation here...
+
+
+### How To Setup a Development Environment
+
+Describe how a developer would setup a new workspace for this plugin...
+
+% end

data/templates/web/layouts/_basic.html.erb

@@ -0,0 +1,13 @@
+---
+title: <%= options[:title] || Origen.config.name %>
+---
+<%= render "partials/navbar.html", tab: options[:tab] %>
+
+<div class="row">
+%# The markdown attribute is important if you are going to include content written
+%# in markdown, without this is will be included verbatim
+  <div class="span12" markdown="1">
+<%= yield %>    
+
+</div>
+</div>

data/templates/web/partials/_navbar.html.erb

@@ -0,0 +1,20 @@
+<nav class="navbar navbar-inverse navbar-fixed-top">
+  <div class="container">
+    <div class="navbar-header">
+      <button type="button" class="navbar-toggle collapsed" data-toggle="collapse" data-target="#navbar" aria-expanded="false" aria-controls="navbar">
+        <span class="sr-only">Toggle navigation</span>
+        <span class="icon-bar"></span>
+        <span class="icon-bar"></span>
+        <span class="icon-bar"></span>
+      </button>
+      <a class="navbar-brand" href="<%= path "/" %>">Home</a>
+    </div>
+    <div id="navbar" class="collapse navbar-collapse">
+      <ul class="nav navbar-nav">
+        <li class="<%= options[:tab] == :api ? 'active' : '' %>"><a href="<%= path "/api/" %>">API</a></li>
+        <li class="<%= options[:tab] == :release ? 'active' : '' %>"><a href="<%= path "/release_notes" %>">Release Notes</a></li>
+      </ul>
+      <%= import "origen/web/logo.html" %>
+    </div><!--/.nav-collapse -->
+  </div>
+</nav>

data/templates/web/release_notes.md.erb

@@ -0,0 +1,5 @@
+% render "layouts/basic.html", tab: :release do
+
+<%= render "#{Origen.root}/doc/history" %>
+
+% end