origen_sim 0.15.0 → 0.16.0

data/lib/origen_sim/stderr_reader.rb

@@ -7,6 +7,7 @@ module OrigenSim
       @socket = socket
       @continue = true
       @logged_errors = false
+      @last_message_at = Time.now
       super do
         begin
           while @continue
@@ -17,12 +18,13 @@ module OrigenSim
                  !OrigenSim.stderr_string_exceptions.any? { |s| s.is_a?(Regexp) ? s.match?(line) : line =~ /#{s}/i }
                 # We're failing on stderr, so print its results and log as errors if its not an exception.
                 @logged_errors = true
-                Origen.log.error "(STDERR): #{line}"
+                Origen.log.error "(STDERR): #{line}", from_origen_sim: true
               elsif OrigenSim.verbose?
-                Origen.log.info line
+                Origen.log.info line, from_origen_sim: true
               else
-                Origen.log.debug line
+                Origen.log.debug line, from_origen_sim: true
               end
+              @last_message_at = Time.now
             end
           end
         rescue IOError => e
@@ -36,5 +38,9 @@ module OrigenSim
     def stop
       @continue = false
     end
+
+    def time_since_last_message
+      Time.now - @last_message_at
+    end
   end
 end

data/lib/origen_sim/stdout_reader.rb

@@ -3,31 +3,50 @@ module OrigenSim
   class StdoutReader < Thread
     attr_reader :socket, :logged_errors
 
-    def initialize(socket)
+    def initialize(socket, simulator)
       @socket = socket
       @continue = true
       @logged_errors = false
+      @last_message_at = Time.now
       super do
         begin
           while @continue
             line = @socket.gets
             if line
               line = line.chomp
-              if OrigenSim.error_strings.any? { |s| s.is_a?(Regexp) ? s.match?(line) : line =~ /#{s}/i } &&
-                 !OrigenSim.error_string_exceptions.any? { |s| s.is_a?(Regexp) ? s.match?(line) : line =~ /#{s}/i }
-                @logged_errors = true
-                Origen.log.error "(STDOUT): #{line}"
-              elsif OrigenSim.warning_strings.any? { |s| s.is_a?(Regexp) ? s.match?(line) : line =~ /#{s}/i } &&
-                    !OrigenSim.warning_string_exceptions.any? { |s| s.is_a?(Regexp) ? s.match?(line) : line =~ /#{s}/i }
-                Origen.log.warn line
+              # If line has been sent from Origen for logging
+              # https://rubular.com/r/1czQZnlhBq9YtK
+              if line =~ /^!(\d)!\[\s*((\d+),)?\s*(\d+)\]\s*(.*)/
+                if Regexp.last_match(3)
+                  time_in_sim_units = (Regexp.last_match(3).to_i << 32) | Regexp.last_match(4).to_i
+                  time_in_ns = simulator.send(:simtime_units_to_ns, time_in_sim_units)
+                else
+                  # Messages sent from the Origen testbench already have a timestamp in ns
+                  time_in_ns = Regexp.last_match(4).to_i
+                end
+                msg = "#{time_in_ns}".rjust(11) + ' ns: ' + Regexp.last_match(5)
+
+                Origen.log.send(Simulator::LOG_CODES_[Regexp.last_match(1).to_i], msg, from_origen_sim: true)
+
+                simulator.send(:max_error_abort) if line =~ /!MAX_ERROR_ABORT!/
               else
-                if OrigenSim.verbose? ||
-                   OrigenSim.log_strings.any? { |s| s.is_a?(Regexp) ? s.match?(line) : line =~ /#{s}/i }
-                  Origen.log.info line
+                if OrigenSim.error_strings.any? { |s| s.is_a?(Regexp) ? s.match?(line) : line =~ /#{s}/i } &&
+                   !OrigenSim.error_string_exceptions.any? { |s| s.is_a?(Regexp) ? s.match?(line) : line =~ /#{s}/i }
+                  @logged_errors = true
+                  Origen.log.error "(STDOUT): #{line}", from_origen_sim: true
+                elsif OrigenSim.warning_strings.any? { |s| s.is_a?(Regexp) ? s.match?(line) : line =~ /#{s}/i } &&
+                      !OrigenSim.warning_string_exceptions.any? { |s| s.is_a?(Regexp) ? s.match?(line) : line =~ /#{s}/i }
+                  Origen.log.warn line, from_origen_sim: true
                 else
-                  Origen.log.debug line
+                  if OrigenSim.verbose? ||
+                     OrigenSim.log_strings.any? { |s| s.is_a?(Regexp) ? s.match?(line) : line =~ /#{s}/i }
+                    Origen.log.info line, from_origen_sim: true
+                  else
+                    Origen.log.debug line, from_origen_sim: true
+                  end
                 end
               end
+              @last_message_at = Time.now
             end
           end
         rescue IOError => e
@@ -41,5 +60,9 @@ module OrigenSim
     def stop
       @continue = false
     end
+
+    def time_since_last_message
+      Time.now - @last_message_at
+    end
   end
 end

data/lib/origen_sim/tester.rb

@@ -19,11 +19,6 @@ module OrigenSim
       super()
     end
 
-    # Returns the current cycle count
-    def cycle_count
-      @cycle_count || 0
-    end
-
     def simulator
       OrigenSim.simulator
     end
@@ -43,9 +38,9 @@ module OrigenSim
       end
       @sync_pins.map do |pin|
         if @sync_cycles.size == 1
-          simulator.peek("origen.pins.#{pin.id}.sync_memory[0]")
+          simulator.peek("#{simulator.testbench_top}.pins.#{pin.id}.sync_memory[0]")
         else
-          simulator.peek("origen.pins.#{pin.id}.sync_memory[#{@sync_cycles - 1}:0]")
+          simulator.peek("#{simulator.testbench_top}.pins.#{pin.id}.sync_memory[#{@sync_cycles - 1}:0]")
         end
       end
     end
@@ -62,9 +57,9 @@ module OrigenSim
     end
 
     # Flush any buffered simulation output, this should cause live waveviewers to
-    # reflect the latest state
-    def flush
-      simulator.flush
+    # reflect the latest state and the console and log files to update
+    def flush(*args)
+      simulator.flush(*args)
     end
 
     def set_timeset(name, period_in_ns)
@@ -79,24 +74,35 @@ module OrigenSim
 
     # This method intercepts vector data from Origen, removes white spaces and compresses repeats
     def push_vector(options)
-      unless options[:timeset]
-        puts 'No timeset defined!'
-        puts 'Add one to your top level startup method or target like this:'
-        puts '$tester.set_timeset("nvmbist", 40)   # Where 40 is the period in ns'
-        exit 1
-      end
-      flush_comments unless @comment_buffer.empty?
-      simulator.cycle(options[:repeat] || 1)
-      @cycle_count ||= 0
-      @cycle_count += options[:repeat] || 1
-      if @after_next_vector
-        @after_next_vector.call(@after_next_vector_args)
-        @after_next_vector = nil
+      if simulator.simulation.max_errors_exceeded
+        fail Origen::Generator::AbortError, 'The max error count has been exceeded in the simulation'
+      else
+        unless options[:timeset]
+          puts 'No timeset defined!'
+          puts 'Add one to your top level startup method or target like this:'
+          puts '$tester.set_timeset("nvmbist", 40)   # Where 40 is the period in ns'
+          exit 1
+        end
+        flush_comments unless @comment_buffer.empty?
+        simulator.cycle(options[:repeat] || 1)
+        if @after_next_vector
+          @after_next_vector.call(@after_next_vector_args)
+          @after_next_vector = nil
+        end
       end
     end
 
     def c1(msg, options = {})
-      @comment_buffer << msg if @step_comment_on
+      if @step_comment_on
+        simulator.log msg
+        @comment_buffer << msg
+      end
+    end
+
+    def ss(msg = nil)
+      simulator.log '=' * 70
+      super
+      simulator.log '=' * 70
     end
 
     def loop_vectors(name, number_of_loops, options = {})
@@ -132,7 +138,7 @@ module OrigenSim
           end
         end
       end
-      if simulator.sync_active?
+      if simulator.sync_active? && @sync_cycles
         @sync_cycles += 1
         pins.each do |pin|
           @sync_pins << pin unless @sync_pins.include?(pin)
@@ -222,12 +228,186 @@ module OrigenSim
 
     def wait(*args)
       super
-      flush if Origen.running_interactively? && dut_version > '0.12.1'
+      if Origen.running_interactively? ||
+         (defined?(Byebug) && Byebug.try(:mode) == :attached)
+        flush quiet: true
+      end
     end
 
-    # def method_missing(m, *args, &block)
-    #  super
-    # end
+    def log_file_written(path)
+      simulator.simulation.log_files << path if simulator.simulation
+    end
+
+    def read_register(reg_or_val, options = {})
+      # This could be called multiple times for the same transaction
+      if read_reg_open?
+        yield
+      else
+        @read_reg_meta_supplied = false
+        @read_reg_open = true
+        @read_reg_cycles = {}
+        unless @supports_transactions_set
+          @supports_transactions = dut_version > '0.15.0'
+          @supports_transactions_set = true
+        end
+
+        if reg_or_val.respond_to?(:named_bits)
+          bit_names = reg_or_val.named_bits.map { |name, bits| name }.uniq
+          expected = bit_names.map do |name|
+            bits = reg_or_val.bits(name)
+            if bits.is_to_be_read?
+              [name, bits.status_str(:read)]
+            end
+          end.compact
+
+          # Save which bits are being read for later, the driver performing the read will
+          # clear the register flags
+          read_flags = reg_or_val.map(&:is_to_be_read?)
+        end
+
+        error_count = simulator.error_count
+
+        simulator.start_read_reg_transaction if @supports_transactions
+
+        yield
+
+        if @supports_transactions
+          errors_captured, exceeded_max_errors, errors = *(simulator.stop_read_reg_transaction)
+        end
+
+        @read_reg_open = false
+
+        if simulator.error_count > error_count
+          if @supports_transactions
+            actual_data_available = true
+            if exceeded_max_errors
+              Origen.log.warning 'The number of errors in this transaction exceeded the capture buffer, the actual data reported here may not be accurate'
+            end
+            out_of_sync = simulator.simulation.cycle_count != simulator.cycle_count
+            if out_of_sync
+              Origen.log.warning 'Something has gone wrong and Origen and the simulator do not agree on the current cycle number, it is not possible to resolve the actual data'
+              actual_data_available = false
+            else
+              diffs = []
+              errors.each do |error|
+                if c = read_reg_cycles[error[:cycle]]
+                  if p = c[simulator.pins_by_rtl_name[error[:pin_name]]]
+                    if p[:position]
+                      diffs << [p[:position], error[:recieved], error[:expected]]
+                    end
+                  end
+                end
+              end
+              if diffs.empty?
+                if @read_reg_meta_supplied
+                  Origen.log.warning 'It looks like the miscompare(s) occurred on pins/cycles that are not associated with register data'
+                else
+                  Origen.log.warning 'It looks like your current read register driver does not provide the necessary meta-data to map these errors to an actual register value'
+                end
+                actual_data_available = false
+              end
+            end
+          else
+            Origen.log.warning 'Your DUT needs to be compiled with a newer version of OrigenSim to support reporting of the actual read data from this failed transaction'
+            actual_data_available = false
+          end
+
+          # If a register object has been supplied...
+          if read_flags
+            Origen.log.error "Errors occurred reading register #{reg_or_val.path}:"
+            if actual_data_available
+              actual = nil
+              reg_or_val.preserve_flags do
+                reg_or_val.each_with_index do |bit, i|
+                  bit.read if read_flags[i]
+                end
+
+                diffs.each do |position, received, expected|
+                  reg_or_val[position].data = received
+                end
+
+                actual = bit_names.map do |name|
+                  bits = reg_or_val.bits(name)
+                  if bits.is_to_be_read?
+                    [name, bits.status_str(:read)]
+                  end
+                end.compact
+
+                # Put the data back so the application behaves as it would if generating
+                # for a non-simulation tester target
+                diffs.each do |position, received, expected|
+                  reg_or_val[position].data = expected
+                end
+              end
+            end
+
+            expected.each do |name, expected|
+              msg = "#{reg_or_val.path}.#{name}: expected #{expected}"
+              if actual_data_available
+                received_ = nil
+                actual.each do |name2, received|
+                  if name == name2
+                    received_ = received
+                    msg += " received #{received}"
+                  end
+                end
+                if expected == received_
+                  Origen.log.info msg
+                else
+                  Origen.log.error msg
+                end
+              else
+                msg += " received #{expected}" if @read_reg_meta_supplied
+                Origen.log.error msg
+              end
+            end
+          else
+            Origen.log.error 'Errors occurred while reading a register:'
+            msg = "expected #{reg_or_val.to_s(16).upcase}"
+            if actual_data_available
+              actual = reg_or_val
+              diffs.each do |position, received, expected|
+                if received == 1
+                  actual |= (1 << position)
+                else
+                  lower = actual[(position - 1)..0]
+                  actual = actual >> (position + 1)
+                  actual = actual << (position + 1)
+                  actual |= lower
+                end
+              end
+              msg += " received #{actual.to_s(16).upcase}"
+            else
+              msg += " received #{reg_or_val.to_s(16).upcase}" if @read_reg_meta_supplied
+            end
+            Origen.log.error msg
+          end
+
+          Origen.log.error
+          caller.each do |line|
+            if Pathname.new(line.split(':').first).expand_path.to_s =~ /^#{Origen.root}(?!(\/lbin|\/vendor\/gems)).*$/
+              Origen.log.error line
+            end
+          end
+        end
+      end
+    end
+
+    def read_reg_open?
+      @read_reg_open
+    end
+
+    def read_reg_cycles
+      @read_reg_cycles
+    end
+
+    def cycle_count
+      simulator.simulation.cycle_count
+    end
+
+    def read_reg_meta_supplied=(val)
+      @read_reg_meta_supplied = val
+    end
 
     private
 

data/lib/origen_sim_dev/dut.rb

@@ -121,37 +121,39 @@ module OrigenSimDev
     end
 
     def read_register(reg, options = {})
-      # Special read for this register to test sync'ing over a parallel
-      if reg.id == :parallel_read
-        pins = []
-        reg.shift_out_with_index do |bit, i|
-          if bit.is_to_be_stored?
-            pins << dut.pins(:dout)[i]
+      tester.read_register(reg, options) do
+        # Special read for this register to test sync'ing over a parallel
+        if reg.id == :parallel_read
+          pins = []
+          reg.shift_out_with_index do |bit, i|
+            if bit.is_to_be_stored?
+              pins << dut.pins(:dout)[i]
+            end
           end
-        end
-        tester.store_next_cycle(*pins.reverse)
-        1.cycle
-        dut.pins(:dout).dont_care
-      else
-        if reg.path =~ /ip(\d)/
-          ir_val = 0b0100 | Regexp.last_match(1).to_i
-          jtag.write_ir(ir_val, size: 4)
-          ip = reg.parent
-          ip.dr.bits(:write).write(0)
-          ip.dr.bits(:address).write(reg.address)
-          ip.dr.bits(:data).write(0)
-          jtag.write_dr(ip.dr)
-          ip.dr.bits(:data).copy_all(reg)
-          jtag.read_dr(ip.dr)
+          tester.store_next_cycle(*pins.reverse)
+          1.cycle
+          dut.pins(:dout).dont_care
         else
-          jtag.write_ir(0x8, size: 4)
-          dr.rg_enable.write(1)
-          dr.rg_read.write(1)
-          dr.rg_addr.write(reg.address)
-          jtag.write_dr(dr)
-          dr.rg_enable.write(0)
-          dr.rg_data.copy_all(reg)
-          jtag.read_dr(dr)
+          if reg.path =~ /ip(\d)/
+            ir_val = 0b0100 | Regexp.last_match(1).to_i
+            jtag.write_ir(ir_val, size: 4)
+            ip = reg.parent
+            ip.dr.bits(:write).write(0)
+            ip.dr.bits(:address).write(reg.address)
+            ip.dr.bits(:data).write(0)
+            jtag.write_dr(ip.dr)
+            ip.dr.bits(:data).copy_all(reg)
+            jtag.read_dr(ip.dr)
+          else
+            jtag.write_ir(0x8, size: 4)
+            dr.rg_enable.write(1)
+            dr.rg_read.write(1)
+            dr.rg_addr.write(reg.address)
+            jtag.write_dr(dr)
+            dr.rg_enable.write(0)
+            dr.rg_data.copy_all(reg)
+            jtag.read_dr(dr)
+          end
         end
       end
     end