origen_sim 0.14.0 → 0.15.0

checksums.yaml

@@ -1,7 +1,7 @@
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-  data.tar.gz: 8f6582388d383142beebaf1c313936b78b6f495f0b2403193df02f8ae51f25f0
+  metadata.gz: a37dd737642a62e60b4cc98f47928b659004f3b89e771aa9efabfd2610622080
+  data.tar.gz: 74309fc46e200d299e8704e4599fdd3553abd1cb380ec56a9c7d926f1a7728f7
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+  data.tar.gz: 0404e46a47d0d02d5933ed238fc84b6660f3cbae5f70d7c632c4ca2cb87c8ada52b8a2b382becf4e59b2c276a423890b569de6a227b6d31f329eee26ca66711f

data/config/application.rb

@@ -52,7 +52,8 @@ class OrigenSimApplication < Origen::Application
       dir: "example_rtl",
       rc_url: 'https://github.com/Origen-SDK/example_rtl.git',
       version: "master",
-      development: true
+      development: true,
+      #path: "/home/stephen/Code/github/example_rtl"
     }
   ]
 

data/config/shared_commands.rb

@@ -36,6 +36,10 @@ when "sim:unpack"
   OrigenSim::Commands::Pack.unpack
   exit 0
 
+when "sim:run"
+  OrigenSim.run_source(ARGV[0])
+  exit 0
+  
 #when "sim:list"
 #  require "#{Origen.root!}/lib/origen_sim/commands/pack"
 #  OrigenSim::Commands::Pack.list

data/config/version.rb

@@ -1,6 +1,6 @@
 module OrigenSim
   MAJOR = 0
-  MINOR = 14
+  MINOR = 15
   BUGFIX = 0
   DEV = nil
 

data/lib/origen_sim/commands/build.rb

@@ -3,7 +3,7 @@ require 'origen_sim'
 require_relative '../../../config/version'
 require 'origen_verilog'
 
-options = { source_dirs: [], testbench_name: 'origen', defines: [] }
+options = { incl_files: [], source_dirs: [], testbench_name: 'origen', defines: [], user_details: {}, initial_pin_states: {}, verilog_top_output_name: 'origen' }
 
 # App options are options that the application can supply to extend this command
 app_options = @application_options || []
@@ -22,9 +22,43 @@ Usage: origen sim:build TOP_LEVEL_VERILOG_FILE [options]
   opts.on('-s', '--source_dir PATH', 'Directories to look for include files in (the directory containing the top-level is already considered)') do |path|
     options[:source_dirs] << path
   end
+  opts.on('--sv', 'Generate a .sv file instead of a .v file.') { |t| options[:sv] = t }
+  opts.on('--verilog_top_output_name NAME', 'Renames the output filename from origen.v to NAME.v') do |name|
+    options[:verilog_top_output_name] = name
+  end
   opts.on('--define MACRO', 'Specify a compiler define') do |macro|
     options[:defines] << macro
   end
+  opts.on('--init_pin_state PIN_AND_STATE', 'Specify how the pins should be initialized.') do |pin_and_state|
+    name, state = pin_and_state.split(':')
+
+    # Make sure that we recognize the pin state option before building.
+    unless OrigenSim::INIT_PIN_STATE_MAPPING.include?(state)
+      fail "Provide state '#{state}' to --init_pin_state pin_and_state not recognized!"
+    end
+    (options[:initial_pin_states])[name.to_sym] = OrigenSim::INIT_PIN_STATE_MAPPING[state]
+  end
+  opts.on('--include FILE' 'Specify files to include in the top verilog file.') { |f| options[:incl_files] << f }
+
+  # Specifying snapshot details
+  opts.on('--device_name NAME', '(Snapshot Detail) Specify a device name') { |n| options[:device_name] = n }
+  opts.on('--testbench_version VER', '(Snapshot Detail) Specify a version of the testbench this snapshot was built from') { |v| options[:testbench_version] = v }
+  opts.on('--revision REV', '(Snapshot Detail) Specify a revision of the snapshot') { |r| options[:revision] = r }
+  opts.on('--revision_note REV_NOTE', '(Snapshot Detail) Specify a brief note on this revision of the snapshot') { |n| options[:revision_note] = n }
+  opts.on('--author AUTHOR', '(Snapshot Detail) Specify the author of the snapshot (default is just Origen.current_user)') { |a| options[:author] = a }
+
+  # User-defined snapshot details
+  opts.on('--USER_DETAIL NAME_AND_VALUE', 'Specify custom user-defined details to build into the snapshot details. Format as NAME:VALUE, e.g.: \'--USER_DETAIL BUILD_TYPE:RTL\'') do |name_and_value|
+    name, value = name_and_value.split(':')
+
+    unless name.upcase == name
+      Origen.log.warning "Non-capitalized user detail '#{name}' was given!"
+      Origen.log.warning 'OrigenSim forces the Verilog practice that parameters should be capitalized.'
+      Origen.log.warning "The parameter '#{name.upcase}' will be used instead"
+      name.upcase!
+    end
+    (options[:user_details])[name] = value
+  end
   opts.on('-d', '--debugger', 'Enable the debugger') {  options[:debugger] = true }
   app_options.each do |app_option|
     opts.on(*app_option) {}
@@ -82,19 +116,37 @@ rtl_top_module = mod.name
 
 mod.to_top_level # Creates dut
 
+# Update the pins with any setings from the command line
+options[:initial_pin_states].each do |pin, state|
+  dut.pins(pin).meta[:origen_sim_init_pin_state] = state
+end
+
 if $_testing_build_return_dut_
   dut
 
 else
 
   output_directory = options[:output] || Origen.config.output_directory
+  output_name = options[:sv] ? "#{options[:verilog_top_output_name]}.sv" : "#{options[:verilog_top_output_name]}.v"
 
   Origen.app.runner.launch action:            :compile,
                            files:             "#{Origen.root!}/templates/rtl_v/origen.v.erb",
+                           output_file_name:  output_name,
                            output:            output_directory,
                            check_for_changes: false,
                            quiet:             true,
-                           options:           { vendor: :cadence, top: dut.name, incl: options[:incl_files] }
+                           preserve_target:   true,
+                           options:           {
+                             vendor:            :cadence,
+                             top:               dut.name,
+                             incl:              options[:incl_files],
+                             device_name:       options[:device_name],
+                             revision:          options[:revision],
+                             revision_note:     options[:revision_note],
+                             parent_tb_version: options[:testbench_version],
+                             user_details:      options[:user_details],
+                             author:            options[:author]
+                           }
 
   Origen.app.runner.launch action:            :compile,
                            files:             "#{Origen.root!}/ext",
@@ -113,7 +165,7 @@ else
   puts
   puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
   puts
-  puts "  #{output_directory}/origen.v \\"
+  puts "  #{output_directory}/#{output_name} \\"
   puts "  #{output_directory}/*.c \\"
   puts '  -ccargs "-std=c99" \\'
   puts '  -top origen \\'
@@ -124,7 +176,7 @@ else
   puts
   puts 'Here is an example which may work for the file you just parsed (add additional -incdir options at the end if required):'
   puts
-  puts "  #{ENV['ORIGEN_SIM_IRUN'] || 'irun'} #{rtl_top} #{output_directory}/origen.v #{output_directory}/*.c -ccargs \"-std=c99\" -top origen -elaborate -snapshot origen -access +rw -timescale 1ns/1ns -incdir #{Pathname.new(rtl_top).dirname}"
+  puts "  #{ENV['ORIGEN_SIM_IRUN'] || 'irun'} #{rtl_top} #{output_directory}/#{output_name} #{output_directory}/*.c -ccargs \"-std=c99\" -top origen -elaborate -snapshot origen -access +rw -timescale 1ns/1ns -incdir #{Pathname.new(rtl_top).dirname}"
   puts
   puts 'Copy the following directory (produced by irun) to simulation/<target>/cadence/. within your Origen application:'
   puts
@@ -136,7 +188,7 @@ else
   puts
   puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
   puts
-  puts "  #{output_directory}/origen.v \\"
+  puts "  #{output_directory}/#{output_name} \\"
   puts "  #{output_directory}/bridge.c \\"
   puts "  #{output_directory}/client.c \\"
   puts '  -CFLAGS "-std=c99" \\'
@@ -149,7 +201,7 @@ else
   puts
   puts 'Here is an example which may work for the file you just parsed (add additional -incdir options at the end if required):'
   puts
-  puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} #{output_directory}/origen.v #{output_directory}/bridge.c #{output_directory}/client.c -CFLAGS \"-std=c99\" +vpi #{output_directory}/origen.c -timescale=1ns/1ns  +define+ORIGEN_VPD=1 +incdir+#{Pathname.new(rtl_top).dirname} -debug_access+all -PP"
+  puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} #{output_directory}/#{output_name} #{output_directory}/bridge.c #{output_directory}/client.c -CFLAGS \"-std=c99\" +vpi #{output_directory}/origen.c -timescale=1ns/1ns  +define+ORIGEN_VPD=1 +incdir+#{Pathname.new(rtl_top).dirname} -debug_access+all -PP"
   puts
   puts 'Copy the following files (produced by vcs) to simulation/<target>/synopsys/. within your Origen application:'
   puts
@@ -166,13 +218,13 @@ else
   puts
   puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
   puts
-  puts "  #{output_directory}/origen.v \\"
+  puts "  #{output_directory}/#{output_name} \\"
   puts '  -o origen.vvp \\'
   puts '  -DORIGEN_VCD'
   puts
   puts 'Here is an example which may work for the file you just parsed (add additional source dirs with more -I options at the end if required):'
   puts
-  puts "  #{ENV['ORIGEN_SIM_IVERILOG'] || 'iverilog'} #{rtl_top} #{output_directory}/origen.v -o origen.vvp -DORIGEN_VCD -I #{Pathname.new(rtl_top).dirname}"
+  puts "  #{ENV['ORIGEN_SIM_IVERILOG'] || 'iverilog'} #{rtl_top} #{output_directory}/#{output_name} -o origen.vvp -DORIGEN_VCD -I #{Pathname.new(rtl_top).dirname}"
   puts
   puts 'Copy the following files (produced by iverilog) to simulation/<target>/icarus/. within your Origen application:'
   puts
@@ -185,8 +237,8 @@ else
   puts
   puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
   puts
-  puts "  #{output_directory}/origen.v \\"
-  puts "  #{output_directory}/bridge.c \\"
+  puts "  #{output_directory}/#{output_name} \\"
+  puts "  #{output_directory}/brdige.c \\"
   puts "  #{output_directory}/client.c \\"
   puts '  -CFLAGS "-std=c99" \\'
   puts '  +vpi \\'
@@ -202,7 +254,7 @@ else
   puts
   puts 'Here is an example which may work for the file you just parsed (add additional -incdir options at the end if required):'
   puts
-  puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} #{output_directory}/origen.v #{output_directory}/bridge.c #{output_directory}/client.c -CFLAGS \"-std=c99\" +vpi #{output_directory}/origen.c +define+ORIGEN_FSDB=1 +incdir+#{Pathname.new(rtl_top).dirname} -debug_access+all +lint=all,noVCDE,noIWU,noVNGS,noCAWM-L,noPORTFRC,noZERO,noNS -PP -timescale=1ns/100ps -full64 -lca -kdb"
+  puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} #{output_directory}/#{output_name} #{output_directory}/bridge.c #{output_directory}/client.c -CFLAGS \"-std=c99\" +vpi #{output_directory}/origen.c +define+ORIGEN_FSDB=1 +incdir+#{Pathname.new(rtl_top).dirname} -debug_access+all +lint=all,noVCDE,noIWU,noVNGS,noCAWM-L,noPORTFRC,noZERO,noNS -PP -timescale=1ns/100ps -full64 -lca -kdb"
   puts
   puts 'Copy the following files (produced by vcs) to simulation/<target>/verdi/. within your Origen application:'
   puts

data/lib/origen_sim/heartbeat.rb

@@ -1,7 +1,7 @@
 require 'thread'
 module OrigenSim
   class Heartbeat < Thread
-    attr_reader :socket
+    attr_reader :socket, :simulation
 
     # Can't use this with threads currently because Byebug pauses the sleep,
     # during a breakpoint, which means that the simulator is killed.
@@ -9,7 +9,8 @@ module OrigenSim
     # whenever this is set to false.
     THREADSAFE = false
 
-    def initialize(socket)
+    def initialize(simulation, socket)
+      @simulation = simulation
       @socket = socket
       @continue = true
       super do
@@ -17,8 +18,12 @@ module OrigenSim
           begin
             socket.write("OK\n")
           rescue Errno::EPIPE => e
-            Origen.log.error 'Communication with the simulation monitor has been lost!'
-            sleep 2
+            exit 0 if simulation.ended
+            if simulation.monitor_running?
+              Origen.log.error 'Communication with the simulation monitor has been lost (though it seems to still be running)!'
+            else
+              Origen.log.error 'The simulation monitor has stopped unexpectedly!'
+            end
             exit 1
           end
           sleep 5

data/lib/origen_sim/simulation.rb

@@ -18,6 +18,10 @@ module OrigenSim
     # Returns the communication socket used for sending commands to the Origen VPI running
     # in the simulation process
     attr_reader :socket
+    # Returns false when the simulation is running and will be set to true once all instructions
+    # have been sent and executed by the simulator and immediately before the end_simulation
+    # instruction is sent to the simulator.
+    attr_accessor :ended
 
     def initialize(id, view_wave_command)
       @id = id
@@ -25,6 +29,7 @@ module OrigenSim
       @completed_cleanly = false
       @failed_to_start = false
       @logged_errors = false
+      @ended = false
       @error_count = 0
       @socket_ids = {}
 
@@ -85,6 +90,24 @@ module OrigenSim
       end
     end
 
+    def ended=(val)
+      # If running the heartbeat from a fork we need to communicate to it that the simulation has
+      # ended by writing to a file
+      if val == true && !Heartbeat::THREADSAFE
+        FileUtils.touch(ended_file)
+      else
+        @ended = val
+      end
+    end
+
+    def ended_file
+      @ended_file ||= begin
+        dir = Origen.root.join('tmp', 'origen_sim', 'ended')
+        FileUtils.mkdir_p(dir.to_s)
+        dir.join(socket_number).to_s
+      end
+    end
+
     # Provide a heartbeat to let the parallel Ruby process in charge of the simulator
     # know that the master Origen process is still alive. If the Origen process crashes and leaves
     # the simulator running, the child process will automatically reap it after a couple of missed
@@ -92,20 +115,25 @@ module OrigenSim
     def start_heartbeat
       @heartbeat = @server_heartbeat.accept
       if Heartbeat::THREADSAFE
-        @heartbeat_thread = Heartbeat.new(@heartbeat)
+        @heartbeat_thread = Heartbeat.new(self, @heartbeat)
       else
+        ended_file # Cache this file name before forking
         @heartbeat_pid = fork do
           loop do
             begin
               @heartbeat.write("OK\n")
             rescue Errno::EPIPE => e
-              if monitor_running?
-                Origen.log.error 'Communication with the simulation monitor has been lost (though it seems to still be running)!'
+              if File.exist?(ended_file)
+                FileUtils.rm_f(ended_file)
+                exit 0
               else
-                Origen.log.error 'The simulation monitor has stopped unexpectedly!'
+                if monitor_running?
+                  Origen.log.error 'Communication with the simulation monitor has been lost (though it seems to still be running)!'
+                else
+                  Origen.log.error 'The simulation monitor has stopped unexpectedly!'
+                end
+                exit 1
               end
-              sleep 2 # To make sure that any log output from the simulator is captured before we pull the plug
-              exit 1
             end
             sleep 5
           end
@@ -125,6 +153,7 @@ module OrigenSim
         rescue Errno::ECHILD
           # Heartbeat process has already stopped, so ignore this.
         end
+        FileUtils.rm_f(ended_file) if File.exist?(ended_file)
       end
     end
 

data/lib/origen_sim/{artifacts.rb → simulator/artifacts.rb}

@@ -74,6 +74,10 @@ module OrigenSim
       alias_method :pop_method, :populate_method
 
       def populate
+        unless Dir.exist?(run_target.dirname)
+          FileUtils.mkdir_p(run_target.dirname)
+        end
+
         if populate_method == :symlink
           File.symlink(target, run_target)
         elsif populate_method == :copy

data/lib/origen_sim/simulator/snapshot_details.rb

@@ -0,0 +1,59 @@
+require 'origen_sim/simulator/user_details'
+
+module OrigenSim
+  class Simulator
+    # The SnapshotDetails and UserDetails share a lot in common, with the
+    # SnapshotDetails containing a bit of extra stuff.
+    class SnapshotDetails < UserDetails
+      attr_reader :_user_details
+
+      def initialize(simulator:, cache: true)
+        # @fetch_error_message = "OrigenSim was unable to find net #{detail_names_net} in the snapshot! Unable to retrieve snapshot details!"
+        super(simulator: simulator, cache: cache)
+
+        @_user_details = UserDetails.new(simulator: simulator, cache: cache)
+      end
+
+      def detail_to_net(d)
+        "#{@simulator.testbench_top}.debug.snapshot_details.#{d}"
+      end
+
+      def _missing_detail_message(d)
+        "Detail '#{d}' is not an available snapshot detail name!"
+      end
+
+      ### The user details interface is the same as the snapshot_details ###
+      ### just on the snapshot_details itself                            ###
+
+      def user_details(d = nil)
+        if d
+          _user_details[d]
+        else
+          _user_details
+        end
+      end
+
+      def user_detail(d)
+        user_details(d)
+      end
+    end
+
+    ### Add the following methods to the simulator ###
+
+    def _snapshot_details
+      @_snapshot_details ||= SnapshotDetails.new(simulator: self, **@configuration[:snapshot_details_options])
+    end
+
+    def snapshot_details(d = nil)
+      if d
+        _snapshot_details[d]
+      else
+        _snapshot_details
+      end
+    end
+
+    def snapshot_detail(d)
+      snapshot_details(d)
+    end
+  end
+end

data/lib/origen_sim/simulator/user_details.rb

@@ -0,0 +1,107 @@
+module OrigenSim
+  class Simulator
+    class UserDetails
+      DETAIL_NAMES_NET = '_AVAILABLE_DETAILS_'
+
+      attr_reader :cache
+      attr_reader :details
+
+      def initialize(simulator:, cache: true)
+        @simulator = simulator
+        @fetch_error_message = "OrigenSim was unable to find net #{detail_names_net} in the snapshot! Unable to retrieve snapshot details!"
+        @details = fetch
+        @cache = cache
+      end
+
+      # This gets called for some reason when 'puts' is used for the object.
+      # Provide something here to avoid seeing the error message.
+      def to_ary
+        nil
+      end
+
+      def method_missing(method, *args, &block)
+        self[method]
+      end
+
+      def [](d)
+        _d = d.to_s.upcase
+        if cache
+          if details
+            if details.key?(_d)
+              details[_d]
+            else
+              Origen.log.error(_missing_detail_message(_d))
+              nil
+            end
+          else
+            # if detail fetching failed, but the user is still trying to query
+            # details, re-print the fetch error message
+            Origen.log.error(@fetch_error_message)
+            nil
+          end
+        else
+          details = fetch
+          if details
+            if details.key?(_d)
+              details[_d]
+            else
+              Origen.log.error(_missing_detail_message(_d))
+              nil
+            end
+          end
+        end
+      end
+
+      def _missing_detail_message(d)
+        "Detail '#{d}' was not provided in this snapshot!"
+      end
+
+      # Fetches the details available in the snapshot.
+      #   This is done at runtime to get the latest details list from the snapshot
+      #   but can be cached for future use.
+      # @note This requires the details <code>origen.debug.AVAILABLE_DETAILS</code>
+      #  to be defined. This should be a comma-separeted string of the available values.
+      #  It will be assumed that each details will be defined in the snapshot.
+      def fetch
+        puts 'FETCHING!'.cyan
+        # Read the available details.
+        # names = str_peek("#{debug_module}.PARAMETER_NAMES").split(',')
+        names = @simulator.peek_str(detail_names_net)
+        if names.nil?
+          Origen.log.error(@fetch_error_message)
+
+          # Returning false indicates that the fetch failed.
+          false
+        elsif names.empty?
+          # Empty string was returned. No available details/no details given.
+          {}
+        else
+          # Fetch each detail value and return as a Hash
+          names.split(',').map do |n|
+            [n, @simulator.str_peek(detail_to_net(n))]
+          end.to_h
+        end
+      end
+
+      def available_details
+        if details
+          details.keys
+        else
+          details = fetch
+          @details = details if cache
+          if details
+            details.keys
+          end
+        end
+      end
+
+      def detail_to_net(d)
+        "#{@simulator.testbench_top}.debug.snapshot_details.user_details.#{d}"
+      end
+
+      def detail_names_net
+        detail_to_net(DETAIL_NAMES_NET)
+      end
+    end
+  end
+end

data/lib/origen_sim/simulator.rb

@@ -1,5 +1,6 @@
 require 'origen_sim/simulation'
-require 'origen_sim/artifacts'
+require 'origen_sim/simulator/artifacts'
+require 'origen_sim/simulator/snapshot_details'
 
 module OrigenSim
   # Responsible for managing and communicating with the simulator
@@ -117,7 +118,9 @@ module OrigenSim
       unless VENDORS.include?(options[:vendor])
         fail "Unknown vendor #{options[:vendor]}, valid values are: #{VENDORS.map { |v| ':' + v.to_s }.join(', ')}"
       end
-      @configuration = options
+      @configuration = {
+        snapshot_details_options: {}
+      }.merge(options)
       @tmp_dir = nil
 
       # Temporary workaround for bug in componentable, which is making the container a class object, instead of an
@@ -171,7 +174,7 @@ module OrigenSim
     end
 
     def target_artifact_dir
-      Pathname(@configuration[:target_artifact_dir] || "#{Origen.app.root}/simulation/#{Origen.target.name}/artifacts")
+      Pathname(@configuration[:target_artifact_dir] || "#{Origen.app.root}/simulation/#{id}/artifacts")
     end
 
     def artifact_run_dir
@@ -311,7 +314,7 @@ module OrigenSim
 
       when :synopsys
         if configuration[:verdi]
-          cmd = "#{compiled_dir}/simv +socket+#{socket_id} +FSDB_ON +fsdbfile+#{Origen.root}/waves/#{Origen.target.name}/#{wave_file_basename}.fsdb +memcbk +vcsd"
+          cmd = "#{compiled_dir}/simv +socket+#{socket_id} +FSDB_ON +fsdbfile+#{Origen.root}/waves/#{id}/#{wave_file_basename}.fsdb +memcbk +vcsd"
         else
           cmd = "#{compiled_dir}/simv +socket+#{socket_id} -vpd_file #{wave_file_basename}.vpd"
         end
@@ -364,12 +367,12 @@ module OrigenSim
         OrigenSim.flow.to_s
       else
         if Origen.app.current_job
-          @last_wafe_file_basename = Pathname.new(Origen.app.current_job.output_file).basename('.*').to_s
+          @last_wave_file_basename = Pathname.new(Origen.app.current_job.output_file).basename('.*').to_s
         else
           if Origen.interactive?
             'interactive'
           else
-            @last_wafe_file_basename
+            @last_wave_file_basename || 'unnamed_pattern'
           end
         end
       end
@@ -407,7 +410,7 @@ module OrigenSim
           cmd = "cd #{edir} && "
           cmd += configuration[:verdi] || 'verdi'
           dir = Pathname.new(wave_dir).relative_path_from(edir.expand_path)
-          cmd += " -ssz -dbdir #{Origen.root}/simulation/#{Origen.target.name}/synopsys/simv.daidir/ -ssf #{dir}/#{wave_file_basename}.fsdb"
+          cmd += " -ssz -dbdir #{Origen.root}/simulation/#{id}/synopsys/simv.daidir/ -ssf #{dir}/#{wave_file_basename}.fsdb"
           f = Pathname.new(wave_config_file).relative_path_from(edir.expand_path)
           cmd += " -sswr #{f}"
           cmd += ' &'
@@ -643,6 +646,7 @@ module OrigenSim
         @pattern_count += 1
       end
     end
+    alias_method :setup_simulation, :before_pattern
 
     # This will be called at the end of every pattern, make
     # sure the simulator is not running behind before potentially
@@ -653,6 +657,7 @@ module OrigenSim
         simulation.completed_cleanly = true unless @flow_running
       end
     end
+    alias_method :complete_simulation, :pattern_generated
 
     def write_comment(line, comment)
       return if line >= OrigenSim::NUMBER_OF_COMMENT_LINES
@@ -864,6 +869,8 @@ module OrigenSim
       @simulation_open = false
       simulation.error_count = error_count
       Origen.listeners_for(:simulation_shutdown).each(&:simulation_shutdown)
+      sync_up
+      simulation.ended = true
       end_simulation
       # Give the simulator time to shut down
       sleep 0.1 while simulation.running?
@@ -973,6 +980,23 @@ module OrigenSim
       peek("#{testbench_top}.pins.match_errors").to_i
     end
 
+    def peek_str(signal)
+      val = tester.simulator.peek(signal)
+      unless val.nil?
+        puts val
+        puts val.class
+        # All zeros seems to be what an empty string is returned from the VPI,
+        # Otherwise, break the string up into 8-bit chunks and decode the ASCII>
+        val = (val.to_s == 'b00000000' ? '' : val.to_s[1..-1].scan(/.{1,8}/).collect { |char| char.to_i(2).chr }.join)
+      end
+      val
+      # puts "Peaking #{signal}: #{a}: #{a.class}"
+      # tester.simulator.peek(signal).to_s[1..-1].scan(/.{1,8}/).collect { |char| char.to_i(2).chr }.join
+    end
+    alias_method :str_peek, :peek_str
+    alias_method :peek_string, :peek_str
+    alias_method :string_peek, :peek_str
+
     private
 
     # Pre 0.8.0 the simulator represented the time in ns instead of ps

data/lib/origen_sim/tester.rb

@@ -225,6 +225,10 @@ module OrigenSim
       flush if Origen.running_interactively? && dut_version > '0.12.1'
     end
 
+    # def method_missing(m, *args, &block)
+    #  super
+    # end
+
     private
 
     def flush_comments

data/lib/origen_sim.rb

@@ -19,6 +19,44 @@ module OrigenSim
   autoload :Tester, 'origen_sim/tester'
   autoload :Generator, 'origen_sim/generator'
 
+  # Include a mapping for various sematics.
+  INIT_PIN_STATE_MAPPING = {
+    # Drive Low Options
+    'drive_lo'       => 0,
+    'drive-lo'       => 0,
+    'drive_low'      => 0,
+    'drive-low'      => 0,
+    'lo'             => 0,
+    'low'            => 0,
+    '0'              => 0,
+
+    # Drive High Options
+    'drive_hi'       => 1,
+    'drive-hi'       => 1,
+    'drive_high'     => 1,
+    'drive-high'     => 1,
+    'hi'             => 1,
+    'high'           => 1,
+    '1'              => 1,
+
+    # High Impedance Options
+    'z'              => 2,
+    'high_z'         => 2,
+    'high-z'         => 2,
+    'hi_z'           => 2,
+    'hi-z'           => 2,
+    'high_impedance' => 2,
+    'high-impedance' => 2,
+    '2'              => 2,
+
+    # Disable Options
+    '-1'             => -1,
+    'disable'        => -1,
+    'disabled'       => -1,
+    'no_action'      => -1,
+    'no-action'      => -1
+  }
+
   def self.__instantiate_simulator__
     @simulator ||= Simulator.new
   end
@@ -145,5 +183,23 @@ module OrigenSim
   def self.error(message)
     simulator.error(message)
   end
+
+  def self.run(name, options = {}, &block)
+    # Load up the application and target
+    Origen.load_application
+    Origen.app.load_target!
+
+    # Start up the simulator and run whatever's in the target block.
+    # After the block completes, shutdown the simulator
+    tester.simulator.setup_simulation(name)
+    yield
+    tester.simulator.complete_simulation(name)
+  end
+
+  def self.run_source(source, options = {})
+    OrigenSim.run(source) do
+      OrigenTesters::Decompiler.decompile(source).execute
+    end
+  end
 end
 OrigenSim.__instantiate_simulator__

data/lib/origen_sim_dev/dut.rb

@@ -72,6 +72,9 @@ module OrigenSimDev
         reg.bits 6..4, :b5
         reg.bits 2..0, :b6
       end
+
+      sub_block :ip1, class_name: 'IP'
+      sub_block :ip2, class_name: 'IP'
     end
 
     def interactive_startup
@@ -98,12 +101,23 @@ module OrigenSimDev
     end
 
     def write_register(reg, options = {})
-      jtag.write_ir(0x8, size: 4)
-      dr.rg_enable.write(1)
-      dr.rg_read.write(0)
-      dr.rg_addr.write(reg.address)
-      dr.rg_data.write(reg.data)
-      jtag.write_dr(dr)
+      if reg.path =~ /ip(\d)/
+        ir_val = 0b0100 | Regexp.last_match(1).to_i
+        jtag.write_ir(ir_val, size: 4)
+        ip = reg.parent
+        ip.dr.bits(:write).write(1)
+        ip.dr.bits(:address).write(reg.address)
+        ip.dr.bits(:data).write(reg.data)
+        jtag.write_dr(ip.dr)
+      # Write to top-level reg
+      else
+        jtag.write_ir(0x8, size: 4)
+        dr.rg_enable.write(1)
+        dr.rg_read.write(0)
+        dr.rg_addr.write(reg.address)
+        dr.rg_data.write(reg.data)
+        jtag.write_dr(dr)
+      end
     end
 
     def read_register(reg, options = {})
@@ -119,14 +133,26 @@ module OrigenSimDev
         1.cycle
         dut.pins(:dout).dont_care
       else
-        jtag.write_ir(0x8, size: 4)
-        dr.rg_enable.write(1)
-        dr.rg_read.write(1)
-        dr.rg_addr.write(reg.address)
-        jtag.write_dr(dr)
-        dr.rg_enable.write(0)
-        dr.rg_data.copy_all(reg)
-        jtag.read_dr(dr)
+        if reg.path =~ /ip(\d)/
+          ir_val = 0b0100 | Regexp.last_match(1).to_i
+          jtag.write_ir(ir_val, size: 4)
+          ip = reg.parent
+          ip.dr.bits(:write).write(0)
+          ip.dr.bits(:address).write(reg.address)
+          ip.dr.bits(:data).write(0)
+          jtag.write_dr(ip.dr)
+          ip.dr.bits(:data).copy_all(reg)
+          jtag.read_dr(ip.dr)
+        else
+          jtag.write_ir(0x8, size: 4)
+          dr.rg_enable.write(1)
+          dr.rg_read.write(1)
+          dr.rg_addr.write(reg.address)
+          jtag.write_dr(dr)
+          dr.rg_enable.write(0)
+          dr.rg_data.copy_all(reg)
+          jtag.read_dr(dr)
+        end
       end
     end
   end

data/lib/origen_sim_dev/ip.rb

@@ -0,0 +1,53 @@
+module OrigenSimDev
+  class IP
+    include Origen::Model
+
+    def initialize
+      # Virtual reg to implement the JTAG scan chain
+      add_reg :dr, 0x0, size: 49 do |reg|
+        reg.bit 48, :write
+        reg.bits 47..32, :address
+        reg.bits 31..0, :data
+      end
+
+      # User regs
+      add_reg :cmd, 0x0
+
+      reg :status, 0x4 do |reg|
+        reg.bit 2, :error, access: :w1c
+        reg.bit 1, :fail, access: :w1c
+        reg.bit 0, :busy
+      end
+
+      add_reg :data, 0x8
+    end
+
+    def communication_test
+      ss "Communication test with #{name}"
+      data.write!(0x1234)
+      data.read!
+      data.read!
+      data.write!(0x5555_AAAA)
+      data.read!
+    end
+
+    def execute_cmd(code)
+      ss "Execute command #{code}"
+      # Verify that no command is currently running
+      status.read!(0)
+
+      cmd.write!(code)
+      10.cycles
+      # Verify that the command has started
+
+      status.busy.read!(1)
+
+      # Wait for the command to complete, a 'command' lasts for
+      # 1000 cycles times the command code
+      (code * 1000).cycles
+
+      # Verify that the command completed and passed
+      status.read!(0)
+    end
+  end
+end

data/pattern/ip1_test.rb

@@ -0,0 +1,9 @@
+Pattern.create do
+
+  dut.ip1.communication_test
+
+  dut.ip1.execute_cmd(1)
+
+  dut.ip1.execute_cmd(50)
+
+end

data/pattern/ip2_test.rb

@@ -0,0 +1,8 @@
+Pattern.create do
+
+  dut.ip2.communication_test
+
+  dut.ip2.execute_cmd(10)
+  dut.ip2.execute_cmd(10)
+  dut.ip2.execute_cmd(10)
+end

data/templates/rtl_v/origen.v.erb

@@ -11,6 +11,12 @@
 //
 // 0 - Force data 0
 // 1 - Force data 1
+//
+// Parameter init_drive
+// 0 - Initialize drive and assign to 0
+// 1 - Initialize drive and assign to 1
+// 2 - Don't initialize drive and assign to Z (default)
+// -1 - Don't initialize drive or assign. Pin will be left unknown
 module pin_driver(error, pin, sync, match_loop);
   parameter init_drive = 2; // Which means don't drive initially, set to 0 or 1 to drive
   parameter pin_name = "undefined_name";
@@ -33,7 +39,9 @@ module pin_driver(error, pin, sync, match_loop);
   wire drive_data = force_data[0] ? 0 : (force_data[1] ? 1 : data[0]);
   wire contention = drive ? (pin !== drive_data ? 1 : 0) : 0;
 
-  assign pin = drive ? drive_data : 1'bz;
+  if (init_drive != -1) begin
+    assign pin = drive ? drive_data : 1'bz;
+  end
 
   // Debug signal to show the expected data in the waves
   wire expect_data = compare ? data[0] : 1'bz;
@@ -113,14 +121,43 @@ module pin_drivers(errors, <%= dut.rtl_pins.map { |n, p, o| "#{p.id}_o" }.join('
   end
 
 % dut.rtl_pins.each do |name, pin, options|
-  pin_driver #(.init_drive(<%= pin.driving? ? "#{pin.value}" : '2' %>), .pin_name("<%= pin.id %>")) <%= pin.id %>(.pin(<%= pin.id %>_o), .error(<%= pin.id %>_err), .sync(sync), .match_loop(match_loop));
+  pin_driver #(<%= pin.meta[:origen_sim_init_pin_state].nil? ? '' : ".init_drive(#{pin.meta[:origen_sim_init_pin_state]}), "%>.pin_name("<%= pin.id %>")) <%= pin.id %>(.pin(<%= pin.id %>_o), .error(<%= pin.id %>_err), .sync(sync), .match_loop(match_loop));
 % end
 
+
 endmodule
 
+// Placeholder for user notes. This will be an empty module if no notes were given
+module user_details;
+  parameter _AVAILABLE_DETAILS_ = "<%= options[:user_details].empty? ? "" : options[:user_details].keys.join(',') %>";
+
+% options[:user_details].each do |name, note|
+  parameter <%= name %> = "<%= note %>";
+% end
+endmodule
 
-module debug(errors);
 
+// SnapshotDetails module. Just stores some traceability details into the snapshot
+// that can be queried by OrigenSim or viewed in the waveform viewer.
+module snapshot_details;
+  // Add a parameter that lists the available parameters. OrigenSim can use this known parameter to query any others that are
+  // added here.
+  parameter _AVAILABLE_DETAILS_ = "ORIGEN_SIM_VERSION,COMPILATION_TIME_STAMP,COMPILATION_PATH,DEVICE_NAME,REVISION,REVISION_NOTE,TESTBENCH_VERSION,AUTHOR";
+  
+  parameter ORIGEN_SIM_VERSION = "<%= OrigenSim::VERSION %>";
+  parameter COMPILATION_TIME_STAMP = "<%= Time.now %>";
+  parameter COMPILATION_PATH = "<%= Dir.pwd %>";
+  parameter DEVICE_NAME = "<%= options[:device_name] || 'No --device_name specified' %>";
+  parameter REVISION = "<%= options[:revision] || 'No --revision specified' %>";
+  parameter REVISION_NOTE = "<%= options[:revision_note] || 'No --revision_note specified' %>";
+  parameter TESTBENCH_VERSION = "<%= options[:parent_tb_version] || 'No --testbench_version specified' %>";
+  parameter AUTHOR = "<%= options[:author] || Origen.current_user.username %>";
+  
+  user_details user_details();
+
+endmodule
+
+module debug(errors);
   input [31:0] errors;
 
   reg [1023:0] pattern = 0;
@@ -130,6 +167,8 @@ module debug(errors);
 
   reg handshake;
 
+  snapshot_details snapshot_details();
+  
 endmodule
 
 module origen;
@@ -157,14 +196,17 @@ module origen;
 % dut.ground_pins.each do |name, pin, options|
     .<%= pin.id %>(<%= pin.id %>),
 % end
+% # Keep track of the primary groups seen.
+% seen_groups = []
 % dut.rtl_pins.each_with_index do |(name, pin, options), i|
 %   if options[:group]
-%     if pin.group_index == 0
+%     unless seen_groups.include?(pin.primary_group)
     .<%= pin.primary_group.id %>({
 %       pin.primary_group.each_with_index do |pin, i|
       <%= pin.id %><%= i == (pin.primary_group.size - 1) ? '' : ',' %>
 %       end
     })<%= i == (dut.rtl_pins.size - 1) ? '' : ',' %>
+%       seen_groups << pin.primary_group
 %     end
 %   else
     .<%= pin.rtl_name %>(<%= pin.id %>)<%= i == (dut.rtl_pins.size - 1) ? '' : ',' %>

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_sim
 version: !ruby/object:Gem::Version
-  version: 0.14.0
+  version: 0.15.0
 platform: ruby
 authors:
 - Stephen McGinty
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2018-11-27 00:00:00.000000000 Z
+date: 2019-02-11 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.35.0
+        version: 0.41.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.35.0
+        version: 0.41.0
 - !ruby/object:Gem::Dependency
   name: origen_testers
   requirement: !ruby/object:Gem::Requirement
@@ -44,14 +44,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.5.1
+        version: 0.5.2
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.5.1
+        version: 0.5.2
 description: 
 email:
 - stephen.f.mcginty@gmail.com
@@ -75,7 +75,6 @@ files:
 - ext/origen.h
 - ext/vpi_user.h
 - lib/origen_sim.rb
-- lib/origen_sim/artifacts.rb
 - lib/origen_sim/commands/build.rb
 - lib/origen_sim/commands/ci.rb
 - lib/origen_sim/commands/co.rb
@@ -89,11 +88,17 @@ files:
 - lib/origen_sim/origen_testers/api.rb
 - lib/origen_sim/simulation.rb
 - lib/origen_sim/simulator.rb
+- lib/origen_sim/simulator/artifacts.rb
+- lib/origen_sim/simulator/snapshot_details.rb
+- lib/origen_sim/simulator/user_details.rb
 - lib/origen_sim/stderr_reader.rb
 - lib/origen_sim/stdout_reader.rb
 - lib/origen_sim/tester.rb
 - lib/origen_sim_dev/dut.rb
+- lib/origen_sim_dev/ip.rb
 - lib/tasks/origen_sim.rake
+- pattern/ip1_test.rb
+- pattern/ip2_test.rb
 - pattern/test.rb
 - pattern/test2.rb
 - program/p1.rb
@@ -138,7 +143,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
       version: 1.8.11
 requirements: []
 rubyforge_project: 
-rubygems_version: 2.7.6
+rubygems_version: 2.7.7
 signing_key: 
 specification_version: 4
 summary: Plugin that provides a testbench environment to simulate Origen test patterns