origen_sim 0.13.0 → 0.14.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
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+  data.tar.gz: 8f6582388d383142beebaf1c313936b78b6f495f0b2403193df02f8ae51f25f0
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+  data.tar.gz: 8a968093af5c18778e2835115f02c46ec3f638b1a5049124c9fe339dbe9007eb4f8a80aac3146a0e377aee0bcb920f147c54bf092b2721ccefd587614fee0fb6

data/config/version.rb

@@ -1,6 +1,6 @@
 module OrigenSim
   MAJOR = 0
-  MINOR = 13
+  MINOR = 14
   BUGFIX = 0
   DEV = nil
 

data/ext/bridge.c

@@ -222,7 +222,7 @@ static void bridge_enable_drive_wave(Pin * pin) {
 
 
 static void bridge_disable_drive_wave(Pin * pin) {
-  Wave *wave = &compare_waves[(*pin).drive_wave];
+  Wave *wave = &drive_waves[(*pin).drive_wave];
 
   if ((*wave).active_pin_count == 0) {
     vpi_printf("Wanted to disable drive on pin %i, but its drive wave has no active pins!\n", (*pin).index);
@@ -352,7 +352,9 @@ static void bridge_compare_pin(char * index, char * val) {
     if ((*pin).previous_state != 2) {
       bridge_enable_compare_wave(pin);
       if ((*pin).previous_state == 1) {
-        bridge_disable_drive_wave(pin);
+        if (!bridge_is_drive_whole_cycle(pin)) {
+          bridge_disable_drive_wave(pin);
+        }
       }
       (*pin).previous_state = 2;
     }

data/lib/origen_sim.rb

@@ -36,7 +36,7 @@ module OrigenSim
     Tester.new(options.merge(vendor: :cadence), &block)
   end
 
-  def self.synopsys(optoins = {}, &block)
+  def self.synopsys(options = {}, &block)
     Tester.new(options.merge(vendor: :synopsys), &block)
   end
 

data/lib/origen_sim/commands/build.rb

@@ -141,7 +141,7 @@ else
   puts "  #{output_directory}/client.c \\"
   puts '  -CFLAGS "-std=c99" \\'
   puts '  +vpi \\'
-  puts "  -use_vpiobj #{output_directory}/origen.c \\"
+  puts "  #{output_directory}/origen.c \\"
   puts '  +define+ORIGEN_VPD=1 \\'
   puts '  -debug_access+all \\'
   puts '  -PP \\'
@@ -149,7 +149,7 @@ else
   puts
   puts 'Here is an example which may work for the file you just parsed (add additional -incdir options at the end if required):'
   puts
-  puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} #{output_directory}/origen.v #{output_directory}/bridge.c #{output_directory}/client.c -CFLAGS \"-std=c99\" +vpi -use_vpiobj #{output_directory}/origen.c -timescale=1ns/1ns  +define+ORIGEN_VPD=1 +incdir+#{Pathname.new(rtl_top).dirname} -debug_access+all -PP"
+  puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} #{output_directory}/origen.v #{output_directory}/bridge.c #{output_directory}/client.c -CFLAGS \"-std=c99\" +vpi #{output_directory}/origen.c -timescale=1ns/1ns  +define+ORIGEN_VPD=1 +incdir+#{Pathname.new(rtl_top).dirname} -debug_access+all -PP"
   puts
   puts 'Copy the following files (produced by vcs) to simulation/<target>/synopsys/. within your Origen application:'
   puts
@@ -186,7 +186,7 @@ else
   puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
   puts
   puts "  #{output_directory}/origen.v \\"
-  puts "  #{output_directory}/brdige.c \\"
+  puts "  #{output_directory}/bridge.c \\"
   puts "  #{output_directory}/client.c \\"
   puts '  -CFLAGS "-std=c99" \\'
   puts '  +vpi \\'

data/templates/rtl_v/origen.v.erb

@@ -11,12 +11,14 @@
 //
 // 0 - Force data 0
 // 1 - Force data 1
-module pin_driver(error, pin, sync);
+module pin_driver(error, pin, sync, match_loop);
   parameter init_drive = 2; // Which means don't drive initially, set to 0 or 1 to drive
+  parameter pin_name = "undefined_name";
 
   output reg error;
   inout pin;
   input sync;
+  input match_loop;
 
   reg [1:0] data = 0;
   reg [1:0] force_data = 0;
@@ -29,6 +31,7 @@ module pin_driver(error, pin, sync);
   reg [127:0] sync_memory = 0;
 
   wire drive_data = force_data[0] ? 0 : (force_data[1] ? 1 : data[0]);
+  wire contention = drive ? (pin !== drive_data ? 1 : 0) : 0;
 
   assign pin = drive ? drive_data : 1'bz;
 
@@ -39,6 +42,19 @@ module pin_driver(error, pin, sync);
     error = (compare && !capture) ? (pin == data[0] ? 0 : 1) : 0;
   end
 
+  // pin compare failure logger
+  always @(posedge error) begin
+    if (match_loop != 1) begin
+      $display("OrigenSim Error: miscompare on pin %s, expected %d received %d at %t", pin_name, data[0], pin, $time);
+    end
+  end
+  
+  // SMcG - needs more work, causes non-genuine fails in OrigenSim test case
+  //// pin contention logger
+  //always @(posedge contention) begin
+  //  $display("OrigenSim Error: contention on pin %s, tester drives %d beginning at %t", pin_name, drive_data, $time);
+  //end
+
   always @(posedge capture) begin
     if (sync == 1) begin
       sync_memory[127:1] <= sync_memory[126:0];
@@ -52,6 +68,8 @@ module pin_driver(error, pin, sync);
   end
 
   initial begin
+    // Set the timescale to ns (-9) with 0 decimal place precision, 20 chars
+    $timeformat(-9, 0, " ns", 20);
     if (init_drive == 1) begin
       drive = 1;
       data[0] = 1;
@@ -95,7 +113,7 @@ module pin_drivers(errors, <%= dut.rtl_pins.map { |n, p, o| "#{p.id}_o" }.join('
   end
 
 % dut.rtl_pins.each do |name, pin, options|
-  pin_driver <%= pin.driving? ? "#(#{pin.value}) " : '' %><%= pin.id %>(.pin(<%= pin.id %>_o), .error(<%= pin.id %>_err), .sync(sync));
+  pin_driver #(.init_drive(<%= pin.driving? ? "#{pin.value}" : '2' %>), .pin_name("<%= pin.id %>")) <%= pin.id %>(.pin(<%= pin.id %>_o), .error(<%= pin.id %>_err), .sync(sync), .match_loop(match_loop));
 % end
 
 endmodule

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_sim
 version: !ruby/object:Gem::Version
-  version: 0.13.0
+  version: 0.14.0
 platform: ruby
 authors:
 - Stephen McGinty
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2018-10-04 00:00:00.000000000 Z
+date: 2018-11-27 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen
@@ -44,14 +44,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: '0.5'
+        version: 0.5.1
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: '0.5'
+        version: 0.5.1
 description: 
 email:
 - stephen.f.mcginty@gmail.com
@@ -138,7 +138,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
       version: 1.8.11
 requirements: []
 rubyforge_project: 
-rubygems_version: 2.7.7
+rubygems_version: 2.7.6
 signing_key: 
 specification_version: 4
 summary: Plugin that provides a testbench environment to simulate Origen test patterns