origen_nexus 0.8.0

checksums.yaml

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+---
+SHA1:
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+  data.tar.gz: 7b47b5560e5e2d9c9e2617bcbfd5325a0436aee5
+SHA512:
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data/config/application.rb

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+class OrigenNexusApplication < Origen::Application
+
+  # This file contains examples of some of the most common configuration options,
+  # to see a real production example from a large application have a look at:
+  # sync://sync-15088:15088/Projects/common_tester_blocks/blocks/C90TFS_NVM_tester/tool_data/origen_v2/config/application.rb
+
+  # This information is used in headers and email templates, set it specific
+  # to your application
+  config.name     = "Origen Nexus"
+  config.initials = "OrigenNexus"
+  config.rc_url   = "git@github.com:Origen-SDK/origen_nexus.git"
+  config.release_externally = true
+
+  config.web_directory = "git@github.com:Origen-SDK/Origen-SDK.github.io.git/nexus"
+  config.web_domain = "http://origen-sdk.org/nexus"
+
+  # You can map moo numbers to targets here, this allows targets to be selected via
+  # origen t <moo>
+  #config.production_targets = {
+  #  "1m79x" => "production",
+  #}
+  
+  # Set up lint test
+  config.lint_test = {
+    # Require the lint tests to pass before allowing a release to proceed
+    :run_on_tag => true,
+    # Auto correct violations where possible whenever 'origen lint' is run
+    :auto_correct => true,
+    # Limit the testing for large legacy applications
+    #:level => :easy,
+    # Run on these directories/files by default
+    #:files => ["lib", "config/application.rb"],
+  }
+
+  # Versioning is based on a timestamp by default, if you would rather use semantic
+  # versioning, i.e. v1.0.0 format, then set this to true.
+  # In parallel go and edit config/version.rb to enable the semantic version code.
+  config.semantically_version = true
+
+  # An example of how to set application specific LSF parameters
+  #config.lsf.project = "msg.te"
+  
+  # An exmaple of how to specify a prefix to add to all generated patterns
+  #config.pattern_prefix = "nvm"
+
+  # An example of how to add header comments to all generated patterns
+  #config.pattern_header do
+  #  cc "This is a pattern created by the example origen application"
+  #end
+
+  # By default all generated output will end up in ./output.
+  # Here you can specify an alternative directory entirely, or make it dynamic such that
+  # the output ends up in a setup specific directory. 
+  #config.output_directory do
+  #  "#{Origen.root}/output/#{$dut.class}"
+  #end
+
+  # Similary for the reference files, generally you want to setup the reference directory
+  # structure to mirror that of your output directory structure.
+  #config.reference_directory do
+  #  "#{Origen.root}/.ref/#{$dut.class}"
+  #end
+
+  # Run code coverage when deploying the web site
+  def before_deploy_site
+    Dir.chdir Origen.root do
+      system "origen examples -c"
+      system "origen specs -c"
+      dir = "#{Origen.root}/web/output/coverage"
+      FileUtils.remove_dir(dir, true) if File.exists?(dir)
+      system "mv #{Origen.root}/coverage #{dir}"
+    end
+  end
+
+  # To automatically deploy your documentation after every tag use this code
+  def after_release_email(tag, note, type, selector, options)
+    command = "origen web compile --remote --api"
+    Dir.chdir Origen.root do
+      system command
+    end
+  end
+
+=begin
+  # To enabled source-less pattern generation create a class (for example PatternDispatcher)
+  # to generate the pattern. This should return false if the requested pattern has been
+  # dispatched, otherwise Origen will proceed with looking up a pattern source as normal.
+  #def before_pattern_lookup(requested_pattern)
+  #  PatternDispatcher.new.dispatch_or_return(requested_pattern)
+  #end
+
+  # If you use pattern iterators you may come accross the case where you request a pattern
+  # like this:
+  #   origen g example_pat_b0.atp
+  #
+  # However it cannot be found by Origen since the pattern name is actually example_pat_bx.atp
+  # In the case where the pattern cannot be found Origen will pass the name to this translator
+  # if it exists, and here you can make any substitutions to help Origen find the file you 
+  # want. In this example any instances of _b\d, where \d means a number, are replaced by
+  # _bx.
+  #config.pattern_name_translator do |name|
+  #  name.gsub(/_b\d/, "_bx")
+  #end
+
+  # If you want to use pattern iterators, that is the ability to generate multiple pattern
+  # variants from a single source file, then you can define the required behavior here.
+  # The examples below implement some of the iterators that were available in Origen 1,
+  # you can remove them if you don't want to use them, or of course modify or add new 
+  # iterators specific to your application logic.
+  
+  # By setting iterator
+  config.pattern_iterator do |iterator|
+    # Define a key that you will use to enable this in a pattern, here the iterator
+    # can be enabled like this: Pattern.create(:by_setting => [1,2,3]) do
+    iterator.key = :by_setting
+
+    # The value passed from the pattern via the key comes in here as the first
+    # argument, the name applied here can be anything, but settings seem reasonable since
+    # an array of setting values is expected.
+    # The last argument &pattern is mandatory and represents the pattern block (the bit contained
+    # within Pattern.create do ... end)
+    iterator.loop do |settings, &pattern|
+      # Implement the loop however you like, here we loop for each value in the array
+      settings.each do |setting|
+        # Now call the pattern passing in the setting argument, this would be captured
+        # in the pattern like this:
+        #   Pattern.create do |setting|
+        pattern.call(setting)
+      end
+    end
+
+    # Each pattern iteration needs a unique name, otherwise Origen will simply overwrite 
+    # the same output file each time.
+    # The base pattern name and the pattern argument, in this case the setting, will be
+    # passed in here and whatever is returned is what will be used as the name.
+    iterator.pattern_name do |name, setting|
+      # Substitute _x in the name with the setting, _1, _2, etc.
+      name.gsub("_x", "_#{setting}")
+    end
+  end
+=end
+
+end

data/config/commands.rb

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+# This file should be used to extend the origen command line tool with tasks 
+# specific to your application.
+# The comments below should help to get started and you can also refer to
+# lib/origen/commands.rb in your Origen core workspace for more examples and 
+# inspiration.
+#
+# Also see the official docs on adding commands:
+#   http://origen.freescale.net/origen/latest/guides/custom/commands/
+
+# Map any command aliases here, for example to allow origen -x to refer to a 
+# command called execute you would add a reference as shown below: 
+aliases ={
+#  "-x" => "execute",
+}
+
+# The requested command is passed in here as @command, this checks it against
+# the above alias table and should not be removed.
+@command = aliases[@command] || @command
+
+# Now branch to the specific task code
+case @command
+
+# Here is an example of how to implement a command, the logic can go straight
+# in here or you can require an external file if preferred.
+#when "execute"
+#  puts "Executing something..."
+#  require "commands/execute"    # Would load file lib/commands/execute.rb
+#  # You must always exit upon successfully capturing a command to prevent 
+#  # control flowing back to Origen
+#  e it 0
+when "specs"
+  require "rspec"
+  exit RSpec::Core::Runner.run(['spec'])
+
+when "examples", "test"
+  Origen.load_application
+  status = 0
+
+  # Pattern generator tests
+  # (btw, %w() is ruby shorthand for making an array of strings)
+   ARGV = %w(regression.list -t debug_RH1 -r approved)
+   load "#{Origen.top}/lib/origen/commands/generate.rb"
+   ARGV = %w(regression.list -t debug_RL1 -r approved)
+   load "#{Origen.top}/lib/origen/commands/generate.rb"
+   ARGV = %w(regression.list -t debug_RH4 -r approved)
+   load "#{Origen.top}/lib/origen/commands/generate.rb"
+   ARGV = %w(regression.list -t debug_RL4 -r approved)
+   load "#{Origen.top}/lib/origen/commands/generate.rb"
+
+  # check if nothing changed or nothing added
+  if Origen.app.stats.changed_files == 0 && 
+     Origen.app.stats.new_files == 0 &&
+     Origen.app.stats.changed_patterns == 0 &&
+     Origen.app.stats.new_patterns == 0
+ 
+    # report examples having passed
+    Origen.app.stats.report_pass
+  else
+    # report examples having failed
+    Origen.app.stats.report_fail
+    status = 1
+  end
+  puts
+  if @command == "test"
+    Origen.app.unload_target!
+    require "rspec"
+    result = RSpec::Core::Runner.run(['spec'])
+    status = status == 1 ? 1 : result
+  end
+  exit status
+
+# Always leave an else clause to allow control to fall back through to the
+# Origen command handler.
+# You probably want to also add the command details to the help shown via
+# origen -h, you can do this be assigning the required text to @application_commands
+# before handing control back to Origen. Un-comment the example below to get started.
+else
+  @application_commands = <<-EOT
+ specs         Run the specs (tests), -c will enable coverage
+ examples      Run the examples (tests), -c will enable coverage
+ test          Run both specs and examples, -c will enable coverage
+  EOT
+
+end 

data/config/development.rb

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+# This file is similar to environment.rb and will be loaded
+# automatically at the start of each invocation of Origen.
+#
+# However the major difference is that it will not be loaded
+# if the application is imported by a 3rd party app - in that
+# case only environment.rb is loaded.
+#
+# Therefore this file should be used to load anything you need
+# to setup a development environment for this app, normally
+# this would be used to define some dummy classes to instantiate
+# your objects so that they can be tested and/or interacted with
+# in the console.
+module OrigenNexus
+  autoload :DUT,            "origen_nexus/dut"
+  autoload :DUTWithJTAG,    "origen_nexus/dut"
+end

data/config/environment.rb

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+# This file will be required by Origen before your target is loaded, you 
+# can use this to require all of your files, which is the easiest way
+# to get started. As your experience grows you may wish to require only the
+# minimum files required to allow the target to be initialized and let 
+# each class require its own dependencies.
+#
+# It is recommended that you keep all of your application logic in lib/
+# The lib directory has already been added to the search path and so any files
+# in there can be referenced from here with a relative path.
+#
+# Note that pattern files do not need to be referenced from here and these
+# will be located automatically by origen.
+
+# This says load the file "lib/pioneer.rb" the first time anyone makes a 
+# reference to the class name 'Pioneer'.
+#autoload :Pioneer,   "pioneer"
+# This is generally preferable to using require which will load the file
+# regardless of whether it is needed by the current target or not:
+#require "pioneer"
+# Sometimes you have to use require however:-
+#   1. When defining a test program interface:
+#require "interfaces/j750"
+#   2. If you want to extend a class defined by an imported application, in
+#      this case your must use required and supply a full path (to distinguish
+#      it from the one in the parent application):
+#require "#{Origen.root}/c90_top_level/p2"
+
+require 'origen_nexus'
+module OrigenNexus
+  autoload :Driver, 'origen_nexus/driver'
+end
+

data/config/version.rb

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+module OrigenNexus
+  MAJOR = 0
+  MINOR = 8
+  BUGFIX = 0
+  DEV = nil
+
+  VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
+end

data/lib/origen_nexus.rb

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+require 'origen'
+require_relative '../config/application.rb'
+require_relative '../config/environment.rb'
+require 'origen_jtag' # required for runtime dep gems
+
+module OrigenNexus
+  # Returns an instance of the Nexus::Driver
+  def nexus
+    @nexus ||= Driver.new(self)
+  end
+end

data/lib/origen_nexus/driver.rb

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+module OrigenNexus
+  class Driver
+    # Include JTAG driver instance to fall back on (if owner doesn't have)
+    include OrigenJTAG
+
+    # Allow for JTAG optionality
+    # blank for now
+    JTAG_CONFIG = {}
+
+    # Include registers as Nexus has its own registers
+    include Origen::Registers
+
+    alias_method :local_jtag, :jtag
+
+    # Returns the underlying JTAG driver.  If the owner has its own JTAG driver
+    # then this will be returned, otherwise it will be a fall back driver included
+    # by the Nexus module.
+    def jtag
+      owner.respond_to?(:jtag) ? owner.jtag : local_jtag
+    end
+
+    # Returns the object that included the Nexus module,
+    # should always be the top-level model
+    attr_reader :owner
+
+    # OnCE Command Register (OCMD) width in bits
+    # OnCE (On-Chip Emulation)
+    attr_reader :once_ocmd_width
+
+    # The OnCE Nexus access instruction (NEXUS-ACCESS)
+    # OnCE command value to enable Nexus
+    attr_reader :once_nexus_access_instr
+
+    # The OnCE bypass instruction (BYPASS)
+    # OnCE command value to bypass OnCE
+    attr_reader :once_bypass_instr
+
+    # Nexus command width
+    # width of commands used in first DR pass to read/write
+    # a Nexus register
+    attr_reader :nexus_command_width
+
+    attr_reader :cpuscr_reg_width
+
+    attr_reader :once_cpuscr_go_exit_instr
+
+    def initialize(owner, options = {})
+      if defined?(owner.class::NEXUS_CONFIG)
+        options = owner.class::NEXUS_CONFIG.merge(options)
+      end
+
+      # Fallback defaults
+      options = {
+        tclk_format:               :rh,                      # format of JTAG clock used:  ReturnHigh (:rh), ReturnLo (:rl)
+        tclk_multiple:             1,                      # number of cycles for one clock pulse, assumes 50% duty cycle. Uses tester non-return format to spread TCK across multiple cycles.
+        #    e.g. @tclk_multiple = 2, @tclk_format = :rh, means one cycle with Tck low (non-return), one with Tck high (NR)
+        #         @tclk_multiple = 4, @tclk_format = :rl, means 2 cycles with Tck high (NR), 2 with Tck low (NR)
+        tdo_strobe:                :tclk_high,                # when using multiple cycles for TCK, which state of TCK to strobe for TDO, :tclk_high or :tclk_low or :tclk_all
+        tdo_store_cycle:           0,                    # store vector cycle within TCK (i.e. when to indicate to tester to store vector within TCK cycle.  0 is first vector, 1 is second, etc.)
+        #
+        once_ocmd_width:           10,                   # Width of OnCE OCMD instruction reg in bits
+        once_nexus_access_instr:   0b0001111100, # Instruction used to access nexus via OnCE, default: 0x07C.
+        once_bypass_instr:         0b0001111111,       # Instruction used to bypass OnCE, default: 0x07F.
+        once_cpuscr_go_exit_instr: 0b0110010000,  # Instruction used to exit debug mode and kick off code execution from desired address.
+        nexus_command_width:       8,                # Width of Nexus command data regs, default: 8.
+        cpuscr_reg_width:          192,              # Width of cpuscr reg
+      }.merge(options)
+
+      # Define JTAG configs based on Nexus config
+      JTAG_CONFIG[:tclk_format] = options[:tclk_format]
+      JTAG_CONFIG[:tclk_multiple] = options[:tclk_multiple]
+      JTAG_CONFIG[:tdo_strobe] = options[:tdo_strobe]
+      JTAG_CONFIG[:tdo_store_cycle] = options[:tdo_store_cycle]
+
+      @once_ocmd_width = options[:once_ocmd_width]
+      @once_nexus_access_instr = options[:once_nexus_access_instr]
+      @once_bypass_instr = options[:once_bypass_instr]
+      @once_cpuscr_go_exit_instr = options[:once_cpuscr_go_exit_instr]
+      @nexus_command_width = options[:nexus_command_width]
+      @cpuscr_reg_width = options[:cpuscr_reg_width]
+
+      # Define nexus registers
+      define_nexus_registers
+
+      # Define CPU registers
+      define_cpu_registers
+
+      @owner = owner
+    end
+
+    def on_created
+    end
+
+    # This proxies all pin requests from our local JTAG driver to
+    # our parent DUT model
+    def pin(*args)
+      owner.pin(*args)
+    end
+    alias_method :pins, :pin
+
+    # Define Nexus registers
+    # For now only those related to RWA will be defined.
+    # RWA (read/write access) provides DMA-like access to memory-mapped resources on
+    # the AHB system bus either while the processor is halted or during runtime.
+    def define_nexus_registers
+      # Each register has a Nexus Opcode, which we will use as 'address' below, and
+      #  corresponding read addresses and write addresses
+
+      # RWCS - Read/Write Access Control Register
+      #        read addr = 0x0E, write addr = 0x0F
+      reg :rwcs, 0x0E, size: 32 do
+        bit 31,     :ac
+        bit 30,     :rw
+        bit 29..27, :sz
+        bit 26..24, :map
+        bit 23..22, :pr
+        bit 15..2,  :cnt
+        bit 1,      :err, writable: false
+        bit 0,      :dv, writable: false
+      end
+
+      # RWD - Read/Write Access Data
+      #       read addr = 0x12, write addr = 0x13
+      reg :rwa, 0x12, size: 32 do
+        bit 31..0, :addr
+      end
+
+      # RWD - Read/Write Access Data
+      #       read addr = 0x14, write addr = 0x15
+      reg :rwd, 0x14, size: 32 do
+        bit 31..0, :data
+      end
+    end
+
+    def define_cpu_registers
+      reg :cpuscr, 0x0, size: 192 do
+        bit 191..160, :ctl
+        bit 159..128, :ir
+        bit 127..96,  :pc
+        bit 95..64,   :msr
+        bit 63..32,   :wbbrh
+        bit 31..0,    :wbbrl
+      end
+    end
+
+    # Enable Nexus module
+    # Loads NEXUS-ACCESS instruction into JTAG Instruction
+    # Register (OnCE OCMD register).
+    # repeated calls will not generate vectors if the instruction
+    # is already loaded
+    #
+    # Optionally also accepts a block to allow temporary Nexus access
+    #
+    #   nexus.enable_nexus_access do
+    #      # Do something with nexus enabled
+    #   end
+    #   # Nexus access disabled
+    #
+    def enable_nexus_access
+      if @ir_reg_value != once_nexus_access_instr
+        jtag.write_ir once_nexus_access_instr, size: once_ocmd_width, msg: log2("Enable Nexus Access: OnCE_Send(#{once_ocmd_width}, 0x%02X)" % [once_nexus_access_instr])
+        @ir_reg_value = once_nexus_access_instr
+      end
+      if block_given?
+        yield
+        disable_once
+      end  # whether to mark all bits in RWD for read
+    end
+
+    # Disable OnCE
+    def disable_once
+      if @ir_reg_value != once_bypass_instr
+        jtag.write_ir once_bypass_instr, size: once_ocmd_width, msg: log2("Bypass OnCE: OnCE_Send(#{once_ocmd_width}, 0x%02X)" % [once_bypass_instr])
+        @ir_reg_value = once_bypass_instr
+      end
+    end
+
+    def go_exit(code_start_address = 0x4)
+      jtag.write_ir once_cpuscr_go_exit_instr, size: once_ocmd_width, msg: log2('Enabling CPUSCR register for read/write access')
+      regs(:cpuscr).bit(:wbbrl).write(0x00000000)
+      regs(:cpuscr).bit(:wbbrh).write(0x00000000)
+      regs(:cpuscr).bit(:msr).write(0x00000000)
+      regs(:cpuscr).bit(:pc).write(code_start_address - 4)
+      regs(:cpuscr).bit(:ir).write(0x7c0004ac)
+      regs(:cpuscr).bit(:ctl).write(0x00000000)
+      jtag.write_dr regs(:cpuscr).value, size: cpuscr_reg_width, msg: log2('Writing GO+EXIT to CPUSCR')
+    end
+
+    # Write a given Nexus register
+    def write_nexus_register(reg_or_val, options = {})
+      options = { write:    true,        # whether to write or read
+                  overlay:  false,
+                  care_out: false
+                }.merge(options)
+      addr = exact_address(reg_or_val, options)
+      addr += 1 if options[:write] # offset address by 1 since writing
+      data = exact_data(reg_or_val, options)
+      size = exact_size(reg_or_val, options)
+      name = exact_name(reg_or_val, options)
+
+      if options[:write]
+        log "Write Nexus Reg: #{name.upcase} at 0x%04X with 0x%08X" % [addr, data]
+      else
+        log "Read Nexus Reg: #{name.upcase} at 0x%04X with 0x%08X" % [addr, data]
+      end
+
+      # first pass : select register via nexus command
+      jtag.write_dr addr, size: nexus_command_width, msg: log2("OnCE_Send(#{nexus_command_width}, 0x%02X)" % [addr])
+      if options[:overlay] == true
+        # if we want to overlay expect values, then
+        #   put dummy data in vectors to force them to be uncompressable by pattern generator.
+        reg_or_val.data = 0x55555555
+        data = exact_data(reg_or_val, options)
+      end
+
+      if options[:capture]
+        reg(reg_or_val.name).store
+      end
+
+      if options[:write]
+        # second pass : pass data to register
+        jtag.write_dr reg_or_val, overlay: options[:overlay], overlay_label: options[:overlay_label], size: size, msg: log2("OnCE_Send(#{size}, 0x%08X)" % [data])
+      else
+        if options[:care_output]
+          reg(reg_or_val.name).read
+        end
+        # second pass : read data from register
+        jtag.read_dr(reg_or_val, overlay: options[:overlay], overlay_label: options[:overlay_label], size: size, msg: log2("OnCE_Read(#{size}, 0x%08X)" % [data]))
+      end
+    end
+
+    # Read a given Nexus register
+    def read_nexus_register(reg_or_val, options = {})
+      write_nexus_register(reg_or_val, options.merge(write: false))
+    end
+
+    # Write data cycles only for a Register
+    # Used if only want data cycles for overlay subroutines
+    def write_data_only(reg_or_val, options = {})
+      options = { write: true,        # whether to write or read
+                }.merge(options)
+
+      data = exact_data(reg_or_val, options)
+
+      # Size of RWD register being used for output
+      size = reg(:rwd).size
+
+      # if reading a real register then need to handle copying over all data and flags
+      # undefined regs will be handled in lower function so that default is to treat
+      # as undefined reg (just simple accesses)
+      reg(:rwd).overlay(nil)  # clear overlay flags if there, as sticky
+      if real_reg?(reg_or_val)
+        reg(:rwd).copy_all(reg_or_val)
+      end
+
+      if options[:write]
+        # Send command to write RWD reg
+        # Send data value to be written to RWD reg
+        reg(:rwd).write(data)
+
+        jtag.shift(reg(:rwd), options.merge(size: size, cycle_last: true, includes_last_bit: true))
+
+      else
+        # Mark all bits for read
+        reg(:rwd).read
+
+        jtag.shift(reg(:rwd), options.merge(size: size, read: true, cycle_last: true, includes_last_bit: true))
+
+      end
+
+      # Clear flags so as to not affect subsequent reg reads/writes
+      reg(:rwd).clear_flags
+      reg_or_val.clear_flags if reg_or_val.respond_to?(:clear_flags)
+    end
+
+    # Read data cycles only for RWD Register
+    def read_data_only(reg_or_val, options = {})
+      write_data_only(reg_or_val, options.merge(write: false))
+    end
+
+    # Single Write to memory-mapped resource
+    # for now only supports 32-bit data
+    def single_write_access(address, data, options = {})
+      options = { write:      true,          # whether to write or read the register
+                  undef:      true,          # whether IPS being accessed is a register or undefined
+                  count:      1,             # by default use single address access mode
+                  overlay:    false,                         # default: assume not a real register
+                  nexus_init: true,
+                  width:      32,      # default write width to 32 bits
+              }.merge(options)
+      if options[:width] == 8
+        write_width = 0b0
+      elsif options[:width] == 16
+        write_width = 0b1
+      elsif  options[:width] == 32
+        write_width = 0b10
+      elsif  options[:width] == 64
+        write_width = 0b11
+      else
+        Origen.log.warn 'Nexus 3 width supplied is invalid, defaulting to 32 bit width.'
+      end
+
+      if options[:nexus_init]
+        enable_nexus_access
+      end
+      # Send command to write RWA reg
+      # Send address value to RWA reg
+      reg(:rwa).write(address)
+      write_nexus_register(reg(:rwa))
+
+      # Send command to write RWCS reg
+      # Send settings to RWCS
+      reg(:rwcs).bits(:ac).write(1)
+      reg(:rwcs).bits(:rw).write(options[:write] ? 1 : 0)
+      reg(:rwcs).bits(:sz).write(write_width)                 # write_width, defaul value = 32 bits.
+      reg(:rwcs).bits(:map).write(0b000)                # map select = primary
+      reg(:rwcs).bits(:pr).write(0b11)                  # priority = highest
+      reg(:rwcs).bits(:cnt).write(options[:count])      # single access
+      reg(:rwcs).bits(:err).write(0)                    # read/write access error
+      reg(:rwcs).bits(:dv).write(0)                     # read/write access data valid
+      write_nexus_register(reg(:rwcs))
+
+      if options[:write]
+        # Send command to write RWD reg
+        # Send data value to be written to RWD reg
+        reg(:rwd).write(data)
+        write_nexus_register(reg(:rwd), options.reject { |x| x == :address })
+      else
+        # If undefined reg, then mark all bits for read
+        if options[:undef]
+          reg(:rwd).read
+        end
+        # Send command to read RWD reg
+        # Read RWD reg value
+        reg(:rwd).write(data)
+        read_nexus_register(reg(:rwd), options.reject { |x| x == :address })
+      end
+    end
+
+    # Single Read from memory-mapped resource
+    # for now only supports 32-bit data
+    def single_read_access(address, data, options = {})
+      single_write_access(address, data, options.merge(write: false))
+    end
+
+    # Block Write to memory-mapped resources
+    # for now only supports 32-bit data
+    #
+    # address = address at start of block
+    # block_data = array of 32-bit values of block data to write
+    def block_write_access(address, block_data = [], options = {})
+      options = { write: true,          # whether to write or read the block
+                  width: 32       # width default to 32 bits
+              }.merge(options)
+      block_data.each_index do |i|
+        if i == 0                                  # first do single write access with count > 1
+          single_write_access(address, block_data[0], options.merge(count: block_data.count))
+          if options[:width] > 32
+            reg(:rwd).write(block_data[i = i + 1])
+            if options[:write]
+              write_nexus_register(reg(:rwd), options)
+            else
+              read_nexus_register(reg(:rwd), options)
+            end
+          end
+        else
+          next if i.odd? && options[:width] > 32
+          reg(:rwd).write(block_data[i])
+          if options[:write]
+            write_nexus_register(reg(:rwd), options)
+          else
+            read_nexus_register(reg(:rwd), options)
+          end
+          if options[:width] > 32
+            reg(:rwd).write(block_data[i = i + 1])
+            if options[:write]
+              write_nexus_register(reg(:rwd), options)
+            else
+              read_nexus_register(reg(:rwd), options)
+            end
+          end
+        end
+      end
+    end
+
+    # Block Read of memory-mapped resources
+    # for now only supports 32-bit data
+    #
+    # address = address at start of block
+    # block_data = array of 32-bit values of block data to read
+    def block_read_access(address, block_data = [], options = {})
+      block_write_access(address, block_data, options.merge(write: false))
+    end
+
+    #    def test_read_flag(reg_to_check)
+    #      reg_to_check.size.times do |i|
+    #        if reg_to_check.bit(i).is_to_be_read?
+    #          print "\t\tBIT #{i} of #{reg_to_check.name.upcase} has read flag!\n"
+    #        else
+    #          print "\t\tBIT #{i} of #{reg_to_check.name.upcase} DOES NOT HAVE read flag!\n"
+    #        end
+    #      end
+    #    end
+    #
+    #    def test_store_flag(reg_to_check)
+    #      reg_to_check.size.times do |i|
+    #        if reg_to_check.bit(i).is_to_be_stored?
+    #          print "\t\tBIT #{i} of #{reg_to_check.name.upcase} has store flag!\n"
+    #        else
+    #          print "\t\tBIT #{i} of #{reg_to_check.name.upcase} DOES NOT HAVE store flag!\n"
+    #        end
+    #      end
+    #    end
+    #
+    #    def test_overlay_flag(reg_to_check, options={})
+    #      options={:msg => ""}.merge(options)
+    #      reg_to_check.size.times do |i|
+    #        if reg_to_check.bit(i).has_overlay?
+    #          print "\t\t#{options[:msg]}: BIT #{i} of #{reg_to_check.name.upcase} has overlay flag!\n"
+    #        else
+    #          print "\t\t#{options[:msg]}: BIT #{i} of #{reg_to_check.name.upcase} DOES NOT HAVE overlay flag!\n"
+    #        end
+    #      end
+
+    # determines whether real register or not
+    def real_reg?(reg_or_val)
+      reg_or_val.respond_to?(:name)
+    end
+
+    # Write the given register (or system memory location) or given value to a specified address
+    # reg_or_val          := register symbol to use -- assumes register preloaded with
+    #                        required data to use, can override by using :address option
+    #                        in which case data to use provided here
+    #
+    # options[:address]   := address to write to.  This is mandatory in the case of the
+    #                        reg_or_val argument being a value (for data), if it is a
+    #                        Register object then this is optional and if present then
+    #                        will override the register's address.
+    #
+    def write_register(reg_or_val, options = {})
+      options = { write:   true,    # whether to write or read the register
+                  overlay: false
+              }.merge(options)
+      address = exact_address(reg_or_val, options)
+      data = exact_data(reg_or_val, options)
+      size = exact_size(reg_or_val, options)
+      name = (exact_name(reg_or_val, options)).upcase
+
+      op = options[:write] ? 'Write' : 'Read'
+
+      # Set undefined register flag to override option for simple_write_access below
+      options[:undef] = !real_reg?(reg_or_val)
+
+      # if reading a real register then need to handle copying over all data and flags
+      # undefined regs will be handled in lower function so that default is to treat
+      # as undefined reg (just simple accesses)
+      reg(:rwd).overlay(nil)  # clear overlay flags if there, as sticky
+      if real_reg?(reg_or_val)
+        reg(:rwd).copy_all(reg_or_val)
+      end
+
+      cc "**************************** NEXUS REGISTER #{op.upcase} BEGIN ****************************"
+      cc "- #{op} Register #{name}: addr: 0x%08X, data: 0x%08X\n" % [address, data]
+      single_write_access(address, data, options)
+      cc "**************************** NEXUS REGISTER #{op.upcase} END ****************************"
+
+      # Clear flags so as to not affect subsequent reg reads/writes
+      reg(:rwd).clear_flags
+      reg_or_val.clear_flags if reg_or_val.respond_to?(:clear_flags)
+    end
+    alias_method :write, :write_register
+
+    # Read the given register (or system memory location) or given value from a specified address
+    # reg_or_val          := register symbol to use -- assumes register preloaded with
+    #                        required data to use, can override by using :address option
+    #                        in which case data to use provided here
+    #
+    # options[:address]   := address to read from.  This is mandatory in the case of the
+    #                        reg_or_val argument being a value (for data), if it is a
+    #                        Register object then this is optional and if present then
+    #                        will override the register's address.
+    #
+    def read_register(reg_or_val, options = {})
+      write_register(reg_or_val, options.merge(write: false))
+    end
+    alias_method :read, :read_register
+
+    # Provides exact address value either if a defined register is
+    # provided or if an address is provided
+    def exact_address(reg_or_val, options = {})
+      address = options[:addr] || options[:address]
+      unless address
+        # if no address provided as option then use register address
+        if real_reg?(reg_or_val)             # if real register
+          address = reg_or_val.address       # use register address
+        else
+          fail "An :address option must be supplied when not providing a register to Nexus!\n"
+        end
+      end
+      address
+    end
+
+    # Provides exact data value either if a defined register is
+    # provided or if an address is provided
+    def exact_data(reg_or_val, _options = {})
+      # if no data provided as option then use register data
+      if real_reg?(reg_or_val)             # if real register
+        data = reg_or_val.data             # use register value
+      else
+        data = reg_or_val                  # use reg_or_val passed as data
+      end
+      data
+    end
+
+    # Provide size of register if real register passed--
+    #  otherwise indicate number of bits of data value
+    def exact_size(reg_or_val, _options = {})
+      if real_reg?(reg_or_val)             # if real register
+        size = reg_or_val.size             # use register size
+      else
+        size = reg_or_val.to_s(2).size     # get number of bits in value
+      end
+      size
+    end
+
+    # Provide name of register, if real register passed
+    # otherwise given 'undef' as name
+    def exact_name(reg_or_val, _options = {})
+      if real_reg?(reg_or_val)             # if real register
+        name = reg_or_val.name             # use register name
+      else
+        name = 'undef'                     # undefined register
+      end
+      name
+    end
+
+    def log2(msg)
+      "Nexus::Driver - #{msg}"
+    end
+
+    def log(msg)
+      cc "#{log2(msg)}"
+    end
+  end
+end