origen_link 0.1.0.pre0 → 0.1.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/bin/start_link_server +20 -0
- data/config/application.rb +0 -0
- data/config/boot.rb +3 -2
- data/config/commands.rb +0 -0
- data/config/version.rb +1 -1
- data/lib/origen_link.rb +1 -15
- data/lib/origen_link/callback_handlers.rb +13 -0
- data/lib/origen_link/server/jtag.rb +180 -0
- data/lib/origen_link/server/pin.rb +125 -0
- data/lib/origen_link/server/sequencer.rb +353 -0
- data/lib/origen_link/{includes_vector_based.rb → server_com.rb} +32 -7
- data/lib/origen_link/test/top_level.rb +48 -0
- data/lib/origen_link/test/top_level_controller.rb +44 -0
- data/lib/origen_link/test/vector_based.rb +25 -0
- data/lib/origen_link/vector_based.rb +254 -53
- data/lib/tasks/origen_link.rake +0 -0
- data/pattern/example.rb +0 -0
- data/pattern/jtag_100_operations.rb +0 -0
- data/pattern/jtag_comm_fail_test.rb +0 -0
- data/pattern/jtag_comm_test.rb +0 -0
- data/templates/web/index.md.erb +0 -0
- data/templates/web/layouts/_basic.html.erb +0 -0
- data/templates/web/partials/_navbar.html.erb +0 -0
- data/templates/web/release_notes.md.erb +0 -0
- metadata +32 -18
- data/lib/origen_link/test/regression_tests.rb +0 -68
- data/lib/origen_link/test/test_dut.rb +0 -46
- data/lib/origen_link/test/test_dut_controller.rb +0 -42
- data/lib/origen_link/test/vector_based_redefs.rb +0 -17
- data/lib/origen_link_server/LinkSequencer.rb +0 -333
- data/lib/origen_link_server/LinkTCPServer.rb +0 -45
- data/lib/origen_link_server/jtag_interface.rb +0 -177
- data/lib/origen_link_server/pin_interface.rb +0 -134
- data/lib/origen_link_server/test/test_Sequencer.rb +0 -51
@@ -1,45 +0,0 @@
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# rubocop:disable Style/FileName: Use snake_case for source file names.
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require 'socket'
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require_relative 'LinkSequencer'
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server = TCPServer.open('192.168.0.2', 12_777)
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puts 'server started'
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pinsequencer = OrigenLinkSequencer.new
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# time measurements for debug only
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# total_receive_time=0
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# total_process_time=0
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# total_xmit_time=0
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# total_close_time=0
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# total_packets=0
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loop do
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client = server.accept
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# time measurements for debug only
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# t1 = Time.now
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message = client.gets
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# t2 = Time.now
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# process the message
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# for now only pin_ messages are accepted
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response = pinsequencer.processmessage(message.chomp)
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# t3 = Time.now
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client.puts(response)
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# t4 = Time.now
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client.close
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# t5 = Time.now
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# puts "packet process time: #{t3-t2}"
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# total_receive_time += (t2-t1)
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# total_process_time += (t3-t2)
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# total_xmit_time += (t4-t3)
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# total_close_time += (t5-t4)
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# total_packets += 1
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# puts "total receive time: #{total_receive_time}"
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# puts "total process time: #{total_process_time}"
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# puts "total xmit time: #{total_xmit_time}"
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# puts "total close time: #{total_close_time}"
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# puts ''
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# puts "total receive time: #{total_receive_time/total_packets}"
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# puts "total process time: #{total_process_time/total_packets}"
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# puts "total xmit time: #{total_xmit_time/total_packets}"
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# puts "total close time: #{total_close_time/total_packets}"
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end
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@@ -1,177 +0,0 @@
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# rubocop:disable Style/For: Prefer each over for.
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require_relative 'pin_interface'
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class OrigenLinkJtag
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attr_reader :tdoval
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attr_accessor :verbose_enable
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attr_accessor :anytdofail
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def initialize(tdiio = 16, tdoio = 23, tmsio = 19, tckio = 26, tck_period = 0.000001)
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@tdipin = OrigenLinkPin.new(tdiio, :out_low)
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@tdopin = OrigenLinkPin.new(tdoio, :in)
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@tmspin = OrigenLinkPin.new(tmsio, :out_low)
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@tckpin = OrigenLinkPin.new(tckio, :out_low)
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@tck_half_period = tck_period / 2
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@tdoval = 0
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@tdostr = ''
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@verbose_enable = true
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@anytdofail = false
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end
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def tck_period=(value)
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@tck_half_period = value / 2
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end
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def destroy
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@tdipin.destroy
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@tdopin.destroy
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@tmspin.destroy
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@tckpin.destroy
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@tdipin = nil
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@tdopin = nil
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@tmspin = nil
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@tckpin = nil
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end
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def do_cycle(tdival, tmsval, capturetdo = false)
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@tdipin.out(tdival)
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@tmspin.out(tmsval)
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sleep @tck_half_period
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@tckpin.out(1)
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sleep @tck_half_period
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if capturetdo
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@tdostr = @tdopin.in + @tdostr
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end
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@tckpin.out(0)
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end
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def do_tlr
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for step in 1..8 do do_cycle(0, 1) end
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do_cycle(0, 0)
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end
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def do_shift(numbits, value, capturetdo = false, suppresscomments = false, tdocompare = '')
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@tdoval = 0
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@tdostr = ''
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for bit in 0..numbits - 2 do
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do_cycle(value[bit], 0, capturetdo)
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end
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do_cycle(value[numbits - 1], 1, capturetdo)
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@tdoval = @tdostr.to_i(2) if capturetdo
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if !(suppresscomments) && @verbose_enable && capturetdo
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puts 'TDO output = 0x' + @tdoval.to_s(16)
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end
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if capturetdo && tdocompare != ''
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thiscomparefail = false
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for bit in 0..numbits - 1 do
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if tdocompare[numbits - 1 - bit] == 'H'
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compareval = 1
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elsif tdocompare[numbits - 1 - bit] == 'L'
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compareval = 0
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else
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compareval = @tdoval[bit]
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end
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if @tdoval[bit] != compareval
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@anytdofail = true
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thiscomparefail = true
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end
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end
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tdovalstr = @tdoval.to_s(2)
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tdovalstr = '0' * (numbits - tdovalstr.length) + tdovalstr
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if thiscomparefail
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puts '****************************>>>>>>>>>>>>>>>>> TDO failure <<<<<<<<<<<<<<<<<<****************************'
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puts 'expected: ' + tdocompare
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puts 'received: ' + tdovalstr
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else
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puts 'TDO compare pass'
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puts 'expected: ' + tdocompare
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puts 'received: ' + tdovalstr
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end
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end
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end
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def do_ir(numbits, value, options = {})
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defaults = {
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capturetdo: false,
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suppresscomments: false,
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tdocompare: ''
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}
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options = defaults.merge(options)
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if !(options[:suppresscomments]) && @verbose_enable
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puts " shift IR, #{numbits} bits, value = 0x" + value.to_s(16)
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end
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if options[:tdocompare] != ''
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capturetdo = true
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else
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capturetdo = options[:capturetdo]
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end
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# Assume starting from run test idle
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# Advance to shift IR
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do_cycle(0, 1)
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do_cycle(0, 1)
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do_cycle(0, 0)
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do_cycle(0, 0)
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do_shift(numbits, value, capturetdo, options[:suppresscomments], options[:tdocompare])
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# Return to run test idle
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do_cycle(0, 1)
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do_cycle(0, 0)
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end
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def do_dr(numbits, value, options = {})
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defaults = {
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capturetdo: true,
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suppresscomments: false,
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tdocompare: ''
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}
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options = defaults.merge(options)
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if !(options[:suppresscomments]) && @verbose_enable
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puts " shift DR, #{numbits} bits, value = 0x" + value.to_s(16)
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end
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if options[:tdocompare] != ''
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capturetdo = true
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else
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capturetdo = options[:tdocompare]
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end
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# Assume starting from run test idle
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# Advance to shift DR
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do_cycle(0, 1)
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do_cycle(0, 0)
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do_cycle(0, 0)
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do_shift(numbits, value, capturetdo, options[:suppresscomments], options[:tdocompare])
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# Return to run test idle
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do_cycle(0, 1)
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do_cycle(0, 0)
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end
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def pause_dr
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do_cycle(0, 1)
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do_cycle(0, 0)
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do_cycle(0, 0)
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do_cycle(0, 1)
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do_cycle(0, 0)
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do_cycle(0, 1)
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do_cycle(0, 1)
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do_cycle(0, 0)
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end
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def pause_ir
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do_cycle(0, 1)
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pause_dr
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end
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end
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@@ -1,134 +0,0 @@
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# OrigenLinkPin class manipulate input/output pins of the Udoo
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# using exported file objects. If the pin is not exported, it
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# will be exported when a pin is initialized
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#
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# initialize:
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# description - This method will execute system command
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# "sudo echo ionumber > /sys/class/gpio/export"
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# to create the IO file interface. It will
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# set the direction, initial pin state and initialize
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# instance variables
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# ionumber - required, value indicating the pin number (BCM IO number,
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# not the header pin number)
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# direction - optional, specifies the pin direction. A pin is
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# initialized as an input if a direction isn't specified.
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#
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#
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# out:
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# description - Sets the output state of the pin. If the pin
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# is setup as an input, the direction will first
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# be changed to output.
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#
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#
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# in:
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# description - Reads and returns state of the pin. If the pin
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# is setup as an output, the direction will first
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# be changed to input.
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#
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#
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# update_direction:
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# description - Sets the pin direction
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#
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# direction - specifies the pin direction. A pin is
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# initialized as an input if a direction isn't specified.
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#
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# Valid direction values:
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# :in - input
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# :out - output
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# :out_high - output, initialized high
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# :out_low - output, initialized low
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class OrigenLinkPin
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@@pin_setup = {
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in: 'in',
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out: 'out',
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out_high: 'high',
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out_low: 'low'
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}
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attr_reader :gpio_valid
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def initialize(ionumber, direction = :in)
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@ionumber = Integer(ionumber)
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@pin_dir_name = "/sys/class/gpio/gpio#{@ionumber}/direction"
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@pin_val_name = "/sys/class/gpio/gpio#{@ionumber}/value"
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if notFile.exist?(@pin_dir_name)
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system("echo #{@ionumber} > /sys/class/gpio/export")
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sleep 0.05
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if $CHILD_STATUS == 0
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@gpio_valid = true
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else
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@gpio_valid = false
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end
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else
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@gpio_valid = true
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end
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if @gpio_valid
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if File.writable?(@pin_dir_name)
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@pin_dir_obj = File.open(@pin_dir_name, 'w')
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update_direction(direction)
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else
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@gpio_valid = false
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puts "#{@pin_dir_name} is not writable. Fix permissions or run as super user."
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end
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@pin_val_obj = File.open(@pin_val_name, 'r+') if @gpio_valid
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end
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end
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def destroy
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if @gpio_valid
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@pin_dir_obj.close
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@pin_val_obj.close
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system("echo #{@ionumber} > /sys/class/gpio/unexport")
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puts "pin #{@ionumber} is no longer exported"
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end
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end
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def out(value)
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if @gpio_valid
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if @direction == :in
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if value == 1
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update_direction(:out_high)
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else
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update_direction(:out_low)
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end
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end
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@pin_val_obj.write(value)
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@pin_val_obj.flush
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end
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end
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# rubocop:disable Style/EmptyElse: Redundant else-clause.
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def in
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if @gpio_valid
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if @direction == :out
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update_direction(:in)
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end
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# below is original read - slow to reopen every time
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# File.open(@pin_val_name, 'r') do |file|
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# file.read#.chomp
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# end
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# end original read
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@pin_val_obj.pos = 0
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@pin_val_obj.getc
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else
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nil
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end
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end
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def update_direction(direction)
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if @gpio_valid
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@pin_dir_obj.pos = 0
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@pin_dir_obj.write(@@pin_setup[direction])
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@pin_dir_obj.flush
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if direction == :in
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@direction = direction
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else
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@direction = :out
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end
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128
|
-
end
|
129
|
-
end
|
130
|
-
|
131
|
-
def to_s
|
132
|
-
'OrigenLinkPin' + @ionumber.to_s
|
133
|
-
end
|
134
|
-
end
|
@@ -1,51 +0,0 @@
|
|
1
|
-
# rubocop:disable Style/FileName: Use snake_case for source file names.
|
2
|
-
require_relative '../LinkSequencer'
|
3
|
-
require 'test/unit'
|
4
|
-
|
5
|
-
class TestLinkSequencer < Test::Unit::TestCase
|
6
|
-
def test_pinmap
|
7
|
-
test_obj = OrigenLinkSequencer.new
|
8
|
-
assert_equal('P:', test_obj.processmessage('pin_assign:tck,23'))
|
9
|
-
assert_equal('OrigenLinkPin23', test_obj.pinmap['tck'].to_s)
|
10
|
-
assert_equal('F:pin tdo gpio1900 is invalid', test_obj.processmessage('pin_assign:tdo,1900'))
|
11
|
-
assert_equal('P:', test_obj.processmessage('pin_assign:tck,23'))
|
12
|
-
assert_equal('OrigenLinkPin23', test_obj.pinmap['tck'].to_s)
|
13
|
-
assert_equal(-1, test_obj.pinmap['tdo'])
|
14
|
-
end
|
15
|
-
|
16
|
-
def test_pinorder
|
17
|
-
test_obj2 = OrigenLinkSequencer.new
|
18
|
-
assert_equal('P:', test_obj2.processmessage('pin_patternorder:tdi,tdo,tms'))
|
19
|
-
assert_equal(%w(tdi tdo tms), test_obj2.patternorder)
|
20
|
-
assert_equal({ 'tdi' => 0, 'tdo' => 1, 'tms' => 2 }, test_obj2.patternpinindex)
|
21
|
-
assert_equal([%w(tdi tdo tms), [], []], test_obj2.cycletiming[0]['timing'])
|
22
|
-
end
|
23
|
-
|
24
|
-
def test_clear
|
25
|
-
end
|
26
|
-
|
27
|
-
def test_pinformat_timing
|
28
|
-
test_obj3 = OrigenLinkSequencer.new
|
29
|
-
assert_equal('P:', test_obj3.processmessage('pin_format:1,tck,rl'))
|
30
|
-
assert_equal(['tck'], test_obj3.cycletiming[1]['rl'])
|
31
|
-
assert_equal(nil, test_obj3.cycletiming[1]['rh'])
|
32
|
-
|
33
|
-
assert_equal('P:', test_obj3.processmessage('pin_format:1,xtal,rh'))
|
34
|
-
assert_equal(nil, test_obj3.cycletiming[1]['rl'])
|
35
|
-
assert_equal(['xtal'], test_obj3.cycletiming[1]['rh'])
|
36
|
-
|
37
|
-
assert_equal('P:', test_obj3.processmessage('pin_format:2,tck,rl'))
|
38
|
-
assert_equal(['tck'], test_obj3.cycletiming[2]['rl'])
|
39
|
-
assert_equal(nil, test_obj3.cycletiming[2]['rh'])
|
40
|
-
assert_equal(nil, test_obj3.cycletiming[1]['rl'])
|
41
|
-
assert_equal(['xtal'], test_obj3.cycletiming[1]['rh'])
|
42
|
-
|
43
|
-
assert_equal('P:', test_obj3.processmessage('pin_timing:1,tdi,0,tms,1,tdo,2'))
|
44
|
-
assert_equal(['tck'], test_obj3.cycletiming[2]['rl'])
|
45
|
-
assert_equal(nil, test_obj3.cycletiming[2]['rh'])
|
46
|
-
assert_equal(nil, test_obj3.cycletiming[1]['rl'])
|
47
|
-
assert_equal(['xtal'], test_obj3.cycletiming[1]['rh'])
|
48
|
-
assert_equal([['tdi'], ['tms'], ['tdo']], test_obj3.cycletiming[1]['timing'])
|
49
|
-
assert_equal([[], [], []], test_obj3.cycletiming[2]['timing'])
|
50
|
-
end
|
51
|
-
end
|