origen_jtag 0.21.1 → 0.22.2
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/config/version.rb +2 -3
- data/lib/origen_jtag/driver.rb +59 -46
- data/lib/origen_jtag/tap_controller.rb +70 -31
- data/lib/origen_jtag_dev/new_style.rb +2 -1
- data/pattern/full_reg_subr_overlay.rb +26 -0
- data/pattern/jtag_workout.rb +7 -1
- data/pattern/overlay_subr.rb +56 -0
- data/templates/web/index.md.erb +4 -4
- metadata +5 -4
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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-
metadata.gz:
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data.tar.gz:
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metadata.gz: cc6050891bc69e2a38991157a3423a8765284b257a56d68c2fb87a8b5844f98b
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data.tar.gz: 4e491ddb526412da9761cd1d5a6886a7a17a009e60ea2736db46365035cf94e2
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: dbb5ac9d278793a4994d8a50079bb587f326186701ed760edc119824b899cb29bb0551693d4d8f7f72e7eaff2fefc2c7fd2e6fd4f4563ed2049b208f63b6b8a6
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data.tar.gz: 93668e735cb0c23de2788bb6be7bb057a2e58a41bfff14a3a204de7c6a33f1ab6b2aaee427804869f62c9bf474fd888e6e82ab85ecf2b764a2f193c63db16f5d
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data/config/version.rb
CHANGED
data/lib/origen_jtag/driver.rb
CHANGED
@@ -35,7 +35,8 @@ module OrigenJTAG
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alias_method :tclk_format, :tck_format
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alias_method :tclk_format=, :tck_format=
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-
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attr_accessor :tdo_strobe
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attr_accessor :tdo_store_cycle
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# Set true to print out debug comments about all state transitions
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attr_accessor :verbose
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@@ -57,7 +58,7 @@ module OrigenJTAG
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end
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@cycle_callback = options[:cycle_callback]
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-
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@given_options = options.dup # Save these for later use in the pins method
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# Fallback defaults
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options = {
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@@ -211,7 +212,7 @@ module OrigenJTAG
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overlay_options = {}
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if tester.respond_to?(:source_memory) && !cycle_callback?
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if ovl_reg[i] && ovl_reg[i].has_overlay? && !Origen.mode.simulation?
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-
overlay_options[:pins] =
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+
overlay_options[:pins] = pins[:tdi]
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if global_ovl
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overlay_options[:overlay_str] = global_ovl
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else
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@@ -280,7 +281,7 @@ module OrigenJTAG
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overlay_options[:change_data] = false # data change only on first cycle if overlay
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end
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end
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-
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pins[:tdo].dont_care unless cycle_callback?
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else
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@deferred_compare = true
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@deferred_store = true if store_tdo_this_tck
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@@ -323,7 +324,7 @@ module OrigenJTAG
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# If TDO is already suspended (by an application) then don't do the
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# suspends below since the resume will clear the application's suspend
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tdo_already_suspended = !cycle_callback? &&
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tdo_already_suspended = !cycle_callback? && pins[:tdo].suspended? && !@tdo_suspended_by_driver
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@tck_multiple.times do |i|
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# 50% duty cycle if @tck_multiple is even, otherwise slightly off
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@@ -332,26 +333,26 @@ module OrigenJTAG
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if i < (@tck_multiple + 1) / 2
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# first half of cycle
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-
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pins[:tck].drive(@tck_vals ? @tck_vals[:on] : tck_val)
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unless tdo_already_suspended
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if mask_tdo_half0
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@tdo_suspended_by_driver = true
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-
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pins[:tdo].suspend
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else
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@tdo_suspended_by_driver = false
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-
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pins[:tdo].resume
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end
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end
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else
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# second half of cycle
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-
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pins[:tck].drive(@tck_vals ? @tck_vals[:off] : (1 - tck_val))
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unless tdo_already_suspended
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if mask_tdo_half1
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@tdo_suspended_by_driver = true
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-
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pins[:tdo].suspend
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else
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@tdo_suspended_by_driver = false
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-
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pins[:tdo].resume
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end
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end
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end
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@@ -359,7 +360,7 @@ module OrigenJTAG
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end
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if @tdo_suspended_by_driver
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@tdo_suspended_by_driver = false
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-
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pins[:tdo].resume
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end
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end
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end
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@@ -415,7 +416,7 @@ module OrigenJTAG
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cc "#{options[:msg]}\n"
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end
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val = reg_or_val.respond_to?(:data) ? reg_or_val.data : reg_or_val
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-
shift_dr(write: val.to_hex) do
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shift_dr(options.merge(write: val.to_hex)) do
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shift(reg_or_val, options)
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end
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end
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@@ -448,7 +449,7 @@ module OrigenJTAG
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if options[:msg]
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cc "#{options[:msg]}\n"
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end
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-
shift_dr(read: Origen::Utility.read_hex(reg_or_val)) do
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shift_dr(options.merge(read: Origen::Utility.read_hex(reg_or_val))) do
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shift(reg_or_val, options)
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end
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end
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@@ -475,19 +476,19 @@ module OrigenJTAG
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# a msg to be written out prior to shifting in IR data. Will not write comment only if write
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# occurs.
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def write_ir(reg_or_val, options = {})
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-
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-
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-
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-
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-
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-
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-
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-
shift_ir(write: val.to_hex) do
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val = reg_or_val.respond_to?(:data) ? reg_or_val.data : reg_or_val
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if val != ir_value || options[:force]
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if options[:msg]
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cc "#{options[:msg]}\n"
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end
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if Origen.tester.respond_to?(:write_ir)
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Origen.tester.write_ir(reg_or_val, options)
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else
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shift_ir(options.merge(write: val.to_hex)) do
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shift(reg_or_val, options)
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end
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-
@ir_value = val
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end
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@ir_value = val
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end
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end
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@@ -548,10 +549,10 @@ module OrigenJTAG
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if cycle_callback?
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@owner.send(@cycle_callback, @actions, options)
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else
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-
apply_action(
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-
apply_action(
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-
apply_action(
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-
tester.store_next_cycle(
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apply_action(pins[:tms], @actions[:tms])
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apply_action(pins[:tdi], @actions[:tdi])
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apply_action(pins[:tdo], @actions[:tdo])
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tester.store_next_cycle(pins[:tdo]) if @actions[:store]
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tester.cycle(options)
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end
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clear_actions
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@@ -665,30 +666,42 @@ module OrigenJTAG
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tdo
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end
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-
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-
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-
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-
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-
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-
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-
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-
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-
@pins
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-
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-
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-
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-
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+
def to_pin(pin_or_id)
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if pin_or_id
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if pin_or_id.is_a?(Symbol) || pin_or_id.is_a?(String)
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@owner.pin(pin_or_id)
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else
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pin_or_id
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end
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end
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end
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def pins
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@pins ||= begin
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pins = {}
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pins[:tck] = to_pin(@given_options[:tck_pin])
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pins[:tdi] = to_pin(@given_options[:tdi_pin])
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pins[:tdo] = to_pin(@given_options[:tdo_pin])
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pins[:tms] = to_pin(@given_options[:tms_pin])
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+
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# Support legacy implementation where tck was incorrectly called tclk, in case of both being
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# defined then :tck has priority
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pins[:tck] ||= @owner.pin(:tck) if @owner.has_pin?(:tck)
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pins[:tck] ||= @owner.pin(:tclk)
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pins[:tdi] ||= @owner.pin(:tdi)
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pins[:tdo] ||= @owner.pin(:tdo)
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pins[:tms] ||= @owner.pin(:tms)
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pins
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+
end
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rescue
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puts 'Missing JTAG pins!'
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puts "In order to use the JTAG driver your #{owner.class} class must either define"
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puts 'the following pins (an alias is fine):'
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puts REQUIRED_PINS
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puts '-- or --'
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-
puts 'Pass the
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-
puts "sub_block :jtag, class_name: 'OrigenJTAG::Driver', tck_pin:
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puts 'Pass the pin IDs to be used instead in the initialization options:'
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+
puts "sub_block :jtag, class_name: 'OrigenJTAG::Driver', tck_pin: :clk, tdi_pin: :gpio1, tdo_pin: :gpio2, tms_pin: :gpio3"
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raise 'JTAG driver error!'
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end
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end
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@@ -4,22 +4,22 @@ module OrigenJTAG
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module TAPController
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# Map of internal state symbols to human readable names
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6
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STATES = {
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7
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-
reset:
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8
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-
idle:
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-
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-
capture_dr:
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-
shift_dr:
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-
exit1_dr:
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-
pause_dr:
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-
exit2_dr:
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-
update_dr:
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-
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-
capture_ir:
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-
shift_ir:
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-
exit1_ir:
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-
pause_ir:
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-
exit2_ir:
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22
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-
update_ir:
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7
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+
reset: 'Test-Logic-Reset',
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+
idle: 'Run-Test/Idle',
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+
select_dr_scan: 'Select-DR-Scan',
|
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+
capture_dr: 'Capture-DR',
|
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+
shift_dr: 'Shift-DR',
|
12
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+
exit1_dr: 'Exit1-DR',
|
13
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+
pause_dr: 'Pause-DR',
|
14
|
+
exit2_dr: 'Exit2-DR',
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+
update_dr: 'Update-DR',
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+
select_ir_scan: 'Select-IR-Scan',
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+
capture_ir: 'Capture-IR',
|
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+
shift_ir: 'Shift-IR',
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19
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+
exit1_ir: 'Exit1-IR',
|
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+
pause_ir: 'Pause-IR',
|
21
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+
exit2_ir: 'Exit2-IR',
|
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+
update_ir: 'Update-IR'
|
23
23
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}
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24
24
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|
25
25
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# Returns the current state of the JTAG TAP Controller
|
@@ -50,11 +50,27 @@ module OrigenJTAG
|
|
50
50
|
# end
|
51
51
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# # State is Run-Test/Idle
|
52
52
|
def shift_dr(options = {})
|
53
|
-
|
53
|
+
options = {
|
54
|
+
start_state: :idle, # Allowed start states: :idle, :select_dr_scan, :update_ir, :update_dr
|
55
|
+
end_state: :idle # Allowed end states: :idle, :update_dr
|
56
|
+
}.merge(options)
|
57
|
+
|
58
|
+
if options[:start_state] == :idle # allow for pause_dr state also if called from pause_dr block
|
59
|
+
validate_state(:idle, :pause_dr)
|
60
|
+
elsif options[:state_state] == :select_dr_scan
|
61
|
+
validate_state(:select_dr_scan, :pause_dr)
|
62
|
+
elsif options[:state_state] == :update_dr
|
63
|
+
validate_state(:update_dr, :pause_dr)
|
64
|
+
elsif options[:state_state] == :update_ir
|
65
|
+
validate_state(:update_ir, :pause_dr)
|
66
|
+
end
|
54
67
|
log 'Transition to Shift-DR...'
|
55
|
-
if state == :idle
|
56
|
-
|
57
|
-
|
68
|
+
if state == :idle || state == :select_dr_scan || state == :update_ir || state == :update_dr
|
69
|
+
# Non-pause states
|
70
|
+
unless state == :select_dr_scan
|
71
|
+
tms!(1) # => Select-DR-Scan
|
72
|
+
update_state :select_dr_scan
|
73
|
+
end
|
58
74
|
tms!(0) # => Capture-DR
|
59
75
|
update_state :capture_dr
|
60
76
|
tms!(0) # => Shift-DR
|
@@ -78,8 +94,10 @@ module OrigenJTAG
|
|
78
94
|
end
|
79
95
|
tms!(1) # => Update-DR
|
80
96
|
update_state :update_dr
|
81
|
-
|
82
|
-
|
97
|
+
if options[:end_state] == :idle
|
98
|
+
tms!(0) # => Run-Test/Idle
|
99
|
+
update_state :idle
|
100
|
+
end
|
83
101
|
else # :pause_dr
|
84
102
|
tms!(1) # => Exit2-DR
|
85
103
|
update_state :exit2_dr
|
@@ -175,13 +193,23 @@ module OrigenJTAG
|
|
175
193
|
# end
|
176
194
|
# # State is Run-Test/Idle
|
177
195
|
def shift_ir(options = {})
|
178
|
-
|
196
|
+
options = {
|
197
|
+
start_state: :idle, # Allowed start states: :idle, :select_ir_scan
|
198
|
+
end_state: :idle # Allowed end states: :idle, :update_ir, :select_dr_scan
|
199
|
+
}.merge(options)
|
200
|
+
if options[:start_state] == :idle
|
201
|
+
validate_state(:idle, :pause_ir)
|
202
|
+
else
|
203
|
+
validate_state(:select_ir_scan, :pause_ir)
|
204
|
+
end
|
179
205
|
log 'Transition to Shift-IR...'
|
180
|
-
if state == :idle
|
181
|
-
|
182
|
-
|
183
|
-
|
184
|
-
|
206
|
+
if state == :idle || state == :select_ir_scan
|
207
|
+
unless state == :select_ir_scan
|
208
|
+
tms!(1) # => Select-DR-Scan
|
209
|
+
update_state :select_dr_scan
|
210
|
+
tms!(1) # => Select-IR-Scan
|
211
|
+
update_state :select_ir_scan
|
212
|
+
end
|
185
213
|
tms!(0) # => Capture-IR
|
186
214
|
update_state :capture_ir
|
187
215
|
tms!(0) # => Shift-IR
|
@@ -195,7 +223,13 @@ module OrigenJTAG
|
|
195
223
|
end
|
196
224
|
log msg, always: true do
|
197
225
|
yield
|
198
|
-
|
226
|
+
if options[:end_state] == :idle
|
227
|
+
log 'Transition to Run-Test/Idle...'
|
228
|
+
elsif options[:end_state] == :update_ir
|
229
|
+
log 'Transition to Update-IR...'
|
230
|
+
elsif options[:end_state] == :select_dr_scan
|
231
|
+
log 'Transition to Select-DR-Scan...'
|
232
|
+
end
|
199
233
|
if @last_data_vector_shifted
|
200
234
|
@last_data_vector_shifted = false
|
201
235
|
else
|
@@ -205,8 +239,13 @@ module OrigenJTAG
|
|
205
239
|
end
|
206
240
|
tms!(1) # => Update-IR
|
207
241
|
update_state :update_ir
|
208
|
-
|
209
|
-
|
242
|
+
if options[:end_state] == :idle
|
243
|
+
tms!(0) # => Run-Test/Idle
|
244
|
+
update_state :idle
|
245
|
+
elsif options[:end_state] == :select_dr_scan
|
246
|
+
tms!(1) # => Select-DR-Scan
|
247
|
+
update_state :select_dr_scan
|
248
|
+
end
|
210
249
|
else # :pause_ir
|
211
250
|
tms!(1) # => Exit2-IR
|
212
251
|
update_state :exit2_ir
|
@@ -30,7 +30,8 @@ module OrigenJTAGDev
|
|
30
30
|
instantiate_pins(options)
|
31
31
|
sub_block :jtag, { class_name: 'OrigenJTAG::Driver' }.merge(@jtag_config)
|
32
32
|
if options[:extra_port]
|
33
|
-
|
33
|
+
# Test supplying both pin IDs (recommended) and pin objects (legacy)
|
34
|
+
sub_block :jtag2, { class_name: 'OrigenJTAG::Driver', tck_pin: :tck_2, tdi_pin: :tdi_2, tdo_pin: pin(:tdo_2), tms_pin: pin(:tms_2) }.merge(@jtag_config)
|
34
35
|
end
|
35
36
|
end
|
36
37
|
|
@@ -0,0 +1,26 @@
|
|
1
|
+
Pattern.create do
|
2
|
+
def test(msg)
|
3
|
+
ss "Test - #{msg}"
|
4
|
+
end
|
5
|
+
|
6
|
+
jtag = $dut.jtag
|
7
|
+
reg16 = $dut.reg(:test16)
|
8
|
+
reg32 = $dut.reg(:test32)
|
9
|
+
|
10
|
+
|
11
|
+
test 'Shift register into TDI with overlay'
|
12
|
+
|
13
|
+
|
14
|
+
cc 'Full register (16 bits)'
|
15
|
+
reg16.overlay('write_overlay16')
|
16
|
+
reg16.write!
|
17
|
+
# tester.cycle # Give a padding cycle as a place for the subroutine call to go
|
18
|
+
# jtag.shift reg, cycle_last: true
|
19
|
+
|
20
|
+
cc 'Full register with additional size (32 bits)'
|
21
|
+
reg32.overlay('write_overlay32')
|
22
|
+
reg32.write!
|
23
|
+
# tester.cycle # Give a padding cycle as a place for the subroutine call to go
|
24
|
+
# jtag.shift reg, cycle_last: true, size: 32
|
25
|
+
|
26
|
+
end
|
data/pattern/jtag_workout.rb
CHANGED
@@ -193,7 +193,13 @@ Pattern.create(options = { name: pat_name }) do
|
|
193
193
|
|
194
194
|
test 'Unless forced'
|
195
195
|
jtag.write_ir 0xF, size: 4, force: true
|
196
|
-
|
196
|
+
|
197
|
+
test 'Write IR, starting with Idle, leave in Select-DR-Scan state'
|
198
|
+
jtag.write_ir(0x7, size: 8, end_state: :select_dr_scan, force: true)
|
199
|
+
|
200
|
+
test 'Write DR starting with Select-DR-Scan state, end with Idle'
|
201
|
+
jtag.write_dr(0x12345678, size: 32, start_state: :select_dr_scan)
|
202
|
+
|
197
203
|
test 'Reset'
|
198
204
|
jtag.reset
|
199
205
|
|
@@ -0,0 +1,56 @@
|
|
1
|
+
Pattern.create do
|
2
|
+
def test(msg)
|
3
|
+
ss "Test - #{msg}"
|
4
|
+
end
|
5
|
+
|
6
|
+
def subroutine(name, options = {})
|
7
|
+
options = {
|
8
|
+
compress: false,
|
9
|
+
}.merge(options)
|
10
|
+
|
11
|
+
tester.start_subroutine(name)
|
12
|
+
# $tester.set_timeset('intram', 40)
|
13
|
+
# $dut.init_pins_for_first_vector
|
14
|
+
# $dut.pin(:RESET_B).drive(1)
|
15
|
+
# $dut.pin(:JTAG_TRST_B).drive(1)
|
16
|
+
|
17
|
+
|
18
|
+
if options[:compress]
|
19
|
+
yield options
|
20
|
+
else
|
21
|
+
tester.dont_compress do
|
22
|
+
yield options
|
23
|
+
end
|
24
|
+
end
|
25
|
+
tester.end_subroutine(options)
|
26
|
+
end
|
27
|
+
def write_partial(thing_to_shift, options = {})
|
28
|
+
options = {
|
29
|
+
read: false,
|
30
|
+
length: false, # Set to the number of bits you want to shift when supplying a data value
|
31
|
+
includes_last_bit: false,
|
32
|
+
cycle_last: true
|
33
|
+
}.merge(options)
|
34
|
+
|
35
|
+
dut.jtag.shift thing_to_shift, size: options[:length], cycle_last: options[:cycle_last], includes_last_bit: options[:includes_last_bit], read: options[:read]
|
36
|
+
end
|
37
|
+
|
38
|
+
|
39
|
+
jtag = $dut.jtag
|
40
|
+
reg16 = $dut.reg(:test16)
|
41
|
+
reg32 = $dut.reg(:test32)
|
42
|
+
|
43
|
+
test 'Shift register into TDI with overlay'
|
44
|
+
|
45
|
+
subroutine 'write_overlay16' do
|
46
|
+
# write_partial(0, length: 16, includes_last_bit: true)
|
47
|
+
dut.jtag.shift 0, size: 16, cycle_last: true, includes_last_bit: true, read: false
|
48
|
+
end
|
49
|
+
|
50
|
+
subroutine 'write_overlay32' do
|
51
|
+
# write_partial(5, length: 32, includes_last_bit: true)
|
52
|
+
dut.jtag.shift 0, size: 32, cycle_last: true, includes_last_bit: false
|
53
|
+
end
|
54
|
+
|
55
|
+
|
56
|
+
end
|
data/templates/web/index.md.erb
CHANGED
@@ -89,10 +89,10 @@ class MyApp::MyDUT
|
|
89
89
|
tck_multiple: 2,
|
90
90
|
tdo_strobe: :tck_high,
|
91
91
|
tdo_store_cycle: 1,
|
92
|
-
tck_pin:
|
93
|
-
tdi_pin:
|
94
|
-
tdo_pin:
|
95
|
-
tms_pin:
|
92
|
+
tck_pin: :tck2,
|
93
|
+
tdi_pin: :tdi2,
|
94
|
+
tdo_pin: :tdo2,
|
95
|
+
tms_pin: :tms2
|
96
96
|
end
|
97
97
|
end
|
98
98
|
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: origen_jtag
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.
|
4
|
+
version: 0.22.2
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Stephen McGinty
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date:
|
11
|
+
date: 2022-04-28 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: origen
|
@@ -62,8 +62,10 @@ files:
|
|
62
62
|
- lib/origen_jtag_dev/serial.rb
|
63
63
|
- lib/origen_jtag_dev/top_level.rb
|
64
64
|
- pattern/full_reg_ovly_cap.rb
|
65
|
+
- pattern/full_reg_subr_overlay.rb
|
65
66
|
- pattern/global_label_test.rb
|
66
67
|
- pattern/jtag_workout.rb
|
68
|
+
- pattern/overlay_subr.rb
|
67
69
|
- pattern/rww_test.rb
|
68
70
|
- pattern/two_port.rb
|
69
71
|
- templates/web/index.md.erb
|
@@ -89,8 +91,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
|
|
89
91
|
- !ruby/object:Gem::Version
|
90
92
|
version: 1.8.11
|
91
93
|
requirements: []
|
92
|
-
|
93
|
-
rubygems_version: 2.7.7
|
94
|
+
rubygems_version: 3.1.4
|
94
95
|
signing_key:
|
95
96
|
specification_version: 4
|
96
97
|
summary: JTAG driver for the Origen SDK
|