origen_jtag 0.19.0 → 0.19.1

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@@ -1,221 +1,221 @@
1
- pat_name = "jtag_workout_#{$dut.tclk_format.upcase}#{$dut.tclk_multiple}"
2
- pat_name = pat_name + "_#{dut.tdo_store_cycle}" if dut.tdo_store_cycle != 0
3
- pat_name += "_tclk_vals" if dut.try(:tclk_vals)
4
-
5
- Pattern.create(options = { name: pat_name }) do
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- def test(msg)
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- ss "Test - #{msg}"
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- end
9
-
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- jtag = $dut.jtag
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- reg = $dut.reg(:test16)
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-
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- # First tests of the TAP Controller
14
-
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- test 'Transition TAP controller in and out of Shift-DR'
16
- jtag.shift_dr {}
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-
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- test 'Transition TAP controller in and out of Pause-DR'
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- jtag.pause_dr {}
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-
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- test 'Transition TAP controller in and out of Shift-IR'
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- jtag.shift_ir {}
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-
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- test 'Transition TAP controller in and out of Pause-IR'
25
- jtag.pause_ir {}
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-
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- test 'Transition into Shift-DR, then back and forth into Pause-DR'
28
- jtag.shift_dr do
29
- jtag.pause_dr {}
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- jtag.pause_dr {}
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- end
32
-
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- test 'Transition into Pause-DR, then back and forth into Shift-DR'
34
- jtag.pause_dr do
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- jtag.shift_dr {}
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- jtag.shift_dr {}
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- end
38
-
39
- test 'Transition into Shift-IR, then back and forth into Pause-IR'
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- jtag.shift_ir do
41
- jtag.pause_ir {}
42
- jtag.pause_ir {}
43
- end
44
-
45
- test 'Transition into Pause-IR, then back and forth into Shift-IR'
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- jtag.pause_ir do
47
- jtag.shift_ir {}
48
- jtag.shift_ir {}
49
- end
50
-
51
- # Tests of the shift method, make sure it handles registers with
52
- # bit-level flags set in additional to dumb values
53
-
54
- test 'Shifting an explicit value into TDI'
55
- jtag.shift 0x1234, size: 16, cycle_last: true
56
-
57
- test 'Shifting an explicit value out of TDO'
58
- jtag.shift 0x1234, size: 16, cycle_last: true, read: true
59
-
60
- test 'Shift register into TDI'
61
- reg.write(0xFF01)
62
- cc 'Full register (16 bits)'
63
- jtag.shift reg, cycle_last: true
64
- cc 'Full register with additional size (32 bits)'
65
- jtag.shift reg, cycle_last: true, size: 32
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- cc 'Full register with reduced size (8 bits)'
67
- jtag.shift reg, cycle_last: true, size: 8, includes_last_bit: false
68
-
69
- test 'Shift register into TDI with overlay'
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- reg.overlay('write_overlay')
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- cc 'Full register (16 bits)'
72
- tester.cycle # Give a padding cycle as a place for the subroutine call to go
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- jtag.shift reg, cycle_last: true
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- cc 'Full register with additional size (32 bits)'
75
- tester.cycle # Give a padding cycle as a place for the subroutine call to go
76
- jtag.shift reg, cycle_last: true, size: 32
77
- cc 'Full register with reduced size (8 bits)'
78
- tester.cycle # Give a padding cycle as a place for the subroutine call to go
79
- jtag.shift reg, cycle_last: true, size: 8, includes_last_bit: false
80
- cc 'It should in-line overlays when running in simulation mode'
81
- Origen.mode = :simulation
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- tester.cycle # Give a padding cycle as a place for the subroutine call to go
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- jtag.shift reg, cycle_last: true
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- Origen.mode = :debug
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- if tester.respond_to?('label')
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- cc 'Full register overlay without using subroutine'
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- jtag.shift reg, cycle_last: true, no_subr: true
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- end
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-
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- test 'Shift register into TDI with single bit overlay'
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- reg.overlay(nil)
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- reg.bit(:bit).overlay('write_overlay2')
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- tester.cycle # Give a padding cycle as a place for the subroutine call to go
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- jtag.shift reg, cycle_last: true
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- reg.overlay(nil)
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-
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- test 'Read register out of TDO'
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- cc 'Full register (16 bits)'
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- reg.read
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- jtag.shift reg, cycle_last: true, read: true
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- cc 'Full register with additional size (32 bits)'
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- reg.read
103
- jtag.shift reg, cycle_last: true, size: 32, read: true
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- cc 'Full register with reduced size (8 bits)'
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- reg.read
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- jtag.shift reg, cycle_last: true, size: 8, read: true, includes_last_bit: false
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-
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- test 'Read single bit out of TDO'
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- reg.bit(:bit).read
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- jtag.shift reg, cycle_last: true, read: true
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-
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- test 'Store register out of TDO'
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- cc 'Full register (16 bits)'
114
- reg.store
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- jtag.shift reg, cycle_last: true, read: true
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- cc 'Full register with additional size (32 bits)'
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- reg.store
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- jtag.shift reg, cycle_last: true, size: 32, read: true
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- cc 'Full register with reduced size (8 bits)'
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- reg.store
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- jtag.shift reg, cycle_last: true, size: 8, read: true, includes_last_bit: false
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-
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- test 'Store single bit out of TDO'
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- reg.bit(:bit).store
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- jtag.shift reg, cycle_last: true, read: true
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-
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- test 'Test flag clear, bit 0 should be read, but not stored'
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- reg.bit(:bit).read
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- jtag.shift reg, cycle_last: true, read: true
130
-
131
- test 'Shift register out of TDO with overlay'
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- reg.overlay('read_overlay')
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- cc 'Full register (16 bits)'
134
- tester.cycle # Give a padding cycle as a place for the subroutine call to go
135
- jtag.shift reg, cycle_last: true, read: true
136
- cc 'Full register with additional size (32 bits)'
137
- tester.cycle # Give a padding cycle as a place for the subroutine call to go
138
- jtag.shift reg, cycle_last: true, size: 32, read: true
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- cc 'Full register with reduced size (8 bits)'
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- tester.cycle # Give a padding cycle as a place for the subroutine call to go
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- jtag.shift reg, cycle_last: true, size: 8, read: true, includes_last_bit: false
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- cc 'It should in-line overlays when running in simulation mode'
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- Origen.mode = :simulation
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- tester.cycle # Give a padding cycle as a place for the subroutine call to go
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- jtag.shift reg, cycle_last: true, read: true
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- Origen.mode = :debug
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- if tester.respond_to?('label')
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- cc 'Full register overlay without using subroutine'
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- jtag.shift reg, cycle_last: true, read: true, no_subr: true
150
- end
151
-
152
- test 'Shift register out of TDO with single bit overlay'
153
- reg.overlay(nil)
154
- reg.bit(:bit).overlay('read_overlay2')
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- tester.cycle # Give a padding cycle as a place for the subroutine call to go
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- jtag.shift reg, cycle_last: true
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- reg.overlay(nil)
158
-
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- # Finally integration tests of the TAPController + shift
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-
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- test 'Write value into DR'
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- jtag.write_dr 0xFFFF, size: 16, msg: 'Write value into DR'
163
-
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- test 'Write value into DR, with compare on TDO'
165
- jtag.write_dr 0xFFFF, size: 16, shift_out_data: 0xAAAA, msg: 'Write value into DR'
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-
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- test 'Write register into DR with full-width overlay'
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- r = $dut.reg(:test32)
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- r.overlay('write_overlay')
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- jtag.write_dr r
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- r.overlay(nil)
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-
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- test 'Read value out of DR'
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- jtag.read_dr 0xFFFF, size: 16, msg: 'Read value out of DR'
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-
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- test 'Store value out of DR'
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- r.store
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- jtag.read_dr r
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-
180
-
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- test 'Read value out of DR, with specified shift in data into TDI'
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- jtag.read_dr 0xFFFF, size: 16, shift_in_data: 0x5555, msg: 'Read value out of DR'
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-
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- test 'Write value into IR'
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- jtag.write_ir 0xF, size: 4, msg: 'Write value into IR'
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-
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- test 'Read value out of IR'
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- jtag.read_ir 0xF, size: 4, msg: 'Read value out of IR'
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-
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- test 'The IR value is tracked and duplicate writes are inhibited'
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- jtag.write_ir 0xF, size: 4
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-
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- test 'Unless forced'
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- jtag.write_ir 0xF, size: 4, force: true
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-
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- test 'Reset'
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- jtag.reset
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-
199
- test 'Suspend of compare on TDO works'
200
- cc 'TDO should be H'
201
- jtag.read_dr 0xFFFF, size: 16, msg: 'Read value out of DR'
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- tester.ignore_fails($dut.pin(:tdo)) do
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- cc 'TDO should be X'
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- jtag.read_dr 0xFFFF, size: 16, msg: 'Read value out of DR'
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- end
206
- cc 'TDO should be H'
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- jtag.read_dr 0xFFFF, size: 16, msg: 'Read value out of DR'
208
-
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- test 'Mask option for read_dr works'
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- cc 'TDO should be H'
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- jtag.read_dr 0xFFFF, size: 16, mask: 0x5555, msg: 'Read value out of DR'
212
-
213
- test 'Write value into DR, with compare on TDO'
214
- jtag.write_dr 0x5555, size: 16, shift_out_data: 0xAAAA, mask: 0x00FF, msg: 'Write value into DR'
215
-
216
- test 'Shifting an explicit value out of TDO with mask'
217
- jtag.shift 0x1234, size: 16, read: true, mask: 0xFF00
218
-
219
- test 'Shifting an explicit value into TDI (and out of TDO)'
220
- jtag.shift 0x1234, size: 16, cycle_last: true, shift_out_data: 0xAAAA, mask: 0x0F0F
221
- end
1
+ pat_name = "jtag_workout_#{$dut.tclk_format.upcase}#{$dut.tclk_multiple}"
2
+ pat_name = pat_name + "_#{dut.tdo_store_cycle}" if dut.tdo_store_cycle != 0
3
+ pat_name += "_tclk_vals" if dut.try(:tclk_vals)
4
+
5
+ Pattern.create(options = { name: pat_name }) do
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+ def test(msg)
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+ ss "Test - #{msg}"
8
+ end
9
+
10
+ jtag = $dut.jtag
11
+ reg = $dut.reg(:test16)
12
+
13
+ # First tests of the TAP Controller
14
+
15
+ test 'Transition TAP controller in and out of Shift-DR'
16
+ jtag.shift_dr {}
17
+
18
+ test 'Transition TAP controller in and out of Pause-DR'
19
+ jtag.pause_dr {}
20
+
21
+ test 'Transition TAP controller in and out of Shift-IR'
22
+ jtag.shift_ir {}
23
+
24
+ test 'Transition TAP controller in and out of Pause-IR'
25
+ jtag.pause_ir {}
26
+
27
+ test 'Transition into Shift-DR, then back and forth into Pause-DR'
28
+ jtag.shift_dr do
29
+ jtag.pause_dr {}
30
+ jtag.pause_dr {}
31
+ end
32
+
33
+ test 'Transition into Pause-DR, then back and forth into Shift-DR'
34
+ jtag.pause_dr do
35
+ jtag.shift_dr {}
36
+ jtag.shift_dr {}
37
+ end
38
+
39
+ test 'Transition into Shift-IR, then back and forth into Pause-IR'
40
+ jtag.shift_ir do
41
+ jtag.pause_ir {}
42
+ jtag.pause_ir {}
43
+ end
44
+
45
+ test 'Transition into Pause-IR, then back and forth into Shift-IR'
46
+ jtag.pause_ir do
47
+ jtag.shift_ir {}
48
+ jtag.shift_ir {}
49
+ end
50
+
51
+ # Tests of the shift method, make sure it handles registers with
52
+ # bit-level flags set in additional to dumb values
53
+
54
+ test 'Shifting an explicit value into TDI'
55
+ jtag.shift 0x1234, size: 16, cycle_last: true
56
+
57
+ test 'Shifting an explicit value out of TDO'
58
+ jtag.shift 0x1234, size: 16, cycle_last: true, read: true
59
+
60
+ test 'Shift register into TDI'
61
+ reg.write(0xFF01)
62
+ cc 'Full register (16 bits)'
63
+ jtag.shift reg, cycle_last: true
64
+ cc 'Full register with additional size (32 bits)'
65
+ jtag.shift reg, cycle_last: true, size: 32
66
+ cc 'Full register with reduced size (8 bits)'
67
+ jtag.shift reg, cycle_last: true, size: 8, includes_last_bit: false
68
+
69
+ test 'Shift register into TDI with overlay'
70
+ reg.overlay('write_overlay')
71
+ cc 'Full register (16 bits)'
72
+ tester.cycle # Give a padding cycle as a place for the subroutine call to go
73
+ jtag.shift reg, cycle_last: true
74
+ cc 'Full register with additional size (32 bits)'
75
+ tester.cycle # Give a padding cycle as a place for the subroutine call to go
76
+ jtag.shift reg, cycle_last: true, size: 32
77
+ cc 'Full register with reduced size (8 bits)'
78
+ tester.cycle # Give a padding cycle as a place for the subroutine call to go
79
+ jtag.shift reg, cycle_last: true, size: 8, includes_last_bit: false
80
+ cc 'It should in-line overlays when running in simulation mode'
81
+ Origen.mode = :simulation
82
+ tester.cycle # Give a padding cycle as a place for the subroutine call to go
83
+ jtag.shift reg, cycle_last: true
84
+ Origen.mode = :debug
85
+ if tester.respond_to?('label')
86
+ cc 'Full register overlay without using subroutine'
87
+ jtag.shift reg, cycle_last: true, no_subr: true
88
+ end
89
+
90
+ test 'Shift register into TDI with single bit overlay'
91
+ reg.overlay(nil)
92
+ reg.bit(:bit).overlay('write_overlay2')
93
+ tester.cycle # Give a padding cycle as a place for the subroutine call to go
94
+ jtag.shift reg, cycle_last: true
95
+ reg.overlay(nil)
96
+
97
+ test 'Read register out of TDO'
98
+ cc 'Full register (16 bits)'
99
+ reg.read
100
+ jtag.shift reg, cycle_last: true, read: true
101
+ cc 'Full register with additional size (32 bits)'
102
+ reg.read
103
+ jtag.shift reg, cycle_last: true, size: 32, read: true
104
+ cc 'Full register with reduced size (8 bits)'
105
+ reg.read
106
+ jtag.shift reg, cycle_last: true, size: 8, read: true, includes_last_bit: false
107
+
108
+ test 'Read single bit out of TDO'
109
+ reg.bit(:bit).read
110
+ jtag.shift reg, cycle_last: true, read: true
111
+
112
+ test 'Store register out of TDO'
113
+ cc 'Full register (16 bits)'
114
+ reg.store
115
+ jtag.shift reg, cycle_last: true, read: true
116
+ cc 'Full register with additional size (32 bits)'
117
+ reg.store
118
+ jtag.shift reg, cycle_last: true, size: 32, read: true
119
+ cc 'Full register with reduced size (8 bits)'
120
+ reg.store
121
+ jtag.shift reg, cycle_last: true, size: 8, read: true, includes_last_bit: false
122
+
123
+ test 'Store single bit out of TDO'
124
+ reg.bit(:bit).store
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+ jtag.shift reg, cycle_last: true, read: true
126
+
127
+ test 'Test flag clear, bit 0 should be read, but not stored'
128
+ reg.bit(:bit).read
129
+ jtag.shift reg, cycle_last: true, read: true
130
+
131
+ test 'Shift register out of TDO with overlay'
132
+ reg.overlay('read_overlay')
133
+ cc 'Full register (16 bits)'
134
+ tester.cycle # Give a padding cycle as a place for the subroutine call to go
135
+ jtag.shift reg, cycle_last: true, read: true
136
+ cc 'Full register with additional size (32 bits)'
137
+ tester.cycle # Give a padding cycle as a place for the subroutine call to go
138
+ jtag.shift reg, cycle_last: true, size: 32, read: true
139
+ cc 'Full register with reduced size (8 bits)'
140
+ tester.cycle # Give a padding cycle as a place for the subroutine call to go
141
+ jtag.shift reg, cycle_last: true, size: 8, read: true, includes_last_bit: false
142
+ cc 'It should in-line overlays when running in simulation mode'
143
+ Origen.mode = :simulation
144
+ tester.cycle # Give a padding cycle as a place for the subroutine call to go
145
+ jtag.shift reg, cycle_last: true, read: true
146
+ Origen.mode = :debug
147
+ if tester.respond_to?('label')
148
+ cc 'Full register overlay without using subroutine'
149
+ jtag.shift reg, cycle_last: true, read: true, no_subr: true
150
+ end
151
+
152
+ test 'Shift register out of TDO with single bit overlay'
153
+ reg.overlay(nil)
154
+ reg.bit(:bit).overlay('read_overlay2')
155
+ tester.cycle # Give a padding cycle as a place for the subroutine call to go
156
+ jtag.shift reg, cycle_last: true
157
+ reg.overlay(nil)
158
+
159
+ # Finally integration tests of the TAPController + shift
160
+
161
+ test 'Write value into DR'
162
+ jtag.write_dr 0xFFFF, size: 16, msg: 'Write value into DR'
163
+
164
+ test 'Write value into DR, with compare on TDO'
165
+ jtag.write_dr 0xFFFF, size: 16, shift_out_data: 0xAAAA, msg: 'Write value into DR'
166
+
167
+ test 'Write register into DR with full-width overlay'
168
+ r = $dut.reg(:test32)
169
+ r.overlay('write_overlay')
170
+ jtag.write_dr r
171
+ r.overlay(nil)
172
+
173
+ test 'Read value out of DR'
174
+ jtag.read_dr 0xFFFF, size: 16, msg: 'Read value out of DR'
175
+
176
+ test 'Store value out of DR'
177
+ r.store
178
+ jtag.read_dr r
179
+
180
+
181
+ test 'Read value out of DR, with specified shift in data into TDI'
182
+ jtag.read_dr 0xFFFF, size: 16, shift_in_data: 0x5555, msg: 'Read value out of DR'
183
+
184
+ test 'Write value into IR'
185
+ jtag.write_ir 0xF, size: 4, msg: 'Write value into IR'
186
+
187
+ test 'Read value out of IR'
188
+ jtag.read_ir 0xF, size: 4, msg: 'Read value out of IR'
189
+
190
+ test 'The IR value is tracked and duplicate writes are inhibited'
191
+ jtag.write_ir 0xF, size: 4
192
+
193
+ test 'Unless forced'
194
+ jtag.write_ir 0xF, size: 4, force: true
195
+
196
+ test 'Reset'
197
+ jtag.reset
198
+
199
+ test 'Suspend of compare on TDO works'
200
+ cc 'TDO should be H'
201
+ jtag.read_dr 0xFFFF, size: 16, msg: 'Read value out of DR'
202
+ tester.ignore_fails($dut.pin(:tdo)) do
203
+ cc 'TDO should be X'
204
+ jtag.read_dr 0xFFFF, size: 16, msg: 'Read value out of DR'
205
+ end
206
+ cc 'TDO should be H'
207
+ jtag.read_dr 0xFFFF, size: 16, msg: 'Read value out of DR'
208
+
209
+ test 'Mask option for read_dr works'
210
+ cc 'TDO should be H'
211
+ jtag.read_dr 0xFFFF, size: 16, mask: 0x5555, msg: 'Read value out of DR'
212
+
213
+ test 'Write value into DR, with compare on TDO'
214
+ jtag.write_dr 0x5555, size: 16, shift_out_data: 0xAAAA, mask: 0x00FF, msg: 'Write value into DR'
215
+
216
+ test 'Shifting an explicit value out of TDO with mask'
217
+ jtag.shift 0x1234, size: 16, read: true, mask: 0xFF00
218
+
219
+ test 'Shifting an explicit value into TDI (and out of TDO)'
220
+ jtag.shift 0x1234, size: 16, cycle_last: true, shift_out_data: 0xAAAA, mask: 0x0F0F
221
+ end
data/pattern/rww_test.rb CHANGED
@@ -1,25 +1,25 @@
1
-
2
- Pattern.create(options = { name: 'rww_test' }) do
3
-
4
- jtag = $dut.jtag
5
- reg = $dut.reg(:full16)
6
-
7
- cc 'TDO should be HLHL_LHLH_HLHL_LHLH'
8
- jtag.write_dr 0xFFFF, size: 16, shift_out_data: 0xA5A5
9
-
10
- cc 'TDO should be XXXX_XXXX_HHHH_HHHH'
11
- reg.write(0xFFFF)
12
- reg.bits[0..7].read
13
- jtag.write_dr 0xFFFF, size: 16, shift_out_data: reg
14
-
15
-
16
- cc 'TDO should be HLHL_LHLH_HLHL_LHLH'
17
- reg.write(0xFFFF)
18
- jtag.write_dr reg, shift_out_data: 0xA5A5
19
-
20
- cc 'TDO should be XXXX_XXXX_HHHH_HHHH'
21
- reg.write(0xFFFF)
22
- reg2 = reg.dup
23
- reg2.bits[0..7].read
24
- jtag.write_dr reg, size: 16, shift_out_data: reg2
25
- end
1
+
2
+ Pattern.create(options = { name: 'rww_test' }) do
3
+
4
+ jtag = $dut.jtag
5
+ reg = $dut.reg(:full16)
6
+
7
+ cc 'TDO should be HLHL_LHLH_HLHL_LHLH'
8
+ jtag.write_dr 0xFFFF, size: 16, shift_out_data: 0xA5A5
9
+
10
+ cc 'TDO should be XXXX_XXXX_HHHH_HHHH'
11
+ reg.write(0xFFFF)
12
+ reg.bits[0..7].read
13
+ jtag.write_dr 0xFFFF, size: 16, shift_out_data: reg
14
+
15
+
16
+ cc 'TDO should be HLHL_LHLH_HLHL_LHLH'
17
+ reg.write(0xFFFF)
18
+ jtag.write_dr reg, shift_out_data: 0xA5A5
19
+
20
+ cc 'TDO should be XXXX_XXXX_HHHH_HHHH'
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+ reg.write(0xFFFF)
22
+ reg2 = reg.dup
23
+ reg2.bits[0..7].read
24
+ jtag.write_dr reg, size: 16, shift_out_data: reg2
25
+ end