origen_debuggers 0.5.0

checksums.yaml

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+---
+SHA1:
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+  data.tar.gz: 0c2ef5364b90d4681a253a32c5688981a7a11f92
+SHA512:
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data/config/application.rb

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+class OrigenDebuggersApplication < Origen::Application
+
+  # See http://origen.freescale.net/origen/latest/api/Origen/Application/Configuration.html
+  # for a full list of the configuration options available
+
+  # This information is used in headers and email templates, set it specific
+  # to your application
+  config.name     = "Origen Debuggers"
+  config.initials = "OrigenDebuggers"
+  config.rc_url   = "git@github.com:Origen-SDK/origen_debuggers.git"
+  config.release_externally = true
+
+  config.web_directory = "git@github.com:Origen-SDK/Origen-SDK.github.io.git/debuggers"
+  config.web_domain = "http://origen-sdk.org/debuggers"
+
+  # When false Origen will be less strict about checking for some common coding errors,
+  # it is recommended that you leave this to true for better feedback and easier debug.
+  # This will be the default setting in Origen v3.
+  config.strict_errors = true
+
+  config.semantically_version = true
+
+  # By default all generated output will end up in ./output.
+  # Here you can specify an alternative directory entirely, or make it dynamic such that
+  # the output ends up in a setup specific directory. 
+  #config.output_directory do
+  #  "#{Origen.root}/output/#{$dut.class}"
+  #end
+
+  # Similary for the reference files, generally you want to setup the reference directory
+  # structure to mirror that of your output directory structure.
+  #config.reference_directory do
+  #  "#{Origen.root}/.ref/#{$dut.class}"
+  #end
+  
+  config.lint_test = {
+    # Require the lint tests to pass before allowing a release to proceed
+    run_on_tag: true,
+    # Auto correct violations where possible whenever 'origen lint' is run
+    auto_correct: true, 
+    # Limit the testing for large legacy applications
+    #level: :easy,
+    # Run on these directories/files by default
+    #files: ["lib", "config/application.rb"],
+  }
+
+  # Ensure that all tests pass before allowing a release to continue
+  def validate_release
+    if !system("origen examples")
+      puts "Sorry but you can't release with failing tests, please fix them and try again."
+      exit 1
+    else
+      puts "All tests passing, proceeding with release process!"
+    end
+  end
+
+  # Run the tests before deploying to generate test coverage numbers
+  def before_deploy_site
+    Dir.chdir Origen.root do
+      system "origen examples -c"
+      #system "origen specs -c"
+      dir = "#{Origen.root}/web/output/coverage"       
+      FileUtils.remove_dir(dir, true) if File.exists?(dir) 
+      system "mv #{Origen.root}/coverage #{dir}"
+    end
+  end
+ 
+  # This will automatically deploy your documentation after every tag
+  def after_release_email(tag, note, type, selector, options)
+    command = "origen web compile --remote --api"
+    Dir.chdir Origen.root do
+      system command
+    end
+  end
+end

data/config/commands.rb

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+# This file should be used to extend the origen command line tool with tasks 
+# specific to your application.
+#
+# Also see the official docs on adding commands:
+#   http://origen-sdk.org/origen/guides/custom/commands/
+
+# Map any command aliases here, for example to allow origen -x to refer to a 
+# command called execute you would add a reference as shown below: 
+aliases ={
+#  "-x" => "execute",
+}
+
+# The requested command is passed in here as @command, this checks it against
+# the above alias table and should not be removed.
+@command = aliases[@command] || @command
+
+# Now branch to the specific task code
+case @command
+
+## Run the unit tests  
+#when "specs"
+#  require "rspec"
+#  exit RSpec::Core::Runner.run(['spec'])
+
+# Run the example-based (diff) tests
+when "examples"  
+  Origen.load_application
+  status = 0
+
+  # Compiler tests
+  #ARGV = %w(templates/example.txt.erb -t debug -r approved)
+  #load "origen/commands/compile.rb"
+  # Pattern generator tests
+  ARGV = %w(regression.list -t jlink -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
+
+  ARGV = %w(pe_regression.list -t pe -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
+
+  if Origen.app.stats.changed_files == 0 &&
+     Origen.app.stats.new_files == 0 &&
+     Origen.app.stats.changed_patterns == 0 &&
+     Origen.app.stats.new_patterns == 0
+
+    Origen.app.stats.report_pass
+  else
+    Origen.app.stats.report_fail
+    status = 1
+  end
+  puts
+  exit status  # Exit with a 1 on the event of a failure per std unix result codes
+
+# Always leave an else clause to allow control to fall back through to the
+# Origen command handler.
+# You probably want to also add the command details to the help shown via
+# origen -h, you can do this be assigning the required text to @application_commands
+# before handing control back to Origen. Un-comment the example below to get started.
+else
+  @application_commands = <<-EOT
+ examples     Run the examples (tests), -c will enable coverage
+  EOT
+
+end 

data/config/development.rb

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+# This file is similar to environment.rb and will be loaded
+# automatically at the start of each invocation of Origen.
+#
+# However the major difference is that it will not be loaded
+# if the application is imported by a 3rd party app - in that
+# case only environment.rb is loaded.
+#
+# Therefore this file should be used to load anything you need
+# to setup a development environment for this app, normally
+# this would be used to load some dummy classes to instantiate
+# your objects so that they can be tested and/or interacted with
+# in the console.
+module OrigenDebuggers
+  module Test
+    autoload :DUT, "origen_debuggers/test/dut"
+  end
+end

data/config/environment.rb

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+# This file will be required by Origen before your target is loaded, you 
+# can use this to require all of your files, which is the easiest way
+# to get started. As your experience grows you may wish to require only the
+# minimum files required to allow the target to be initialized and let 
+# each class require its own dependencies.
+#
+# It is recommended that you keep all of your application logic in lib/
+# The lib directory has already been added to the search path and so any files
+# in there can be referenced from here with a relative path.
+#
+# Note that pattern files do not need to be referenced from here and these
+# will be located automatically by origen.
+
+# This says load the file "lib/pioneer.rb" the first time anyone makes a 
+# reference to the class name 'Pioneer'.
+#autoload :Pioneer,   "pioneer"
+# This is generally preferable to using require which will load the file
+# regardless of whether it is needed by the current target or not:
+#require "pioneer"
+# Sometimes you have to use require however:-
+#   1. When defining a test program interface:
+#require "interfaces/j750"
+#   2. If you want to extend a class defined by an imported application, in
+#      this case your must use required and supply a full path (to distinguish
+#      it from the one in the parent application):
+#require "#{Origen.root}/c90_top_level/p2"
+module OrigenDebuggers
+  autoload :Base,  "origen_debuggers/base"
+  autoload :JLink, "origen_debuggers/j_link"
+  autoload :PEmicro, "origen_debuggers/p_and_e"
+end
+require "origen_debuggers"

data/config/users.rb

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+# This file defines the users associated with your project, it is basically the 
+# mailing list for release notes.
+#
+# You can split your users into "admin" and "user" groups, the main difference 
+# between the two is that admin users will get all tag emails, users will get
+# emails on external/official releases only.
+#
+# Users are also prohibited from running the "origen tag" task, but this is 
+# really just to prevent a casual user from executing it inadvertently and is
+# not intended to be a serious security gate.
+module Origen
+  module Users
+    def users
+      @users ||= [
+      ]
+    end
+  end
+end

data/config/version.rb

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+module OrigenDebuggers
+  MAJOR = 0
+  MINOR = 5
+  BUGFIX = 0
+  DEV = nil
+
+  VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
+end

data/lib/origen_debuggers/base.rb

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+module OrigenDebuggers
+  # This is base class of all debuggers, any methods/attributes
+  # defined here will be available to all
+  class Base < Origen::Tester::CommandBasedTester
+    # Returns true if the debugger supports JTAG
+    def jtag?
+      respond_to?(:write_dr)
+    end
+
+    # Concept of a cycle not supported, print out an error to the output
+    # file to alert the user that execution has hit code that is not
+    # compatible with a command based tester.
+    def cycle(*args)
+      cc '*** Cycle called ***'
+    end
+  end
+end

data/lib/origen_debuggers/j_link.rb

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+module OrigenDebuggers
+  # Driver for the Segger J-Link debugger: http://www.segger.com/debug-probes.html
+  #
+  # For reference here is the complete command list for this debugger. Note that while
+  # not recommended any of these can be called directly from an application by using the
+  # dw (direct write) method, e.g.
+  #
+  #   $tester.dw "hwinfo"
+  #   $tester.dw "mem 0x1234, 10"
+  #
+  # Available commands are:
+  # ----------------------
+  # f          Firmware info
+  # h          halt
+  # g          go
+  # Sleep      Waits the given time (in milliseconds). Syntax: Sleep <delay>
+  # s          Single step the target chip
+  # st         Show hardware status
+  # hwinfo     Show hardware info
+  # mem        Read memory. Syntax: mem  <Addr>, <NumBytes> (hex)
+  # mem8       Read  8-bit items. Syntax: mem8  <Addr>, <NumBytes> (hex)
+  # mem16      Read 16-bit items. Syntax: mem16 <Addr>, <NumItems> (hex)
+  # mem32      Read 32-bit items. Syntax: mem32 <Addr>, <NumItems> (hex)
+  # w1         Write  8-bit items. Syntax: w1 <Addr>, <Data> (hex)
+  # w2         Write 16-bit items. Syntax: w2 <Addr>, <Data> (hex)
+  # w4         Write 32-bit items. Syntax: w4 <Addr>, <Data> (hex)
+  # erase      Erase internal flash of selected device. Syntax: Erase
+  # wm         Write test words. Syntax: wm <NumWords>
+  # is         Identify length of scan chain select register
+  # ms         Measure length of scan chain. Syntax: ms <Scan chain>
+  # mr         Measure RTCK react time. Syntax: mr
+  # q          Quit
+  # qc         Close JLink connection and quit
+  # r          Reset target         (RESET)
+  # rx         Reset target         (RESET). Syntax: rx <DelayAfterReset>
+  # RSetType   Set the current reset type. Syntax: RSetType <type>
+  # Regs       Display contents of registers
+  # wreg       Write register.   Syntax: wreg <RegName>, <Value>
+  # moe        Shows mode-of-entry, meaning: Reason why CPU is halted
+  # SetBP      Set breakpoint.   Syntax: SetBP <addr> [A/T] [S/H]
+  # SetWP      Set Watchpoint. Syntax: <Addr> [R/W] [<Data> [<D-Mask>] [A-Mask]]
+  # ClrBP      Clear breakpoint. Syntax: ClrBP  <BP_Handle>
+  # ClrWP      Clear watchpoint. Syntax: ClrWP  <WP_Handle>
+  # VCatch     Write vector catch. Syntax: VCatch <Value>
+  # loadbin    Load binary file into target memory.
+  #              Syntax: loadbin <filename>, <addr>
+  # savebin    Saves target memory into binary file.
+  #             Syntax: savebin <filename>, <addr>, <NumBytes>
+  # verifybin  Verfies if the specified binary is already in the target memory at th
+  # e specified address.
+  #              Syntax: verifybin <filename>, <addr>
+  # SetPC      Set the PC to specified value. Syntax: SetPC <Addr>
+  # le         Change to little endian mode
+  # be         Change to big endian mode
+  # log        Enables log to file.  Syntax: log <filename>
+  # unlock     Unlocks a device. Syntax: unlock <DeviceName>
+  #            Type unlock without <DeviceName> to get a list
+  #            of supported device names.
+  #            nRESET has to be connected
+  # term       Test command to visualize printf output from the target device,
+  #            using DCC (SEGGER DCC handler running on target)
+  # ReadAP     Reads a CoreSight AP register.
+  #            Note: First read returns the data of the previous read.
+  #            An additional read of DP reg 3 is necessary to get the data.
+  # ReadDP     Reads a CoreSight DP register.
+  #            Note: For SWD data is returned immediately.
+  #            For JTAG the data of the previous read is returned.
+  #            An additional read of DP reg 3 is necessary to get the data.
+  # WriteAP    Writes a CoreSight AP register.
+  # WriteDP    Writes a CoreSight DP register.
+  # SWDSelect  Selects SWD as interface and outputs
+  #            the JTAG -> SWD swichting sequence.
+  # SWDReadAP  Reads a CoreSight AP register via SWD.
+  #            Note: First read returns the data of the previous read.
+  #            An additional read of DP reg 3 is necessary to get the data.
+  # SWDReadDP  Reads a CoreSight DP register via SWD.
+  #            Note: Correct data is returned immediately.
+  # SWDWriteAP Writes a CoreSight AP register via SWD.
+  # SWDWriteDP Writes a CoreSight DP register via SWD.
+  # Device     Selects a specific device J-Link shall connect to
+  #            and performs a reconnect.
+  #            In most cases explicit selection of the device is not necessary.
+  #            Selecting a device enables the user to make use of the J-Link
+  #            flash programming functionality as well as using unlimited
+  #            breakpoints in flash memory.
+  #            For some devices explicit device selection is mandatory in order
+  #            to allow the DLL to perform special handling needed by the device.
+  # ExpDevList Exports the device names from the DLL internal
+  #            device list to a text file
+  #              Syntax: ExpDevList <Filename>
+  # PowerTrace Perform power trace (not supported by all models)
+  # Syntax: PowerTrace <LogFile> [<ChannelMask> <RefCountSel>]
+  # <LogFile>: File to store power trace data to
+  # <ChannelMask>: 32-bit mask to specify what channels shall be enabled
+  # <SampleFreq>: Sampling frequency in Hz (0 == max)
+  # <RefCountSel>:       0: No reference count
+  #                      1: Number of bytes transmitted on SWO
+  # ---- CP15 ------------
+  # rce        Read CP15.  Syntax: rce <Op1>, <CRn>, <CRm>, <Op2>
+  # wce        Write CP15. Syntax: wce <Op1>, <CRn>, <CRm>, <Op2>, <Data>
+  # ---- ICE -------------
+  # Ice        Show state of the embedded ice macrocell (ICE breaker)
+  # ri         Read Ice reg.  Syntax: ri <RegIndex>(hex)
+  # wi         Write Ice reg. Syntax: wi <RegIndex>, <Data>(hex)
+  # ---- TRACE -----------
+  # TAddBranch TRACE - Add branch instruction to trace buffer. Paras:<Addr>,<BAddr>
+  # TAddInst   TRACE - Add (non-branch) instruction to trace buffer. Syntax: <Addr>
+  # TClear     TRACE - Clear buffer
+  # TSetSize   TRACE - Set Size of trace buffer
+  # TSetFormat TRACE - SetFormat
+  # TSR        TRACE - Show Regions (and analyze trace buffer)
+  # TStart     TRACE - Start
+  # TStop      TRACE - Stop
+  # ---- SWO -------------
+  # SWOSpeed   SWO - Show supported speeds
+  # SWOStart   SWO - Start
+  # SWOStop    SWO - Stop
+  # SWOStat    SWO - Display SWO status
+  # SWORead    SWO - Read and display SWO data
+  # SWOShow    SWO - Read and analyze SWO data
+  # SWOFlush   SWO - Flush data
+  # SWOView    SWO - View terminal data
+  # ---- PERIODIC --------
+  # PERConf    PERIODIC - Configure
+  # PERStart   PERIODIC - Start
+  # PERStop    PERIODIC - Stop
+  # PERStat    PERIODIC - Display status
+  # PERRead    PERIODIC - Read and display data
+  # PERShow    PERIODIC - Read and analyze data
+  # ---- File I/O --------
+  # fwrite     Write file to emulator
+  # fread      Read file from emulator
+  # fshow      Read and display file from emulator
+  # fdelete    Delete file on emulator
+  # fsize      Display size of file on emulator
+  # ---- Test ------------
+  # TestHaltGo   Run go/halt 1000 times
+  # TestStep     Run step 1000 times
+  # TestCSpeed   Measure CPU speed.
+  #              Parameters: [<RAMAddr>]
+  # TestWSpeed   Measure download speed into target memory.
+  #              Parameters:  [<Addr> [<Size>]]
+  # TestRSpeed   Measure upload speed from target memory.
+  #              Parameters: [<Addr> [<Size>] [<NumBlocks>]]
+  # TestNWSpeed  Measure network download speed.
+  #              Parameters: [<NumBytes> [<NumReps>]]
+  # TestNRSpeed  Measure network upload speed.
+  #              Parameters: [<NumBytes> [<NumReps>]]
+  # ---- JTAG ------------
+  # Config     Set number of IR/DR bits before ARM device.
+  #              Syntax: Config <IRpre>, <DRpre>
+  # speed      Set JTAG speed. Syntax: speed <freq>|auto|adaptive, e.g. speed 2000,
+  # speed a
+  # i          Read JTAG Id (Host CPU)
+  # wjc        Write JTAG command (IR). Syntax: wjc <Data>(hex)
+  # wjd        Write JTAG data (DR). Syntax: wjd <Data64>(hex), <NumBits>(dec)
+  # RTAP       Reset TAP Controller using state machine (111110)
+  # wjraw      Write Raw JTAG data. Syntax: wjraw <NumBits(dec)>, <tms>, <tdi>
+  # rt         Reset TAP Controller (nTRST)
+  # ---- JTAG-Hardware ---
+  # c00        Create clock with TDI = TMS = 0
+  # c          Clock
+  # tck0       Clear TCK
+  # tck1       Set   TCK
+  # 0          Clear TDI
+  # 1          Set   TDI
+  # t0         Clear TMS
+  # t1         Set   TMS
+  # trst0      Clear TRST
+  # trst1      Set   TRST
+  # r0         Clear RESET
+  # r1         Set   RESET
+  # ---- Connection ------
+  # usb        Connect to J-Link via USB.  Syntax: usb <port>, where port is 0..3
+  # ip         Connect to J-Link ARM Pro or J-Link TCP/IP Server via TCP/IP.
+  #            Syntax: ip <ip_addr>
+  # ---- Configuration ---
+  # si         Select target interface. Syntax: si <Interface>,
+  #            where 0=JTAG and 1=SWD.
+  # power      Switch power supply for target. Syntax: power <State> [perm],
+  #            where State is either On or Off. Example: power on perm
+  # wconf      Write configuration byte. Syntax: wconf <offset>, <data>
+  # rconf      Read configuration bytes. Syntax: rconf
+  # ipaddr     Show/Assign IP address and subnetmask of/to the connected J-Link.
+  # gwaddr     Show/Assign network gateway address of/to the connected J-Link.
+  # dnsaddr    Show/Assign network DNS server address of/to the connected J-Link.
+  # conf       Show configuration of the connected J-Link.
+  # ecp        Enable the  J-Link control panel.
+  # calibrate  Calibrate the target current measurement.
+  # selemu     Select a emulator to communicate with,
+  #            from a list of all emulators which are connected to the host
+  #            The interfaces to search on, can be specified
+  #              Syntax: selemu [<Interface0> <Interface1> ...]
+  # ShowEmuList Shows a list of all emulators which are connected to the host.
+  #             The interfaces to search on, can be specified.
+  #              Syntax: ShowEmuList [<Interface0> <Interface1> ...]
+  # ----------------------
+  # NOTE: Specifying a filename in command line
+  # will start J-Link Commander in script mode.
+  class JLink < Base
+    def initialize
+      super
+      # The minimum time unit is 1ms
+      set_timeset('default', 1_000_000)
+      @pat_extension = 'jlk'
+      @comment_char = '//'
+    end
+
+    # All debuggers should try and support these methods
+    module Common_API
+      def delay(cycles)
+        dw "Sleep #{cycles_to_ms(cycles)}"
+      end
+
+      def write(reg_or_val, options = {})
+        send("write#{extract_size(reg_or_val, options)}".to_sym, reg_or_val, options)
+      end
+      alias_method :write_register, :write
+
+      def read(reg_or_val, options = {})
+        send("read#{extract_size(reg_or_val, options)}".to_sym, reg_or_val, options)
+      end
+      alias_method :read_register, :read
+
+      # Read 8 bits of data to the given byte address
+      def read8(data, options = {})
+        read_memory(extract_address(data, options), number_of_bytes: 1)
+      end
+      alias_method :read_byte, :read8
+      alias_method :read_8, :read8
+
+      # Read 16 bits of data to the given byte address
+      def read16(data, options = {})
+        read_memory(extract_address(data, options), number_of_bytes: 2)
+      end
+      alias_method :read_word, :read16
+      alias_method :read_16, :read16
+
+      # Read 32 bits of data to the given byte address
+      def read32(data, options = {})
+        read_memory(extract_address(data, options), number_of_bytes: 4)
+      end
+      alias_method :read_longword, :read32
+      alias_method :read_32, :read32
+
+      # Write 8 bits of data to the given byte address
+      def write8(data, options = {})
+        dw "w1 0x#{extract_address(data, options).to_s(16).upcase}, 0x#{extract_data(data, options).to_s(16).upcase}"
+      end
+      alias_method :write_byte, :write8
+      alias_method :write_8, :write8
+
+      # Write 16 bits of data to the given byte address
+      def write16(data, options = {})
+        dw "w2 0x#{extract_address(data, options).to_s(16).upcase}, 0x#{extract_data(data, options).to_s(16).upcase}"
+      end
+      alias_method :write_word, :write16
+      alias_method :write_16, :write16
+
+      # Write 32 bits of data to the given byte address
+      def write32(data, options = {})
+        dw "w4 0x#{extract_address(data, options).to_s(16).upcase}, 0x#{extract_data(data, options).to_s(16).upcase}"
+      end
+      alias_method :write_longword, :write32
+      alias_method :write_32, :write32
+
+      # @api private
+      def extract_size(reg_or_val, options = {})
+        size = options[:size] if options[:size]
+        unless size
+          if reg_or_val.respond_to?(:contains_bits?) && reg_or_val.contains_bits?
+            size = reg_or_val.size
+          end
+        end
+        fail 'You must supply an :size option if not providing a register!' unless size
+        unless [8, 16, 32].include?(size)
+          fail 'Only a size of 8, 16 or 32 is supported!'
+        end
+        size
+      end
+
+      # @api private
+      def extract_data(reg_or_val, options = {})
+        return options[:data] if options[:data]
+        return reg_or_val.data if reg_or_val.respond_to?(:data)
+        reg_or_val
+      end
+
+      # @api private
+      def extract_address(reg_or_val, options = {})
+        addr = options[:addr] || options[:address]
+        return addr if addr
+        addr = reg_or_val.address if reg_or_val.respond_to?(:address)
+        fail 'You must supply an :address option if not providing a register!' unless addr
+        addr
+      end
+    end
+    include Common_API
+
+    # If the debugger supports JTAG definitely add these methods, this provides
+    # instant compatibility with any application that uses a JTAG based protocol
+    module JTAG_API
+      # Write the given value, register or bit collection to the data register
+      def write_dr(reg_or_val, options = {})
+        if reg_or_val.respond_to?(:data)
+          data = reg_or_val.data
+          size = options[:size] || reg_or_val.size
+        else
+          data = reg_or_val
+          size = options[:size]
+        end
+        dw "wjd 0x#{data.to_s(16).upcase}, #{size}\nc"  # the extra clock cycle is needed here to opperate correctly on certain devices
+        # the added clock cycle means that the JLink opperation matches the atp tester opperation (J750 etc)
+        # some devices may function without the addition, however an extra clock cycle in "run-Test/idle" is unlikely to
+        # break anything so has been added universally.
+      end
+
+      # Read the given value, register or bit collection from the data register
+      def read_dr(reg_or_val, options = {})
+        # Can't read the DR via J-Link
+      end
+
+      # Write the given value, register or bit collection to the instruction register
+      def write_ir(reg_or_val, options = {})
+        if reg_or_val.respond_to?(:data)
+          data = reg_or_val.data
+        else
+          data = reg_or_val
+        end
+        dw "wjc 0x#{data.to_s(16).upcase}"
+      end
+
+      # Read the given value, register or bit collection from the instruction register
+      def read_ir(reg_or_val, options = {})
+        # Can't read the IR via J-Link
+      end
+    end
+    include JTAG_API
+
+    # Other methods can expose unique features of a given debugger
+    module Custom
+      def read_memory(address, options = {})
+        options = {
+          number_of_bytes: 1
+        }.merge(options)
+        dw "mem 0x#{address.to_s(16).upcase}, #{options[:number_of_bytes]}"
+      end
+    end
+    include Custom
+  end
+end

data/lib/origen_debuggers/p_and_e.rb

@@ -0,0 +1,309 @@
+module OrigenDebuggers
+  # Driver for the P&E Microsystems debugger: http://www.pemicro.com
+  #
+  # For reference here is a command list for this debugger. Note, many commands can be
+  # altered using additional opperands, see help for details.  Note that while
+  # not recommended any of these can be called directly from an application by using the
+  # dw (direct write) method, e.g.
+  #
+  #   $tester.dw "****"
+  #   $tester.dw "****"
+  #
+  # Available commands are:
+  #
+  # write_ir  write "raw" jtag to the instruction register
+  # write_dr  write "raw" jtag to the data register
+  #
+  # ADDSPR 	Sets user-defined SPR name to equal user-defined SPR number.
+  # ASCIIF3 (ASCIIF6) 	Toggle the F3(F6) memory window between showing hexadecimal bytes and ASCII characters.  Nonprintable characters are shown as an ASCII period ('.').
+  # ASM 	Assemble instructions.
+  # BELL 	Sound Bell
+  # BF  	Block fill memory.
+  # BGND_TIME 	Starts processor execution at the current Program Counter and logs time since the last BGND instruction each time a BGND instruction is encountered.
+  # BR  	Set instruction breakpoint.
+  # CAPTURE 	Open a capture file named 'filename'.
+  # CAPTUREOFF 	Turn off capturing and close the current capture file.
+  # CLEARMAP	Remove all symbolic mapfile names.
+  # CLEARSYMBOL	Remove all temporary symbols.
+  # CLEARVAR 	Clears variables list from Variables window.
+  # CODE 	Show disassembled code in the code window starting at address add.  If you specify an address in the middle of an intended instruction, improper results may occur.
+  # COLORS 	Change Debugger Colors
+  # COUNT 	Counts the number of times breakpoints in internal counter table are executed.  Allows optional stop and start parameters to be set.
+  # COUNTER 	Add or subtract a location from the internal counter table.  Using this command with no address shows the current counters.
+  # CR  	Set Condition Register.
+  # CTR 	Set Counter Register
+  # DASM 	Disassemble Instructions
+  # DUMP_TRACE	Dump current trace buffer.
+  # DUMP 	Dumps memory to screen.
+  # EVAL	Evaluate expression.
+  # EXECUTE_OPCODE Treats numeric parameter as an opcode and executes it.
+  # EXIT	Exit debugger.
+  # FPSCR 	Set Floating Point Status And Control Register
+  # FR(x) 	Set Floating Point Register.
+  # G or GO  	Begin program execution.
+  # GOALL  	Begin program execution for multi-core devices..
+  # GOEXIT 	Begin program execution without breakpoints and terminate debugger software.
+  # GOTIL 	Execute until address.
+  # GOTILROM 	Execute fast single steps without updating the screen, until the address is reached.  This is the fastest way to breakpoint in ROM.
+  # HELP	Bring up the help window.
+  # HGO 	Begin Program Execution
+  # HGOALL 	Begin Program Execution For Multi-Core Devices
+  # HLOAD 	Load ELF/DWARF/S19/MAP Object And Debug Information
+  # HLOADMAP 	Load DWARF/MAP Debug Info Only
+  # HSTEP 	High-Level Language Source Step
+  # HSTEPALL 	High-Level Language Source Step For Multi-Core Devices
+  # HSTEPFOR 	High-Level Language Step Forever
+  # LOADDESK 	Loads the visual layout for the debugger from the last instance it was saved, such as with the SAVEDESK command.
+  # LOAD_BIN 	Load a binary file of byte.  The default filename extension is .BIN.
+  # LOADV_BIN 	Perform LOAD_BIN command, verify using the same file.
+  # LOGFILE 	Open/Close Log File
+  # LR    	Set Link Register
+  # MACRO	Execute a Batch File
+  # MACROEND	Stop Saving Commands to File
+  # MACROSTART	Save Debug Commands to File
+  # MACS 	Bring up a window with a list of macros.  These are files with the extension .ICD (such as the STARTUP.ICD macro).  Use the arrow keys and the <ENTER> key or cancel with the <ESC> key.
+  # MD	        Set Memory Window 1 to a specific address.
+  # MD2 	Set Memory Window 2 to a specific address.
+  # MM	        Memory modify.
+  # MSR 	Set Machine Status Register
+  # NOBR 	Clear all break points.
+  # PC	        Set Program Counter.
+  # QUIET	Turn off (on) refresh of memory based windows.
+  # QUIT	Exit debugger.
+  # R	        Display and edit registers (requires REG software).
+  # R(x)	Set General Purpose Register R(x).
+  # REM	        Place comment in macro file.
+  # RESET	Force reset of device into background mode.
+  # RTVAR 	Displays a specified address and its contents in the Variables window for viewing during code execution and while the part is running (real time).
+  # SAVEDESK 	Saves the current visual layout of the debugger.
+  # SERIAL	Set up parameters for dumb terminal.
+  # SERIALOFF	Disable the status window as a dumb terminal.
+  # SERIALON	Enable the status window as a dumb terminal.
+  # SHOWCODE 	Display Code at Address
+  # SHOWMMU 	Displays MMU Information
+  # SHOWPC 	Display Code at PC
+  # SHOWSPR 	Displays SPR Information
+  # SHOWTRACE 	Allows the user to view this trace buffer after having executed the TRACE command.
+  # SNAPSHOT	Send snapshot of screen to capture file.
+  # SOURCEPATH 	Search for source code.
+  # SPR 	Display/modify the value of the special purpose register at address add.
+  # SS	        Execute source step(s)..
+  # ST 	        Execute single step in assembly.
+  # STATUS 	Show registers.
+  # STEP 	Same as ST.
+  # STEPALL 	Execute single step in assembly for multi-core devices.
+  # STEPFOR	Step forever on assembly level.
+  # STEPTIL 	Step until address on the assembly level.
+  # SYMBOL 	Add user symbol.
+  # TIME 	Displays real time elapsed during execution of code
+  # _TR 	Add register field description to the VAR Window
+  # TRACE 	Monitors execution of the CPU and logs instructions.
+  # UPLOAD_SREC Uloads S records to screen.
+  # VAR	        Display variable.
+  # VERIFY	Compare the contents of program memory with an S-record file.
+  # VERSION 	Display the version number of the ICD software.
+  # WATCHDOG	Disable the watchdog if active.
+  # WHEREIS	Display symbol value.
+  # XER 	Set Integer Exception Register.
+  # ----------------------
+
+  class PEmicro < Base
+    def initialize
+      super
+      set_timeset('default', 1_000_000)
+      @pat_extension = 'mac'
+      @comment_char = ';'
+      @in_jtag = false
+    end
+
+    # All debuggers should try and support these methods
+    module Common_API
+      def delay(cycles)
+        dw 'jtag_end' if @in_jtag
+        @in_jtag = false
+        dw "delay #{cycles_to_ms(cycles)}"
+      end
+
+      def write(reg_or_val, options = {})
+        dw 'jtag_end' if @in_jtag
+        @in_jtag = false
+        send("write#{extract_size(reg_or_val, options)}".to_sym, reg_or_val, options)
+      end
+      alias_method :write_register, :write
+
+      def read(reg_or_val, options = {})
+        dw 'jtag_end' if @in_jtag
+        @in_jtag = false
+        send("read#{extract_size(reg_or_val, options)}".to_sym, reg_or_val, options)
+      end
+      alias_method :read_register, :read
+
+      # Read 8 bits of data to the given byte address
+      def read8(data, options = {})
+        dw 'jtag_end' if @in_jtag
+        @in_jtag = false
+        dw "DUMP.B #{(extract_address(data, options))} #{(extract_address(data, options))}"
+      end
+      alias_method :read_byte, :read8
+      alias_method :read_8, :read8
+
+      # Read 16 bits of data to the given byte address
+      def read16(data, options = {})
+        dw 'jtag_end' if @in_jtag
+        @in_jtag = false
+        dw "DUMP.W #{extract_address(data, options)} #{(extract_address(data, options))}"
+      end
+      alias_method :read_word, :read16
+      alias_method :read_16, :read16
+
+      # Read 32 bits of data to the given byte address
+      def read32(data, options = {})
+        dw 'jtag_end' if @in_jtag
+        @in_jtag = false
+        dw "DUMP.L #{(extract_address(data, options))} #{(extract_address(data, options))}"
+      end
+      alias_method :read_longword, :read32
+      alias_method :read_32, :read32
+
+      # Write 8 bits of data to the given byte address
+      def write8(data, options = {})
+        dw 'jtag_end' if @in_jtag
+        @in_jtag = false
+        dw "MM.B #{extract_address(data, options).to_s(16).upcase} #{extract_data(data, options).to_s(16).upcase}"
+      end
+      alias_method :write_byte, :write8
+      alias_method :write_8, :write8
+
+      # Write 16 bits of data to the given byte address
+      def write16(data, options = {})
+        dw 'jtag_end' if @in_jtag
+        @in_jtag = false
+        dw "MM.W #{extract_address(data, options).to_s(16).upcase} #{extract_data(data, options).to_s(16).upcase}"
+      end
+      alias_method :write_word, :write16
+      alias_method :write_16, :write16
+
+      # Write 32 bits of data to the given byte address
+      def write32(data, options = {})
+        dw 'jtag_end' if @in_jtag
+        @in_jtag = false
+        dw "MM.L #{extract_address(data, options).to_s(16).upcase} #{extract_data(data, options).to_s(16).upcase}"
+      end
+      alias_method :write_longword, :write32
+      alias_method :write_32, :write32
+
+      # @api private
+      def extract_size(reg_or_val, options = {})
+        size = options[:size] if options[:size]
+        unless size
+          if reg_or_val.respond_to?(:contains_bits?) && reg_or_val.contains_bits?
+            size = reg_or_val.size
+          end
+        end
+        fail 'You must supply an :size option if not providing a register!' unless size
+        unless [8, 16, 32].include?(size)
+          fail 'Only a size of 8, 16 or 32 is supported!'
+        end
+        size
+      end
+
+      # @api private
+      def extract_data(reg_or_val, options = {})
+        return options[:data] if options[:data]
+        return reg_or_val.data if reg_or_val.respond_to?(:data)
+        reg_or_val
+      end
+
+      # @api private
+      def extract_address(reg_or_val, options = {})
+        addr = options[:addr] || options[:address]
+        return addr if addr
+        addr = reg_or_val.address if reg_or_val.respond_to?(:address)
+        fail 'You must supply an :address option if not providing a register!' unless addr
+        addr
+      end
+    end
+    include Common_API
+
+    # If the debugger supports JTAG definitely add these methods, this provides
+    # instant compatibility with any application that uses a JTAG based protocol
+    module JTAG_API
+      # Write the given value, register or bit collection to the data register
+      def write_dr(reg_or_val, options = {})
+        dw 'jtag_start' unless @in_jtag
+        @in_jtag = true
+        if reg_or_val.respond_to?(:data)
+          data = reg_or_val.data
+          size = options[:size] || reg_or_val.size
+        else
+          data = reg_or_val
+          size = options[:size]
+        end
+        dw "jtag_dr #{size}t #{data.to_s(16).downcase}"
+      end
+
+      # Read the given value, register or bit collection from the data register
+      def read_dr(reg_or_val, options = {})
+        # Can't read the DR
+      end
+
+      # Write the given value, register or bit collection to the instruction register
+      def write_ir(reg_or_val, options = {})
+        dw 'jtag_start' unless @in_jtag
+        @in_jtag = true
+        size = options[:size] || 4 # Used to be hardcoded to 4 with no override capability
+        if reg_or_val.respond_to?(:data)
+          data = reg_or_val.data
+        else
+          data = reg_or_val
+        end
+        dw "jtag_ir #{size}t #{data.to_s(16).downcase}"
+      end
+
+      # Read the given value, register or bit collection from the instruction register
+      def read_ir(reg_or_val, options = {})
+        # Can't read the IR
+      end
+    end
+    include JTAG_API
+
+    # Other methods can expose unique features of a given debugger
+    module Custom
+      def set_pc(address)
+        dw 'jtag_end' if @in_jtag
+        @in_jtag = false
+        dw "PC $#{address.to_s(16).upcase}"
+      end
+      alias_method :setPC, :set_pc
+
+      def go
+        dw 'jtag_end' if @in_jtag
+        @in_jtag = false
+        dw 'GO'
+      end
+
+      def halt
+        dw "\n"
+      end
+
+      def exit_jtag # not expected to be typically used, should be automatically handled in code, unless manually doing  dw "..." calls
+        dw 'jtag_end'
+        @in_jtag = false
+      end
+
+      def enter_jtag # not expected to be typically used, should be automatically handled in code, unless manually doing  dw "..." calls
+        dw 'jtag_start'
+        @in_jtag = true
+      end
+    end
+    include Custom
+
+    def footer_template # if at the end of the file, and still in a jtag mode, close the jtag mode.
+      if @in_jtag
+        "#{Origen.root!}/lib/origen_debuggers/p_e/jtag_end.txt"
+      else
+        "#{Origen.root!}/lib/origen_debuggers/p_e/none.txt"
+      end
+    end
+  end
+end

data/lib/origen_debuggers/p_e/jtag_end.txt

@@ -0,0 +1 @@
+jtag_end

data/lib/origen_debuggers/test/dut.rb

@@ -0,0 +1,34 @@
+module OrigenDebuggers
+  module Test
+    # A simple DUT model used to test the debuggers
+    class DUT
+      include OrigenJTAG
+      include Origen::Pins
+      include Origen::Registers
+
+      def initialize
+        add_pin :tclk
+        add_pin :tdi
+        add_pin :tdo
+        add_pin :tms
+
+        reg :reg32, 0x20 do
+          bits 31..0, :data
+        end
+      end
+
+      # Hook the Nexus into the register API, any register read
+      # requests will use the Nexus by default
+      def read_register(reg, options = {})
+        # nexus.read_register(reg, options)
+        cc 'Needs to be enabled when a register protocol is available'
+      end
+
+      # As above for write requests
+      def write_register(reg, options = {})
+        # nexus.write_register(reg, options)
+        cc 'Needs to be enabled when a register protocol is available'
+      end
+    end
+  end
+end

data/lib/origen_debuggers.rb

@@ -0,0 +1,3 @@
+require 'origen'
+require_relative '../config/application.rb'
+require_relative '../config/environment.rb'

data/pattern/_workout.rb

@@ -0,0 +1,44 @@
+# These are common tests for all testers
+ss "Verify a register API write"
+$dut.reg(:reg32).write!(0x1234_5678)
+
+ss "Verify a register API read"
+$dut.reg(:reg32).read!
+
+if $tester.jtag?
+  ss "Verify write_dr with a register"
+  $tester.write_dr $dut.reg(:reg32)
+  ss "Verify write_dr with a data value"
+  $tester.write_dr 0x1122, :size => 16
+  ss "Verify read_dr with a register"
+  $tester.read_dr $dut.reg(:reg32)
+  ss "Verify read_dr with a data value"
+  $tester.read_dr 0x1122, :size => 16
+  ss "Verify write_ir with a register"
+  $tester.write_ir $dut.reg(:reg32)
+  ss "Verify write_ir with a data value"
+  $tester.write_ir 0x1122, :size => 16
+  ss "Verify read_ir with a register"
+  $tester.read_ir $dut.reg(:reg32)
+  ss "Verify read_ir with a data value"
+  $tester.read_ir 0x1122, :size => 16
+end
+
+ss "Verify write_register method"
+$tester.write_register $dut.reg(:reg32)
+ss "Verify read_register method"
+$tester.read_register $dut.reg(:reg32)
+ss "Verify write8" 
+$tester.write8 0x55, :address => 0x12
+ss "Verify write16" 
+$tester.write16 0x55AA, :address => 0x12
+ss "Verify write32" 
+$tester.write32 0x55AA_3344, :address => 0x12
+ss "Verify write with a register" 
+$tester.write $dut.reg(:reg32)
+ss "Verify write with a data value" 
+$tester.write 0x55, :address => 0x12, :size => 8
+ss "Verify read with a register" 
+$tester.read $dut.reg(:reg32)
+ss "Verify read with a data value" 
+$tester.read 0x55, :address => 0x12, :size => 8

data/pattern/jlink_workout.rb

@@ -0,0 +1,5 @@
+Pattern.create do
+  ss "Verify the time base, wait for 10ms which should be 10 sleep cycles"
+  $tester.wait :time_in_ms => 10
+  load "#{Origen.root}/pattern/_workout.rb"
+end

data/pattern/pe_low_level.rb

@@ -0,0 +1,9 @@
+Pattern.create do
+  ss 'Verify different shift_ir lengths'
+
+  $dut.jtag.write_ir(0x7)
+
+  $dut.jtag.write_ir(0x8, size: 5)
+
+  $dut.jtag.write_ir(0x9, size: 6)
+end

data/templates/web/index.md.erb

@@ -0,0 +1,66 @@
+% render "layouts/basic.html" do
+
+%# HTML tags can be embedded in mark down files if you want to do specific custom
+%# formatting like this, but in most cases that is not required.
+<h1><%= Origen.config.name %> <span style="font-size: 14px">(<%= Origen.app.version %>)</span></h1>
+
+### Purpose
+
+This plugin provides tester models to drive bench debuggers such as the Segger J-Link or PE Micro.
+
+### How To Import
+
+##### To use in an application:
+
+Add the following to your application's <code>Gemfile</code>:
+
+~~~ruby
+gem 'origen_debuggers', '<%= Origen.app.version %>'
+~~~
+
+##### To use in a plugin:
+
+Add the following to your plugin's gemspec:
+
+~~~ruby
+spec.add_runtime_dependency 'origen_debuggers', '~> <%= Origen.app.version.major %>', '>= <%= Origen.app.version %>'
+~~~
+
+and require the gem in your code:
+
+~~~ruby
+require 'origen_debuggers'
+~~~
+
+### How To Use
+
+For JTAG based protocols all that should be required is to change the application target
+to instantiate one of the debuggers that support JTAG, such as J-Link or P&E:
+
+~~~ruby
+$tester = OrigenDebuggers::JLink.new
+#  or
+#$tester = OrigenDebuggers::PEmircro.new
+~~~
+
+Patterns should now generate a debugger command file without any additional application
+modifications.
+
+### How To Setup a Development Environment
+
+[Clone the repository from Github](https://github.com/Origen-SDK/origen_debuggers).
+
+Some patterns can be found in the pattern directory to exercise the debuggers.
+
+Follow the instructions here if you want to make a 3rd party app
+workspace use your development copy of the <%= Origen.app.config.initials %> plugin:
+[Setting up a Plugin Development Environment](http://origen-sdk.org/origen/latest/guides/plugins)
+
+This plugin also contains a test suite, make sure this passes before committing
+any changes!
+
+~~~
+origen examples
+~~~
+
+% end

data/templates/web/layouts/_basic.html.erb

@@ -0,0 +1,16 @@
+---
+title: <%= options[:title] || Origen.config.name %>
+analytics: UA-64455560-1
+---
+<%= render "templates/web/partials/navbar.html", tab: options[:tab] %>
+
+<div class="row">
+%# The markdown attribute is important if you are going to include content written
+%# in markdown, without this is will be included verbatim
+  <div class="span12" markdown="1">
+<%= yield %>    
+
+<%= disqus_comments %>
+
+</div>
+</div>

data/templates/web/partials/_navbar.html.erb

@@ -0,0 +1,22 @@
+<nav class="navbar navbar-inverse navbar-fixed-top">
+  <div class="container">
+    <div class="navbar-header">
+      <button type="button" class="navbar-toggle collapsed" data-toggle="collapse" data-target="#navbar" aria-expanded="false" aria-controls="navbar">
+        <span class="sr-only">Toggle navigation</span>
+        <span class="icon-bar"></span>
+        <span class="icon-bar"></span>
+        <span class="icon-bar"></span>
+      </button>
+      <a class="navbar-brand" href="<%= path "/" %>">Home</a>
+    </div>
+    <div id="navbar" class="collapse navbar-collapse">
+      <ul class="nav navbar-nav">
+        <li class="<%= options[:tab] == :api ? 'active' : '' %>"><a href="<%= path "/api/" %>">API</a></li>
+        <li class="<%= options[:tab] == :coverage ? 'active' : '' %>"><a href="<%= path "/coverage" %>">Coverage</a></li>
+        <li class="<%= options[:tab] == :release ? 'active' : '' %>"><a href="<%= path "/release_notes" %>">Release Notes</a></li>
+        <li><a href="https://github.com/Origen-SDK/origen_debuggers">Github</a></li>
+      </ul>
+      <%= import "origen/web/logo.html" %>
+    </div><!--/.nav-collapse -->
+  </div>
+</nav>

data/templates/web/release_notes.md.erb

@@ -0,0 +1,5 @@
+% render "layouts/basic.html", tab: :release do
+
+<%= render "#{Origen.root}/doc/history" %>
+
+% end

metadata

@@ -0,0 +1,107 @@
+--- !ruby/object:Gem::Specification
+name: origen_debuggers
+version: !ruby/object:Gem::Version
+  version: 0.5.0
+platform: ruby
+authors:
+- Stephen McGinty
+autorequire: 
+bindir: bin
+cert_chain: []
+date: 2015-08-31 00:00:00.000000000 Z
+dependencies:
+- !ruby/object:Gem::Dependency
+  name: origen
+  requirement: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: 0.2.6
+  type: :runtime
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: 0.2.6
+- !ruby/object:Gem::Dependency
+  name: origen_doc_helpers
+  requirement: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: 0.2.0
+  type: :development
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: 0.2.0
+- !ruby/object:Gem::Dependency
+  name: origen_jtag
+  requirement: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: 0.12.0
+  type: :development
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: 0.12.0
+description: 
+email:
+- stephen.f.mfcginty@gmail.com
+executables: []
+extensions: []
+extra_rdoc_files: []
+files:
+- config/application.rb
+- config/commands.rb
+- config/development.rb
+- config/environment.rb
+- config/users.rb
+- config/version.rb
+- lib/origen_debuggers.rb
+- lib/origen_debuggers/base.rb
+- lib/origen_debuggers/j_link.rb
+- lib/origen_debuggers/p_and_e.rb
+- lib/origen_debuggers/p_e/jtag_end.txt
+- lib/origen_debuggers/p_e/none.txt
+- lib/origen_debuggers/test/dut.rb
+- pattern/_workout.rb
+- pattern/jlink_workout.rb
+- pattern/pe_low_level.rb
+- templates/web/index.md.erb
+- templates/web/layouts/_basic.html.erb
+- templates/web/partials/_navbar.html.erb
+- templates/web/release_notes.md.erb
+homepage: http://origen-sdk.org/debuggers
+licenses: []
+metadata: {}
+post_install_message: 
+rdoc_options: []
+require_paths:
+- lib
+required_ruby_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: 1.9.3
+required_rubygems_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: 1.8.11
+requirements: []
+rubyforge_project: 
+rubygems_version: 2.2.2
+signing_key: 
+specification_version: 4
+summary: Provides Origen tester models to drive bench debuggers such as the Segger
+  J-Link.
+test_files: []
+has_rdoc: