origen_arm_debug 1.0.1 → 1.0.2
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- checksums.yaml +4 -4
- data/config/version.rb +1 -1
- data/lib/origen_arm_debug/ap.rb +1 -1
- data/lib/origen_arm_debug/jtag_dp_controller.rb +2 -0
- data/lib/origen_arm_debug/mem_ap.rb +2 -2
- data/templates/web/index.md.erb +90 -7
- metadata +11 -5
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA1:
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metadata.gz:
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data.tar.gz:
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metadata.gz: e5dd246d4525d4ced61bb06b8bccca56084e3ed9
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data.tar.gz: ef1eaa8501694c28aa03227326a2da6cf2e3c9b2
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 3d194a9455d7c34f0dfa0bf366f1aaa31e094f0eb470d3c209557faa4651a7edd70d8e1293630984c4a7d9b6eb73588410c80a446bc9532dad04c272d30e54af
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data.tar.gz: cec545de10b7f3bbe7f2c93b7f1c6053b074c583e3b42f24f8ca38c197decfd4e0b71e50fb407359ee6c317d267225138fedce4cb29f5eaaa550ee30cd158285
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data/config/version.rb
CHANGED
data/lib/origen_arm_debug/ap.rb
CHANGED
@@ -4,7 +4,7 @@ module OrigenARMDebug
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include Origen::Model
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# Wait states for data to be transferred from AP-Reg to RDBUFF (on read)
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-
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attr_accessor :apreg_access_wait
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def initialize(options = {})
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@apreg_access_wait = options[:apreg_access_wait] || 0
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@@ -95,6 +95,7 @@ module OrigenARMDebug
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dr[0].write(1)
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dr[2..1].write(rdbuff.offset >> 2)
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dr[34..3].copy_all(reg)
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options[:mask] = options[:mask] << 3 unless options[:mask].nil?
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dut.jtag.read_dr(dr, options)
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else
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@@ -131,6 +132,7 @@ module OrigenARMDebug
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dr[0].write(1)
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dr[2..1].write(rdbuff.offset >> 2)
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dr[34..3].copy_all(reg)
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options[:mask] = options[:mask] << 3 unless options[:mask].nil?
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ir.write!(0b1010)
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dut.jtag.read_dr(dr, options)
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end
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@@ -2,12 +2,12 @@ module OrigenARMDebug
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# Memory Access Port (MEM-AP)
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class MemAP < AP
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# Latency to write a memory resource
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attr_accessor :latency
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# Wait states for data to be transferred from Memory Resource to DRW on
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# read request. Should be added to apreg_access_wait for complete transaction
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# time of memory read (read data path: memory->drw->rdbuff)
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attr_accessor :apmem_access_wait
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def initialize(options = {})
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super
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data/templates/web/index.md.erb
CHANGED
@@ -32,11 +32,6 @@ Include the <code>OrigenARMDebug</code> module in your DUT class, then hook it u
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to the Origen register API via
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<code>read_register</code> and <code>write_register</code> methods.
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-
The <code>OrigenARMDebug</code> module also provides additional methods to use the ARM Debug protocol including:
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accessing device memory, accessing core and floating point registers (cortex M cores only),
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entering/exiting debug mode (cortex M cores only), setting the PC (cortex M cores only)
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and stepping through code (cortex M cores only).
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-
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You must also include a compatible physical driver depending on what debug
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interface your device has, one of the following can be used:
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@@ -57,7 +52,10 @@ class DUT
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reg.bits 7..0, :lower_byte
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end
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-
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# Simple example using default wait-states and latency:
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# mem_ap: APSEL = 0x00 (base_address[31:24])
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# mem2_ap: APSEL = 0x01 (base_address[31:24])
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sub_block :arm_debug, class_name: 'OrigenARMDebug::DAP', mem_aps: { mem_ap: 0x00000000, mem2_ap: 0x01000000 }
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end
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# Hook the ARMDebug module into the register API, any register read
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@@ -75,7 +73,7 @@ end
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DUT.new.myreg.write!(0x55AA) # => Will generate the required vectors using the ARM debug protocol
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~~~
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-
You can
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You can access the lower-level API using conventional Origen register transactions:
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~~~ruby
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arm_debug.sw_dp.idcode.read!(0x2BA01477)
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@@ -88,6 +86,91 @@ arm_debug.sw_dp.select.write!(0) # Select AHB-AP, bank 0
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arm_debug.ahb_ap.csw.write!(0x23000052)
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~~~
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You can also adjust the intermediate wait-states and latency parameters:
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* [AP.apreg_access_wait](http://origen-sdk.org/arm_debug/api/OrigenARMDebug/AP.html#apreg_access_wait-instance_method)
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* [MemAP.apmem_access_wait](http://origen-sdk.org/arm_debug/api/OrigenARMDebug/MemAP.html#apmem_access_wait-instance_method)
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* [MemAP.latency](http://origen-sdk.org/arm_debug/api/OrigenARMDebug/MemAP.html#latency-instance_method)
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~~~ruby
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# Assuming ahb_ap has been previously defined
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dut.arm_debug.ahb_ap.apmem_access_wait = 16
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dut.arm_debug.ahb_ap.apreg_access_wait = 12
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dut.arm_debug.ahb_ap.latency = 8
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~~~
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### Company Customization
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It may be the case that your application needs additional, customized Access Ports (AP) which are allowed but
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not defined by the standard ARM Debug Interface. The following example shows how you can use the generic AP
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class as a starting point and add extra registers as defined by your specific implementation.
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~~~ruby
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require 'origen_arm_debug'
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module ARMDebugCOMPANY
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# New AP class inherited from generic AP class provided by origen_arm_debug
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class CustomAP < OrigenARMDebug::AP
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# Initialize AP parameters and registers
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def initialize(options = {})
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super
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instantiate_registers(options)
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# Standard AP-register latency for most devices. Can be overriden by
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# top-level if necessary
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@apreg_access_wait = 8
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end
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# Add example registers associated with CustomAP.
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#
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# Custom registers can also be added by ARMDebug owner with add_reg or
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# overloading entire instantiate_registers methd
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#
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# Ex: arm_debug.company_ap.add_reg(:custom_reg_3, 0x08)
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def instantiate_registers(options = {})
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add_reg :custom_reg_1, 0x00
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add_reg :custom_reg_2, 0x04
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end
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end
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end
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class DUT
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include Origen::TopLevel
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include ARMDebugCOMPANY
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# Also include the required physical driver, JTAG in this example
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include OrigenJTAG
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def initialize
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reg :myreg, 0x0012, size: 16 do |reg|
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reg.bits 15..8, :upper_byte
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reg.bits 7..0, :lower_byte
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end
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# Some standard AP parameters values
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std_memap_config = { latency: 16, apreg_access_wait: 8, apmem_access_wait: 8, csw_reset: 0x23000040 }
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# 2 MemAPs using standard parameters (above)
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mem_aps = {
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mem_ap_0: { base_address: 0x00000000 }.merge(std_memap_config), # AP Select = 0x00
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mem_ap_1: { base_address: 0x01000000 }.merge(std_memap_config), # AP Select = 0x01
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}
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# Add Company-Customized AP class @ APSEL = 0x04
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custom_ap = {
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company_ap: { class_name: 'ARMDebugCOMPANY::CustomAP', base_address: 0x04000000, apreg_access_wait: 8 }
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}
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sub_block :arm_debug, class_name: 'OrigenARMDebug::DAP',
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base_address: 0,
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mem_aps: mem_aps,
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aps: custom_ap
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end
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end
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DUT.new.arm_debug.company_ap.custom_reg_1.write!(0x55AA)
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~~~
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### How To Setup a Development Environment
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[Clone the repository from Github](https://github.com/Origen-SDK/origen_arm_debug).
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metadata
CHANGED
@@ -1,14 +1,14 @@
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1
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--- !ruby/object:Gem::Specification
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name: origen_arm_debug
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version: !ruby/object:Gem::Version
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version: 1.0.
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version: 1.0.2
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platform: ruby
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authors:
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- Ronnie Lajaunie
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autorequire:
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bindir: bin
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cert_chain: []
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date: 2017-
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date: 2017-11-16 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: origen
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@@ -34,16 +34,22 @@ dependencies:
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name: origen_jtag
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requirement: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: '0.17'
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- - ">="
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.17.0
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: '0.17'
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- - ">="
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.17.0
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- !ruby/object:Gem::Dependency
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name: origen_swd
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requirement: !ruby/object:Gem::Requirement
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@@ -100,7 +106,7 @@ files:
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- templates/web/release_notes.md.erb
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homepage: http://origen-sdk.org/origen_arm_debug
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licenses:
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-
-
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- MIT
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metadata: {}
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post_install_message:
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rdoc_options: []
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