origen_arm_debug 1.0.1 → 1.0.2

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA1:
-  metadata.gz: 10a26d1f0559e342aac9aa18777bb2bc3f04b9ff
-  data.tar.gz: acbe130cdb99f062be4629eed0ab73569b960928
+  metadata.gz: e5dd246d4525d4ced61bb06b8bccca56084e3ed9
+  data.tar.gz: ef1eaa8501694c28aa03227326a2da6cf2e3c9b2
 SHA512:
-  metadata.gz: d400af4575b1daa231314c17391e13aeb937b04bb066e95e229917ea909a113090938f95f8c9194f66642abff9be001da811a535d1b87eecabbf4d24b1d5bbe0
-  data.tar.gz: 53b6447b770c98bd639ed62f34fe13d39c60e32c9414e06057ecce46995ed3ff80e100b768ffe95077c3bea320eadd15cebdd467d9f440216932a9f0124ed3ac
+  metadata.gz: 3d194a9455d7c34f0dfa0bf366f1aaa31e094f0eb470d3c209557faa4651a7edd70d8e1293630984c4a7d9b6eb73588410c80a446bc9532dad04c272d30e54af
+  data.tar.gz: cec545de10b7f3bbe7f2c93b7f1c6053b074c583e3b42f24f8ca38c197decfd4e0b71e50fb407359ee6c317d267225138fedce4cb29f5eaaa550ee30cd158285

data/config/version.rb

@@ -1,7 +1,7 @@
 module OrigenARMDebug
   MAJOR = 1
   MINOR = 0
-  BUGFIX = 1
+  BUGFIX = 2
   DEV = nil
 
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')

data/lib/origen_arm_debug/ap.rb

@@ -4,7 +4,7 @@ module OrigenARMDebug
     include Origen::Model
 
     # Wait states for data to be transferred from AP-Reg to RDBUFF (on read)
-    attr_reader :apreg_access_wait
+    attr_accessor :apreg_access_wait
 
     def initialize(options = {})
       @apreg_access_wait = options[:apreg_access_wait] || 0

data/lib/origen_arm_debug/jtag_dp_controller.rb

@@ -95,6 +95,7 @@ module OrigenARMDebug
               dr[0].write(1)
               dr[2..1].write(rdbuff.offset >> 2)
               dr[34..3].copy_all(reg)
+              options[:mask] = options[:mask] << 3 unless options[:mask].nil?
               dut.jtag.read_dr(dr, options)
 
             else
@@ -131,6 +132,7 @@ module OrigenARMDebug
         dr[0].write(1)
         dr[2..1].write(rdbuff.offset >> 2)
         dr[34..3].copy_all(reg)
+        options[:mask] = options[:mask] << 3 unless options[:mask].nil?
         ir.write!(0b1010)
         dut.jtag.read_dr(dr, options)
       end

data/lib/origen_arm_debug/mem_ap.rb

@@ -2,12 +2,12 @@ module OrigenARMDebug
   # Memory Access Port (MEM-AP)
   class MemAP < AP
     # Latency to write a memory resource
-    attr_reader :latency
+    attr_accessor :latency
 
     # Wait states for data to be transferred from Memory Resource to DRW on
     #   read request.  Should be added to apreg_access_wait for complete transaction
     #   time of memory read (read data path: memory->drw->rdbuff)
-    attr_reader :apmem_access_wait
+    attr_accessor :apmem_access_wait
 
     def initialize(options = {})
       super

data/templates/web/index.md.erb

@@ -32,11 +32,6 @@ Include the <code>OrigenARMDebug</code> module in your DUT class, then hook it u
 to the Origen register API via
 <code>read_register</code> and <code>write_register</code> methods.
 
-The <code>OrigenARMDebug</code> module also provides additional methods to use the ARM Debug protocol including:
-accessing device memory, accessing core and floating point registers (cortex M cores only),
-entering/exiting debug mode (cortex M cores only), setting the PC (cortex M cores only)
-and stepping through code (cortex M cores only).
-
 You must also include a compatible physical driver depending on what debug
 interface your device has, one of the following can be used:
 
@@ -57,7 +52,10 @@ class DUT
       reg.bits 7..0,  :lower_byte
     end
     
-    sub_block :arm_debug, class_name: "OrigenARMDebug::DAP", mem_aps: { mem_ap: 0x00000000, mem2_ap: 0x01000000 }                           
+    # Simple example using default wait-states and latency:
+    #   mem_ap:  APSEL = 0x00 (base_address[31:24])
+    #   mem2_ap: APSEL = 0x01 (base_address[31:24])
+    sub_block :arm_debug, class_name: 'OrigenARMDebug::DAP', mem_aps: { mem_ap: 0x00000000, mem2_ap: 0x01000000 }                           
   end
 
   # Hook the ARMDebug module into the register API, any register read
@@ -75,7 +73,7 @@ end
 DUT.new.myreg.write!(0x55AA)  # => Will generate the required vectors using the ARM debug protocol
 ~~~
 
-You can also access the lower-level API using conventional Origen register transactions:
+You can access the lower-level API using conventional Origen register transactions:
 
 ~~~ruby
 arm_debug.sw_dp.idcode.read!(0x2BA01477)
@@ -88,6 +86,91 @@ arm_debug.sw_dp.select.write!(0)              # Select AHB-AP, bank 0
 arm_debug.ahb_ap.csw.write!(0x23000052)
 ~~~
 
+You can also adjust the intermediate wait-states and latency parameters:
+
+* [AP.apreg_access_wait](http://origen-sdk.org/arm_debug/api/OrigenARMDebug/AP.html#apreg_access_wait-instance_method)
+* [MemAP.apmem_access_wait](http://origen-sdk.org/arm_debug/api/OrigenARMDebug/MemAP.html#apmem_access_wait-instance_method)
+* [MemAP.latency](http://origen-sdk.org/arm_debug/api/OrigenARMDebug/MemAP.html#latency-instance_method)
+
+~~~ruby
+# Assuming ahb_ap has been previously defined
+dut.arm_debug.ahb_ap.apmem_access_wait = 16
+dut.arm_debug.ahb_ap.apreg_access_wait = 12
+dut.arm_debug.ahb_ap.latency = 8
+~~~
+
+### Company Customization
+
+It may be the case that your application needs additional, customized Access Ports (AP) which are allowed but
+not defined by the standard ARM Debug Interface.  The following example shows how you can use the generic AP
+class as a starting point and add extra registers as defined by your specific implementation.
+
+~~~ruby
+require 'origen_arm_debug'
+module ARMDebugCOMPANY
+  # New AP class inherited from generic AP class provided by origen_arm_debug
+  class CustomAP < OrigenARMDebug::AP
+    # Initialize AP parameters and registers
+    def initialize(options = {})
+      super
+
+      instantiate_registers(options)
+
+      # Standard AP-register latency for most devices.  Can be overriden by
+      #   top-level if necessary
+      @apreg_access_wait = 8
+    end
+
+    # Add example registers associated with CustomAP.
+    # 
+    # Custom registers can also be added by ARMDebug owner with add_reg or
+    #   overloading entire instantiate_registers methd
+    #
+    #   Ex:  arm_debug.company_ap.add_reg(:custom_reg_3, 0x08)
+    def instantiate_registers(options = {})
+      add_reg :custom_reg_1, 0x00
+      add_reg :custom_reg_2, 0x04
+    end
+  end
+end
+
+
+class DUT
+  include Origen::TopLevel
+  include ARMDebugCOMPANY
+
+  # Also include the required physical driver, JTAG in this example
+  include OrigenJTAG
+
+  def initialize
+    reg :myreg, 0x0012, size: 16 do |reg|
+      reg.bits 15..8, :upper_byte
+      reg.bits 7..0,  :lower_byte
+    end
+    
+    # Some standard AP parameters values
+    std_memap_config = { latency: 16, apreg_access_wait: 8, apmem_access_wait: 8, csw_reset: 0x23000040 }  
+
+    # 2 MemAPs using standard parameters (above)
+    mem_aps = {
+      mem_ap_0: { base_address: 0x00000000 }.merge(std_memap_config),    # AP Select = 0x00
+      mem_ap_1: { base_address: 0x01000000 }.merge(std_memap_config),    # AP Select = 0x01
+    }
+
+    # Add Company-Customized AP class @ APSEL = 0x04
+    custom_ap = {
+      company_ap:  { class_name: 'ARMDebugCOMPANY::CustomAP', base_address: 0x04000000, apreg_access_wait: 8 }
+    }
+
+    sub_block :arm_debug, class_name: 'OrigenARMDebug::DAP',
+                          base_address: 0,
+                          mem_aps: mem_aps,
+                          aps: custom_ap
+  end
+end
+DUT.new.arm_debug.company_ap.custom_reg_1.write!(0x55AA)
+~~~
+
 ### How To Setup a Development Environment
 
 [Clone the repository from Github](https://github.com/Origen-SDK/origen_arm_debug).

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_arm_debug
 version: !ruby/object:Gem::Version
-  version: 1.0.1
+  version: 1.0.2
 platform: ruby
 authors:
 - Ronnie Lajaunie
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2017-06-08 00:00:00.000000000 Z
+date: 2017-11-16 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen
@@ -34,16 +34,22 @@ dependencies:
   name: origen_jtag
   requirement: !ruby/object:Gem::Requirement
     requirements:
+    - - "~>"
+      - !ruby/object:Gem::Version
+        version: '0.17'
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.15.0
+        version: 0.17.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
+    - - "~>"
+      - !ruby/object:Gem::Version
+        version: '0.17'
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.15.0
+        version: 0.17.0
 - !ruby/object:Gem::Dependency
   name: origen_swd
   requirement: !ruby/object:Gem::Requirement
@@ -100,7 +106,7 @@ files:
 - templates/web/release_notes.md.erb
 homepage: http://origen-sdk.org/origen_arm_debug
 licenses:
-- LGPL-3
+- MIT
 metadata: {}
 post_install_message: 
 rdoc_options: []