origen_arm_debug 1.1.1 → 1.2.0
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- checksums.yaml +5 -5
- data/config/boot.rb +2 -0
- data/config/commands.rb +15 -11
- data/config/version.rb +2 -3
- data/lib/origen_arm_debug/dap.rb +4 -2
- data/lib/origen_arm_debug/dap_controller.rb +30 -1
- data/lib/origen_arm_debug/dp_controller.rb +8 -2
- data/lib/origen_arm_debug/jtag_dp.rb +12 -0
- data/lib/origen_arm_debug/mem_ap.rb +40 -9
- data/lib/origen_arm_debug/mem_ap_controller.rb +7 -1
- data/lib/origen_arm_debug/sw_dp.rb +9 -0
- data/lib/origen_arm_debug_dev/dut_dual_dp.rb +34 -0
- data/lib/origen_arm_debug_dev/dut_jtag_axi.rb +35 -0
- data/pattern/workout.rb +57 -1
- data/templates/web/index.md.erb +3 -2
- metadata +5 -4
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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-
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metadata.gz:
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data.tar.gz:
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SHA256:
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metadata.gz: 292e4be7741df68524ba13a6af2058a9ca209688ddf12ca19c63a1e2e795135c
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4
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+
data.tar.gz: 58fd3ee8010c9cba1bd4675896fd8a5aa0d9e579113aaeac7ceb30c5039467ac
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SHA512:
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-
metadata.gz:
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data.tar.gz:
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metadata.gz: 880aef44c21b1a5030223b9d7a0155f0284109c9dcc8c711bdab5e95e0dc8f347a4920d93cfb993dcc51e7104fa91b740699c504a3d797a7c3e12252739357e8
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7
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+
data.tar.gz: 15f565c00daa931914a1b9be94894810a2bdccbd19e1553a013dc1234d1cb01b76484e2bc7e47697cb5ee3307fd03ff7e7484577171120579c35aa37e5e392b5
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data/config/boot.rb
CHANGED
data/config/commands.rb
CHANGED
@@ -17,19 +17,23 @@ aliases ={
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17
17
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# Now branch to the specific task code
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18
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case @command
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20
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-
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-
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-
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+
when "specs"
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+
require "rspec"
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+
exit RSpec::Core::Runner.run(['spec'])
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23
23
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|
24
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-
when "examples"
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24
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+
when "examples", "test"
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25
25
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Origen.load_application
|
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26
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status = 0
|
27
27
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|
28
28
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# Pattern generator tests
|
29
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-
ARGV = %w(workout -t jtag -e j750 -r approved)
|
29
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+
ARGV = %w(workout -t jtag.rb -e j750 -r approved)
|
30
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+
load "#{Origen.top}/lib/origen/commands/generate.rb"
|
31
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+
ARGV = %w(workout -t jtag_axi.rb -e j750 -r approved)
|
30
32
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load "#{Origen.top}/lib/origen/commands/generate.rb"
|
31
33
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ARGV = %w(workout -t swd -e j750 -r approved)
|
32
34
|
load "#{Origen.top}/lib/origen/commands/generate.rb"
|
35
|
+
ARGV = %w(workout -t dual_dp -e j750 -r approved)
|
36
|
+
load "#{Origen.top}/lib/origen/commands/generate.rb"
|
33
37
|
ARGV = %w(workout -t config_test -e j750 -r approved/config_test)
|
34
38
|
load "#{Origen.top}/lib/origen/commands/generate.rb"
|
35
39
|
|
@@ -44,12 +48,12 @@ when "examples" # , "test"
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|
44
48
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status = 1
|
45
49
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end
|
46
50
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puts
|
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-
|
48
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-
|
49
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-
|
50
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-
|
51
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-
|
52
|
-
|
51
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+
if @command == "test"
|
52
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+
Origen.app.unload_target!
|
53
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+
require "rspec"
|
54
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+
result = RSpec::Core::Runner.run(['spec'])
|
55
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+
status = status == 1 ? 1 : result
|
56
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+
end
|
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exit status
|
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|
55
59
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# Always leave an else clause to allow control to fall back through to the
|
data/config/version.rb
CHANGED
data/lib/origen_arm_debug/dap.rb
CHANGED
@@ -70,11 +70,13 @@ module OrigenARMDebug
|
|
70
70
|
#
|
71
71
|
def add_ap(name, options)
|
72
72
|
domain name.to_sym
|
73
|
+
# class name is deleted from options in sub_block call
|
74
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+
class_name = options[:class_name]
|
73
75
|
ap = sub_block(name.to_sym, options)
|
74
76
|
|
75
|
-
if
|
77
|
+
if class_name == 'MemAP'
|
76
78
|
mem_aps << ap
|
77
|
-
elsif
|
79
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+
elsif class_name == 'JTAGAP'
|
78
80
|
jtag_aps << ap
|
79
81
|
else
|
80
82
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ext_aps << ap
|
@@ -3,12 +3,41 @@ module OrigenARMDebug
|
|
3
3
|
include Origen::Controller
|
4
4
|
include Helpers
|
5
5
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|
6
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+
attr_accessor :dp
|
7
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+
|
6
8
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# Returns the currently enabled DP (or the only DP if only one
|
7
9
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# of them).
|
8
10
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# If no dp is enabled before calling this, it will choose the
|
9
11
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# SW_DP by default.
|
10
12
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def dp
|
11
|
-
dps.first
|
13
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+
@dp ||= dps.first
|
14
|
+
end
|
15
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+
|
16
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+
def set_dp(dp)
|
17
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+
if dps.size > 1
|
18
|
+
if dp == :swd || dp == :sw
|
19
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+
@dp = dps.first
|
20
|
+
elsif dp == :jtag
|
21
|
+
@dp = dps.last
|
22
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+
else
|
23
|
+
Origen.log.error 'origen_arm_debug: Only SWD and JTAG DP available'
|
24
|
+
end
|
25
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+
else
|
26
|
+
Origen.log.warn 'origen_arm_debug: Ignoring set_dp call since only one DP is available'
|
27
|
+
end
|
28
|
+
end
|
29
|
+
|
30
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+
def reset_dp
|
31
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+
@dp = nil
|
32
|
+
end
|
33
|
+
|
34
|
+
def is_jtag?
|
35
|
+
dp.is_jtag?
|
36
|
+
end
|
37
|
+
|
38
|
+
def is_swd?
|
39
|
+
dp.is_swd?
|
12
40
|
end
|
41
|
+
alias_method :is_sw?, :is_swd?
|
13
42
|
end
|
14
43
|
end
|
@@ -9,8 +9,14 @@ module OrigenARMDebug
|
|
9
9
|
# @api private
|
10
10
|
def select_ap_reg(reg)
|
11
11
|
address = reg.address & 0xFFFF_FFF0
|
12
|
-
|
13
|
-
|
12
|
+
apsel = (reg.address & 0xFF00_0000) >> 24
|
13
|
+
apbanksel = (reg.address & 0xF0) >> 4
|
14
|
+
# if model.select.data != address
|
15
|
+
if model.select.apsel.data != apsel || model.select.apbanksel.data != apbanksel
|
16
|
+
model.select.write! do |r|
|
17
|
+
r.apsel.write apsel
|
18
|
+
r.apbanksel.write apbanksel
|
19
|
+
end
|
14
20
|
end
|
15
21
|
end
|
16
22
|
end
|
@@ -48,9 +48,12 @@ module OrigenARMDebug
|
|
48
48
|
|
49
49
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reg :select, 0x8 do |reg|
|
50
50
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reg.bit 31..24, :apsel
|
51
|
+
reg.bit 23..8, :reserved
|
51
52
|
reg.bit 7..4, :apbanksel
|
52
53
|
end
|
53
54
|
|
55
|
+
select.write options[:dp_select_reset] if options[:dp_select_reset]
|
56
|
+
|
54
57
|
add_reg :rdbuff, 0xC, access: :ro, reset: 0
|
55
58
|
|
56
59
|
reg :abort, options[:abort_select], access: :wo do |reg|
|
@@ -65,5 +68,14 @@ module OrigenARMDebug
|
|
65
68
|
def abort
|
66
69
|
reg(:abort)
|
67
70
|
end
|
71
|
+
|
72
|
+
def is_jtag?
|
73
|
+
true
|
74
|
+
end
|
75
|
+
|
76
|
+
def is_swd?
|
77
|
+
false
|
78
|
+
end
|
79
|
+
alias_method :is_sw?, :is_swd?
|
68
80
|
end
|
69
81
|
end
|
@@ -14,21 +14,52 @@ module OrigenARMDebug
|
|
14
14
|
# For SWD, this is the wait states in between setting the AP, initiating and completing a dummy read, and beginning the actual read transaction.
|
15
15
|
attr_accessor :apacc_wait_states
|
16
16
|
|
17
|
+
# Boolean value indicating whether this is an AXI-AP
|
18
|
+
attr_accessor :is_axi
|
19
|
+
|
20
|
+
# Value to be read from DP CSW for interleaved status checks (debug feature)
|
21
|
+
attr_accessor :csw_status_check
|
22
|
+
|
23
|
+
# Boolean value indicating whether to interleave status checks during transactions (debug feature)
|
24
|
+
attr_accessor :interleave_status_check
|
25
|
+
|
17
26
|
def initialize(options = {})
|
18
27
|
super
|
19
28
|
|
29
|
+
@is_axi = options[:is_axi]
|
30
|
+
@csw_status_check = options[:csw_status_check]
|
31
|
+
@interleave_status_check = options[:interleave_status_check]
|
32
|
+
|
20
33
|
@latency = options[:latency] || 0
|
21
34
|
@apmem_access_wait = options[:apmem_access_wait] || 0
|
22
35
|
|
23
|
-
|
24
|
-
reg
|
25
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-
|
26
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-
|
27
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-
|
28
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-
|
29
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-
|
30
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-
|
31
|
-
|
36
|
+
if @is_axi
|
37
|
+
reg :csw, 0x0 do |reg|
|
38
|
+
reg.bit 31, :reserved
|
39
|
+
reg.bit 30..28, :prot, res: 3
|
40
|
+
reg.bit 27..24, :cache
|
41
|
+
reg.bit 23, :spiden
|
42
|
+
reg.bit 22..15, :reserved2
|
43
|
+
reg.bit 14..13, :domain, res: 3
|
44
|
+
reg.bit 12, :ace_enable
|
45
|
+
reg.bit 11..8, :mode
|
46
|
+
reg.bit 7, :tr_in_prog
|
47
|
+
reg.bit 6, :dbg_status, res: 1
|
48
|
+
reg.bit 5..4, :addr_inc
|
49
|
+
reg.bit 3, :reserved3
|
50
|
+
reg.bit 2..0, :size, res: 2
|
51
|
+
end
|
52
|
+
else
|
53
|
+
reg :csw, 0x0 do |reg|
|
54
|
+
reg.bit 31, :dbg_sw_enable
|
55
|
+
reg.bit 30..24, :prot
|
56
|
+
reg.bit 23, :spiden
|
57
|
+
reg.bit 11..8, :mode
|
58
|
+
reg.bit 7, :tr_in_prog
|
59
|
+
reg.bit 6, :device_en
|
60
|
+
reg.bit 5..4, :addr_inc
|
61
|
+
reg.bit 2..0, :size
|
62
|
+
end
|
32
63
|
end
|
33
64
|
reg(:csw).write(options[:csw_reset]) if options[:csw_reset]
|
34
65
|
|
@@ -18,11 +18,13 @@ module OrigenARMDebug
|
|
18
18
|
log "Write MEM-AP (#{model.name}) address #{addr.to_hex}: #{data.to_hex}" do
|
19
19
|
csw.bits(:size).write!(0b010) if csw.bits(:size).data != 0b010
|
20
20
|
tar.write!(addr) unless tar.data == addr
|
21
|
+
parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
|
21
22
|
drw.reset
|
22
23
|
drw.overlay(nil)
|
23
24
|
drw.copy_all(reg_or_val)
|
24
25
|
drw.write!(options)
|
25
26
|
latency.cycles
|
27
|
+
parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
|
26
28
|
end
|
27
29
|
increment_addr
|
28
30
|
end
|
@@ -43,14 +45,18 @@ module OrigenARMDebug
|
|
43
45
|
csw.bits(:size).write!(0b010) if csw.bits(:size).data != 0b010
|
44
46
|
unless tar.data == addr
|
45
47
|
tar.write!(addr)
|
48
|
+
parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
|
46
49
|
end
|
47
50
|
drw.reset
|
48
51
|
drw.overlay(nil)
|
49
52
|
drw.copy_all(reg_or_val)
|
50
53
|
parent.dp.read_register(drw, options.merge(apacc_wait_states: (apmem_access_wait + apreg_access_wait)))
|
54
|
+
parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
|
51
55
|
end
|
52
56
|
increment_addr
|
53
57
|
end
|
58
|
+
|
59
|
+
reg_or_val.clear_flags if reg_or_val.respond_to?(:clear_flags)
|
54
60
|
end
|
55
61
|
|
56
62
|
def address_increment_enabled?
|
@@ -74,7 +80,7 @@ module OrigenARMDebug
|
|
74
80
|
|
75
81
|
# Reset tar if just crossed a 1kB boundary
|
76
82
|
if address_increment_enabled? && (tar[9..0].data == 0)
|
77
|
-
tar.
|
83
|
+
tar.write(0)
|
78
84
|
end
|
79
85
|
end
|
80
86
|
end
|
@@ -0,0 +1,34 @@
|
|
1
|
+
module OrigenARMDebugDev
|
2
|
+
# Simple JTAG-specific dut model that inherits from protocol-agnostic DUT model
|
3
|
+
class DUAL_DP_DUT < DUT
|
4
|
+
include OrigenSWD
|
5
|
+
include OrigenJTAG
|
6
|
+
|
7
|
+
# Adds jtag-required pins to the simple dut model
|
8
|
+
# Returns nothing.
|
9
|
+
def initialize(options = {})
|
10
|
+
super
|
11
|
+
add_pin :tclk
|
12
|
+
add_pin :tdi
|
13
|
+
add_pin :tdo
|
14
|
+
add_pin :tms
|
15
|
+
add_pin :trst
|
16
|
+
add_pin :swd_clk
|
17
|
+
add_pin :swd_dio
|
18
|
+
|
19
|
+
options[:class_name] = 'OrigenARMDebug::DAP'
|
20
|
+
options[:mem_aps] = {
|
21
|
+
mem_ap: {
|
22
|
+
base_address: 0x00000000,
|
23
|
+
latency: 16,
|
24
|
+
apreg_access_wait: 8,
|
25
|
+
apmem_access_wait: 8,
|
26
|
+
csw_reset: 0x23000040
|
27
|
+
},
|
28
|
+
mdm_ap: 0x01000000
|
29
|
+
}
|
30
|
+
# Specify (customize) ARM Debug implementation details
|
31
|
+
sub_block :arm_debug, options
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
@@ -0,0 +1,35 @@
|
|
1
|
+
module OrigenARMDebugDev
|
2
|
+
# Simple JTAG-specific dut model that inherits from protocol-agnostic DUT model
|
3
|
+
class JTAG_AXI_DUT < DUT
|
4
|
+
include OrigenJTAG
|
5
|
+
|
6
|
+
# Adds jtag-required pins to the simple dut model
|
7
|
+
# Returns nothing.
|
8
|
+
def initialize(options = {})
|
9
|
+
super
|
10
|
+
add_pin :tclk
|
11
|
+
add_pin :tdi
|
12
|
+
add_pin :tdo
|
13
|
+
add_pin :tms
|
14
|
+
add_pin :trst
|
15
|
+
add_pin :swd_clk
|
16
|
+
add_pin :swd_dio
|
17
|
+
|
18
|
+
options[:class_name] = 'OrigenARMDebug::DAP'
|
19
|
+
options[:mem_aps] = {
|
20
|
+
mem_ap: {
|
21
|
+
base_address: 0x00000000,
|
22
|
+
latency: 16,
|
23
|
+
apreg_access_wait: 8,
|
24
|
+
apmem_access_wait: 8,
|
25
|
+
is_axi: true,
|
26
|
+
csw_reset: 0x1080_6002
|
27
|
+
},
|
28
|
+
mdm_ap: 0x01000000
|
29
|
+
}
|
30
|
+
options[:dp_select_reset] = 0xC2_0D00
|
31
|
+
# Specify (customize) ARM Debug implementation details
|
32
|
+
sub_block :arm_debug, options
|
33
|
+
end
|
34
|
+
end
|
35
|
+
end
|
data/pattern/workout.rb
CHANGED
@@ -1,4 +1,12 @@
|
|
1
|
-
|
1
|
+
if Origen.app.target.name == 'dual_dp'
|
2
|
+
pattern_name = 'workout_dual_dp'
|
3
|
+
elsif Origen.app.target.name == 'jtag_axi'
|
4
|
+
pattern_name = 'workout_jtag_axi'
|
5
|
+
else
|
6
|
+
pattern_name = "workout_#{dut.arm_debug.dp.name}"
|
7
|
+
end
|
8
|
+
|
9
|
+
Pattern.create name: pattern_name do
|
2
10
|
|
3
11
|
ss "Tests of direct DP API"
|
4
12
|
dp = dut.arm_debug.dp
|
@@ -58,4 +66,52 @@ Pattern.create name: "workout_#{dut.arm_debug.dp.name}" do
|
|
58
66
|
dut.reg(:test).data = 0x0000FF01
|
59
67
|
dut.reg(:test)[0].read!
|
60
68
|
|
69
|
+
if Origen.app.target.name == 'dual_dp'
|
70
|
+
ss "SWITCHING DP"
|
71
|
+
dut.arm_debug.set_dp(:jtag)
|
72
|
+
|
73
|
+
ss "Test write register, should write value 0xFF01"
|
74
|
+
dut.reg(:test).write!(0x0000FF01)
|
75
|
+
|
76
|
+
ss "Test write register with overlay, no subroutine"
|
77
|
+
dut.reg(:test).overlay('write_overlay')
|
78
|
+
dut.reg(:test).write!(0x0000FF01, no_subr: true)
|
79
|
+
dut.reg(:test).overlay(nil)
|
80
|
+
|
81
|
+
ss "Test write register with overlay, use subroutine if available"
|
82
|
+
dut.reg(:test).overlay('write_overlay_subr')
|
83
|
+
dut.reg(:test).write!(0x0000FF01)
|
84
|
+
dut.reg(:test).overlay(nil)
|
85
|
+
|
86
|
+
ss "Test read register, should read value 0x0000FF01"
|
87
|
+
dut.reg(:test).read!
|
88
|
+
|
89
|
+
ss "Test read register, with overlay, no subroutine, should read value 0x0000FF01"
|
90
|
+
dut.reg(:test).overlay('read_overlay')
|
91
|
+
dut.reg(:test).read!(no_subr: true)
|
92
|
+
dut.reg(:test).overlay(nil)
|
93
|
+
|
94
|
+
ss "Test read register, with overlay, use subroutine if available"
|
95
|
+
dut.reg(:test).overlay('read_overlay_subr')
|
96
|
+
dut.reg(:test).read!
|
97
|
+
dut.reg(:test).overlay(nil)
|
98
|
+
|
99
|
+
ss "Test read register with mask, should read value 0xXXXxxx1"
|
100
|
+
dut.reg(:test).read!(mask: 0x0000_000F)
|
101
|
+
|
102
|
+
ss "Test read register with store"
|
103
|
+
dut.reg(:test).store!
|
104
|
+
|
105
|
+
ss "Test bit level read, should read value 0xXXXxxx1"
|
106
|
+
dut.reg(:test).reset
|
107
|
+
dut.reg(:test).data = 0x0000FF01
|
108
|
+
dut.reg(:test)[0].read!
|
109
|
+
|
110
|
+
ss "RESETTING DP (to default)"
|
111
|
+
dut.arm_debug.reset_dp
|
112
|
+
ss "Test bit level read, should read value 0xXXXxxx1"
|
113
|
+
dut.reg(:test).reset
|
114
|
+
dut.reg(:test).data = 0x0000FF01
|
115
|
+
dut.reg(:test)[0].read!
|
116
|
+
end
|
61
117
|
end
|
data/templates/web/index.md.erb
CHANGED
@@ -52,9 +52,9 @@ class DUT
|
|
52
52
|
|
53
53
|
# Simple example using default wait-states and latency:
|
54
54
|
# mem_ap: APSEL = 0x00 (base_address[31:24])
|
55
|
-
# mem2_ap: APSEL = 0x01 (base_address[31:24])
|
55
|
+
# mem2_ap: APSEL = 0x01 (base_address[31:24], is_axi: true) # is_axi: true for AXI-AP
|
56
56
|
mem_aps = {
|
57
|
-
mem_ap: { base_address: 0x00000000 }
|
57
|
+
mem_ap: { base_address: 0x00000000 },
|
58
58
|
mem2_ap: { base_address: 0x10000000 }
|
59
59
|
}
|
60
60
|
sub_block :arm_debug, class_name: 'OrigenARMDebug::DAP', mem_aps: mem_aps
|
@@ -133,6 +133,7 @@ instantiation_options[:idcode_select] = 0xFE
|
|
133
133
|
instantiation_options[:abort_select] = 0xF8
|
134
134
|
instantiation_options[:dpacc_select] = 0xFA
|
135
135
|
instantiation_options[:apacc_select] = 0xFB
|
136
|
+
instantiation_options[:dp_select_reset] = 0xC2_0D00
|
136
137
|
|
137
138
|
sub_block :arm_debug, instantiation_options
|
138
139
|
~~~
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: origen_arm_debug
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 1.
|
4
|
+
version: 1.2.0
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Ronnie Lajaunie
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date:
|
11
|
+
date: 2022-01-28 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: origen
|
@@ -97,7 +97,9 @@ files:
|
|
97
97
|
- lib/origen_arm_debug/sw_dp.rb
|
98
98
|
- lib/origen_arm_debug/sw_dp_controller.rb
|
99
99
|
- lib/origen_arm_debug_dev/dut.rb
|
100
|
+
- lib/origen_arm_debug_dev/dut_dual_dp.rb
|
100
101
|
- lib/origen_arm_debug_dev/dut_jtag.rb
|
102
|
+
- lib/origen_arm_debug_dev/dut_jtag_axi.rb
|
101
103
|
- lib/origen_arm_debug_dev/dut_swd.rb
|
102
104
|
- pattern/workout.rb
|
103
105
|
- templates/web/index.md.erb
|
@@ -123,8 +125,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
|
|
123
125
|
- !ruby/object:Gem::Version
|
124
126
|
version: 1.8.11
|
125
127
|
requirements: []
|
126
|
-
|
127
|
-
rubygems_version: 2.6.7
|
128
|
+
rubygems_version: 3.1.4
|
128
129
|
signing_key:
|
129
130
|
specification_version: 4
|
130
131
|
summary: Provides an Origen API to perform register read and write operations via
|