origen_arm_debug 0.4.2 → 0.4.3

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checksums.yaml CHANGED
@@ -1,7 +1,7 @@
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data/config/version.rb CHANGED
@@ -1,7 +1,7 @@
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  module OrigenARMDebug
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  MAJOR = 0
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  MINOR = 4
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- BUGFIX = 2
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+ BUGFIX = 3
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  DEV = nil
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  VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
@@ -1,4 +1,9 @@
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  module OrigenARMDebug
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+ # To use this driver the owner model must include the SWD or JTAG protocol drivers:
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+ # include JTAG
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+ # or
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+ # include SWD
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+ #
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  class Driver
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  # Returns the parent object that instantiated the driver, could be
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  # either a DUT object or a protocol abstraction
@@ -16,7 +21,7 @@ module OrigenARMDebug
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  @owner = owner
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  end
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- # Create and/or return the SWJ_DP object with specified protocol
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+ # Create and/or return the SWJ_DP object with specified protocol
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  def swj_dp
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  if owner.respond_to?(:swd)
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  @swj_dp ||= SWJ_DP.new(self, :swd)
@@ -1,4 +1,5 @@
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  module OrigenARMDebug
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+ # Simple JTAG-specific dut model that inherits from protocol-agnostic DUT model
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  class JTAG_DUT < DUT
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  include OrigenJTAG
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  include Origen::Pins
@@ -1,4 +1,5 @@
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  module OrigenARMDebug
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+ # Simple SWD-specific dut model that inherits from protocol-agnostic DUT model
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  class SWD_DUT < DUT
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  include OrigenSWD
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  include Origen::Pins
@@ -1,4 +1,8 @@
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+ 'include rgen'
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  module OrigenARMDebug
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+ # Object that defines the API necessary to perform MEM-AP transactions. Requires
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+ # a top-level protocol be defined as well as a top-level instantiation of an
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+ # SWJ-DP object.
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  class MemAP
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  # ARM Debug Interface v5.1
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  MEM_ADDR_CSW = 0x00000000
@@ -40,6 +44,25 @@ module OrigenARMDebug
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  end
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  alias_method :dp, :debug_port
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+ # Output some instance-specific information
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+ def inspect
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+ Origen.log.info '=' * 30
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+ Origen.log.info ' MEM-AP INFO'
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+ Origen.log.info " name: #{@name}"
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+ Origen.log.info " base address: 0x#{@base_address.to_hex}"
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+ Origen.log.info ''
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+ Origen.log.debug " csw_reg_addr = 0x#{csw_reg_addr.to_hex}"
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+ Origen.log.debug " tar_reg_addr = 0x#{tar_reg_addr.to_hex}"
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+ Origen.log.debug " drw_reg_addr = 0x#{drw_reg_addr.to_hex}"
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+ Origen.log.debug " bd0_reg_addr = 0x#{bd0_reg_addr.to_hex}"
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+ Origen.log.debug " bd1_reg_addr = 0x#{bd1_reg_addr.to_hex}"
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+ Origen.log.debug " bd2_reg_addr = 0x#{bd2_reg_addr.to_hex}"
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+ Origen.log.debug " bd3_reg_addr = 0x#{bd3_reg_addr.to_hex}"
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+ Origen.log.debug " cfg_reg_addr = 0x#{cfg_reg_addr.to_hex}"
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+ Origen.log.debug " base_reg_addr = 0x#{base_reg_addr.to_hex}"
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+ Origen.log.debug " idr_reg_addr = 0x#{idr_reg_addr.to_hex}"
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+ end
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+
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  # -----------------------------------------------------------------------------
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  # User API
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  # -----------------------------------------------------------------------------
@@ -350,7 +373,7 @@ module OrigenARMDebug
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  end
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  # Returns address of BD0 register for this mem-ap instance
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- def bdo_reg_addr
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+ def bd0_reg_addr
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  MEM_ADDR_BD0 + @base_address
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  end
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@@ -1,12 +1,21 @@
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  module OrigenARMDebug
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+ # Object that defines API for performing Debug AP transations using SWD or JTAG
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  class SWJ_DP
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  include Origen::Registers
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  # Returns the parent object that instantiated the driver, could be
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  # either a DUT object or a protocol abstraction
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  attr_reader :owner
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+
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+ # Protocol implemented at the top-level (i.e. SWD or JTAG)
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  attr_reader :imp
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+
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+ # Customizable delay for DUT-specific required cycles for write_ap transaction
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+ # to complete
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  attr_accessor :write_ap_dly
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+
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+ # Customizable delay for DUT-specific required cycles for acc_access transaction
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+ # to complete
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  attr_accessor :acc_access_dly
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  # Initialize class variables
@@ -356,6 +365,9 @@ module OrigenARMDebug
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  $tester.cycle(repeat: @acc_access_dly)
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  end
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+ # Returns the address of the register based on the name (string) of the register
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+ #
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+ # @param [String] name Name of the register
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  def get_dp_addr(name)
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  case name
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  when 'IDCODE' then return 0x0
@@ -369,11 +381,18 @@ module OrigenARMDebug
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  end
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  end
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+ # Writes to the JTAG instruction regsiter in order to perform a transaction on the given Register
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+ #
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+ # @param [String] name Name of the register to be interacted with
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  def set_ir(name)
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  new_ir = get_ir_code(name)
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  jtag.write_ir(new_ir, size: 4)
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  end
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+ # Returns the value to be written to the JTAG instruction regsiter in order to perform
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+ # a transaction on the given Register
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+ #
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+ # @param [String] name Name of the register to be interacted with
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  def get_ir_code(name)
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  case name
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  when 'IDCODE' then return 0b1110 # JTAGC_ARM_IDCODE
@@ -389,6 +408,11 @@ module OrigenARMDebug
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  0
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  end
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+ # Method to select an Access Port (AP) by writing to the SELECT register in the Debug Port
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+ #
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+ # @param [Integer] addr Address to be written to the SELECT register. It's value
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+ # will determine which Access Port is selected.
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+ # @param [Hash] options Options to customize the operation
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  def set_apselect(addr, options = {})
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  if @imp == :swd
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  addr &= 0xff0000f1
@@ -15,4 +15,7 @@ Pattern.create do
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  $dut.arm_debug.mem_ap.W(0x10000004, 0x55555555)
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  $dut.arm_debug.mem_ap.WR(0x10000004, 0x55555555)
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+ $dut.arm_debug.mem_ap.inspect
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+ $dut.arm_debug.mdm_ap.inspect
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+ $dut.arm_debug.alt_ahbapi.inspect
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  end
metadata CHANGED
@@ -1,14 +1,14 @@
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  --- !ruby/object:Gem::Specification
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  name: origen_arm_debug
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  version: !ruby/object:Gem::Version
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- version: 0.4.2
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+ version: 0.4.3
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  platform: ruby
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  authors:
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  - Ronnie Lajaunie
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2015-08-27 00:00:00.000000000 Z
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+ date: 2015-08-28 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: origen