origen_arm_debug 0.4.0

data/lib/origen_arm_debug/abs_if_swd.rb

@@ -0,0 +1,269 @@
+# To use this driver the $soc model must define the following pins (an alias is fine):
+#   :swd_clk
+#   :swd_dio
+#
+# API methods:
+#   R_dp -  debug register read - just a dummy function in origen
+#   RE_dp - debug register read/expect - expect compares not implemented
+#   R_ap - read a specific address - just a dummy function in origen
+#   W_dp - debug register write
+#   W_ap - write a specific address
+#   WR_ap - write a specific address, then read back
+
+module OrigenARMDebug
+  class ABSIF_SWD
+    attr_reader :owner
+    include Origen::Registers
+
+    def initialize(owner, options = {})
+      @current_apaddr = 0
+      @orundetect = 0
+      @owner = owner
+    end
+
+    # Highest level implementation of API - abstracted from 'read' and 'write' for future merging with JTAG debug
+    def R_dp(name, rdata, options = {})
+      cc 'Reading ' + name
+      read_dp(name, options)
+    end
+
+    def RE_dp(name, edata, options = {})
+      R_dp(name, edata, options)
+    end
+
+    def R_ap(addr, rdata, options = {})
+      cc 'Reading address ' + addr.to_s(16)
+      read_ap(addr, options)
+    end
+
+    def WAIT_RE_ap(addr, edata, options = {})
+      options = { mask: 0xffffffff, r_attempts: 1 }.merge(options)
+
+      # just assume that it always passes
+      actual = edata
+
+      R_ap(addr, actual, options)
+
+      cc "ABS-IF: WAIT_RE-AP: addr = 0x#{addr.to_s(16)}, "\
+                             "actual = 0x#{actual.to_s(16)}, "\
+                             "expected = 0x#{edata.to_s(16)}, "\
+                             "mask = 0x#{options[:mask].to_s(16)}"
+    end
+
+    def W_dp(name, wdata, options = {})
+      cc 'Writing 0x' + wdata.to_s(16) + ' to ' + name
+      write_dp(name, wdata, options)
+    end
+
+    def WR_dp(name, wdata, options = {})
+      options = { edata: 0x00000000, mask: 0xffffffff,
+                  w_attempts: 1, r_attempts: 1
+                }.merge(options)
+
+      # just assume that it always passes
+      actual = options[:edata] & options[:mask]
+
+      W_dp(name, wdata, options)
+      R_dp(name, actual, options)
+
+      cc "ABS-IF: WR-DP: #{name} write = 0x#{wdata.to_s(16)}, "\
+                                "read = 0x#{actual.to_s(16)}, "\
+                                "expected = 0x#{options[:edata].to_s(16)}, "\
+                                "mask = 0x#{options[:mask].to_s(16)}"
+    end
+
+    def W_ap(addr, wdata, options = {})
+      options = { w_attempts: 1 }.merge(options)
+      cc 'Writing 0x' + wdata.to_s(16) + ' to address 0x' + addr.to_s(16)
+      write_ap(addr, wdata, options)
+    end
+
+    def WR_ap(addr, wdata, options = {})
+      options = { edata: 0x00000000, mask: 0xffffffff,
+                  w_attempts: 1, r_attempts: 1
+                }.merge(options)
+
+      # just assume that it always passes
+      actual = wdata & options[:mask]
+      W_ap(addr, wdata, options)
+      options.delete(:w_delay) if options.key?(:w_delay)
+      R_ap(addr, actual, options)
+
+      cc "ABS-IF: WR-AP: addr = 0x#{addr.to_s(16)}, "\
+                       "write = 0x#{wdata.to_s(16)}, "\
+                        "read = 0x#{actual.to_s(16)}, "\
+                    "expected = 0x#{options[:edata].to_s(16)}, "\
+                        "mask = 0x#{options[:mask].to_s(16)}"
+    end
+
+    # SWD-specific functions
+    def read_dp(name, options = {})
+      case name
+         when 'IDCODE'    then dpacc_access(name, 1, 0x55555555, options)
+         when 'ABORT'     then cc 'Write only register!'
+         when 'CTRL/STAT' then dpacc_access(name, 1, 0x55555555, options)
+         when 'SELECT'    then cc 'Write only register!'
+         when 'RDBUFF'    then dpacc_access(name, 1, 0x55555555, options)
+         when 'WCR'       then dpacc_access(name, 1, 0x55555555, options)
+         when 'RESEND'    then dpacc_access(name, 1, 0x55555555, options)
+         else cc 'Unknown SW-DP register name'
+      end
+    end
+
+    def write_dp(name, wdata, options = {})
+      case name
+         when 'IDCODE'    then cc 'SW-DP register is read-only'
+         when 'ABORT'     then dpacc_access(name, 0, wdata, options)
+         when 'CTRL/STAT' then dpacc_access(name, 0, wdata, options)
+         when 'SELECT'    then dpacc_access(name, 0, wdata, options)
+         when 'RDBUFF'    then cc 'SW-DP register is read-only'
+         when 'WCR'       then dpacc_access(name, 0, wdata, options)
+         when 'RESEND'    then cc 'SW-DP register is read-only'
+         else cc 'Unknown SW-DP register name'
+      end
+    end
+
+    def write_ap(addr, wdata, options = {})
+      apacc_access(addr, 0, wdata, options)
+    end
+
+    def read_ap(addr, options = {})
+      # Create another copy of options with select keys removed. This first read is junk so we do not want to
+      # store it or compare it.
+      junk_options = options.clone.delete_if do |key, val|
+        (key.eql?(:r_mask) && val.eql?('store')) || key.eql?(:compare_data)
+      end
+      # pass junk options onto the first apacc access
+      apacc_access(addr, 1, 0x55555555, junk_options)
+      read_dp('RDBUFF', options) # This is the real data
+    end
+
+    # Low-level access functions
+    def dpacc_access(name, rwb, wdata, options = {})
+      addr = get_dp_addr(name)
+      if (name == 'CTRL/STAT')
+        cc 'CTRL/STAT'
+        set_apselect(@current_apaddr & 0xFFFFFFFE, options)
+      end
+      if (name == 'WCR')
+        cc 'NOT IMPLEMENTED'
+      end
+
+      acc_access(addr, rwb, 0, wdata, options)
+
+      if (name == 'WCR')
+        cc 'NOT IMPLEMENTED'
+      end
+      if (name == 'CTRL/STAT')
+        @orundetect = wdata & 0x1
+      end
+    end
+
+    def apacc_access(addr, rwb, wdata, options = {})
+      set_apselect((addr & 0xFFFFFFFE) | (@current_apaddr & 1), options)
+      options.delete(:w_delay) if options.key?(:w_delay)
+      acc_access((addr & 0xC), rwb, 1, wdata, options)
+    end
+
+    def get_dp_addr(name)
+      case name
+         when 'IDCODE'    then return 0x0
+         when 'ABORT'     then return 0x0
+         when 'CTRL/STAT' then return 0x4
+         when 'WCR'       then return 0x4
+         when 'RESEND'    then return 0x8
+         when 'SELECT'    then return 0x8
+         when 'RDBUFF'    then return 0xC
+         else cc 'Unknown SW-DP register name'
+      end
+    end
+
+    def acc_access(address, rwb, ap_dp, wdata, options = {})
+      start      = 1
+      apndp      = ap_dp
+      rnw        = rwb
+      addr       = address >> 2
+      parity_pr  = ap_dp ^ rwb ^ (addr >> 3) ^ (addr >> 2) & (0x01) ^ (addr >> 1) & (0x01) ^ addr & 0x01
+      trn        = 0
+      data       = wdata
+      require_dp = @orundetect
+      line_reset = 0
+      stop       = 0
+      park       = 1
+
+      cc 'SWD transaction'
+      cc 'Packet Request Phase'
+
+      annotate 'Send Start Bit'
+      owner.owner.swd.send_data(start, 1)
+      cc('Send APnDP Bit (DP or AP Access Register Bit)', prefix: true)
+      owner.owner.swd.send_data(apndp,      1)
+      c2 'Send RnW Bit (read or write bit)'
+      owner.owner.swd.send_data(rnw,        1)
+      c2 'Send Address Bits (2 bits)'
+      owner.owner.swd.send_data(addr,       2)
+      c2 'Send Parity Bit'
+      owner.owner.swd.send_data(parity_pr,  1)
+      c2 'Send Stop Bit'
+      owner.owner.swd.send_data(stop,       1)
+      c2 'Send Park Bit'
+      owner.owner.swd.send_data(park,       1)
+
+      cc 'Acknowledge Response phase'
+      owner.owner.swd.send_data(0xf, trn + 1)
+      owner.owner.swd.get_data (3)
+      cc 'Read/Write Data Phase'
+      if (rwb == 1)
+        cc 'Read'
+        if options[:r_mask] == 'store'
+          owner.owner.pin(:swd_dio).store
+        end
+        cc 'SWD 32-Bit Read Data Start'
+        owner.owner.swd.get_data(32, options)
+        cc 'SWD 32-Bit Read Data End'
+        cc 'Get Read Parity Bit'
+        owner.owner.swd.get_data(1)
+        cc 'Send Read ACK bits'
+        owner.owner.swd.send_data(0xf, trn + 1)
+      else
+        cc 'Write'
+        cc 'Send ACK Bits'
+        owner.owner.swd.send_data(0xf, trn + 1)
+        cc 'SWD 32-Bit Write Start'
+        owner.owner.swd.send_data(data, 32, options)
+        cc 'SWD 32-Bit Write End'
+        cc 'Send Write Parity Bit'
+        owner.owner.swd.send_data(swd_xor_calc(32, data), 1)
+      end
+
+      if options.key?(:w_delay)
+        cc "SWD DIO to 0 for #{options[:w_delay]} cycles"
+        owner.owner.swd.swd_dio_to_0(options[:w_delay])
+      else
+        cc 'SWD DIO to 0 for 10 cycles'
+        owner.owner.swd.swd_dio_to_0(10)
+      end
+    end
+
+    def set_apselect(addr, options = {})
+      addr &= 0xff0000f1
+      cc "SET_APSelect: addr = 0x#{addr.to_s(16)} "
+
+      if (addr != @current_apaddr)
+        cc 'SET_APSelect: write_dp SELECT'
+        write_dp('SELECT', addr & 0xff0000ff, options)
+      end
+
+      @current_apaddr = addr
+    end
+
+    # Calculate exclusive OR
+    def swd_xor_calc(size, number)
+      xor = 0
+      size.times do |bit|
+        xor ^= (number >> bit) & 0x01
+      end
+      xor
+    end
+ end
+end

data/lib/origen_arm_debug/driver.rb

@@ -0,0 +1,67 @@
+module OrigenARMDebug
+  class Driver
+    # Returns the parent object that instantiated the driver, could be
+    # either a DUT object or a protocol abstraction
+    attr_reader :owner
+
+    # Initialize class variables
+    #
+    # @param [Object] owner Parent object
+    # @param [Hash] options Options to customize the operation
+    #
+    # @example
+    #   DUT.new.arm_debug
+    #
+    def initialize(owner, options = {})
+      @owner = owner
+    end
+
+    def swj_dp
+      if owner.respond_to?(:swd)
+        @swj_dp ||= SWJ_DP.new(self, :swd)
+      elsif owner.respond_to?(:jtag)
+        @swj_dp ||= SWJ_DP.new(self, :jtag)
+      end
+    end
+
+    # Returns an instance of the OrigenARMDebug::MemAP
+    def mem_ap
+      @mem_ap ||= MemAP.new(self)
+    end
+
+    # Method to add additional Memory Access Ports (MEM-AP) with specified base address
+    # name - short name for mem_ap that is being created
+    # base_address - base address
+    def add_mem_ap(name, base_address)
+      instance_variable_set("@#{name}", MemAP.new(self, name: name, base_address: base_address))
+      self.class.send(:attr_accessor, name)
+    end
+
+    def read_register(reg_or_val, options = {})
+      mem_ap.read(reg_or_val.address, size: reg_or_val.size, compare_data: reg_or_val.data)
+    end
+
+    def write_register(reg_or_val, options = {})
+      mem_ap.write(reg_or_val.address, reg_or_val.data, size: reg_or_val.size)
+    end
+
+    private
+
+    def arm_debug_driver
+      return @arm_debug_driver if @arm_debug_driver
+      if owner.respond_to?(:jtag)
+        @arm_debug_driver = owner.jtag
+      elsif owner.respond_to?(:swd)
+        @arm_debug_driver = owner.swd
+      else
+        puts 'Cannot find a compatible physical driver!'
+        puts 'The ARM debug protocol supports the following phyiscal drivers:'
+        puts '  JTAG - http://origen-sdk.org/origen_jtag'
+        puts '  Single Wire Debug - http://origen-sdk.org/origen_swd'
+        puts '  Background Debug - http://origen-sdk.org/origen_bdm'
+        puts "Add one to your #{owner.class} to resolve this error."
+        fail 'ARM Debug error!'
+      end
+    end
+  end
+end

data/lib/origen_arm_debug/dut.rb

@@ -0,0 +1,51 @@
+module OrigenARMDebug
+  # This is a dummy DUT model which is used
+  # to instantiate and test the ARMDebug locally
+  # during development.
+  #
+  # It is not included when this library is imported.
+  class DUT
+    include OrigenARMDebug
+    include Origen::Callbacks
+    include Origen::Registers
+
+    # Initializes simple dut model with test register and required jtag/swd pins
+    #
+    # @example
+    #   $dut = OrigenARMDebug::DUT.new
+    #
+    def initialize
+      add_reg :dap,  0x0, 35, data: { pos: 0, bits: 35 }
+
+      add_reg :test, 0x0, 32, data: { pos: 0, bits: 32 },
+                              bit:  { pos: 0 }
+
+      arm_debug.add_mem_ap('mem_ap', 0x00000000)
+      arm_debug.add_mem_ap('mdm_ap', 0x01000000)
+      arm_debug.add_mem_ap('alt_ahbapi', 0x02000000)
+    end
+
+    # Add any custom startup business here.
+    #
+    # @param [Hash] options Options to customize the operation
+    def startup(options)
+      $tester.set_timeset('arm_debug', 40)
+    end
+
+    # Read data from a register
+    #
+    # @param [Register] reg Register name or address value
+    # @param [Hash] options Options to customize the operation
+    def read_register(reg, options = {})
+      arm_debug.read_register(reg, options)
+    end
+
+    # Write data to a register
+    #
+    # @param [Register] reg Register name or address value
+    # @param [Hash] options Options to customize the operation
+    def write_register(reg, options = {})
+      arm_debug.write_register(reg, options)
+    end
+  end
+end

data/lib/origen_arm_debug/dut_jtag.rb

@@ -0,0 +1,17 @@
+module OrigenARMDebug
+  class JTAG_DUT < DUT
+    include OrigenJTAG
+    include Origen::Pins
+
+    # Adds jtag-required pins to the simple dut model
+    # Returns nothing.
+    def initialize
+      super
+      add_pin :tclk
+      add_pin :tdi
+      add_pin :tdo
+      add_pin :tms
+      add_pin :trst
+    end
+  end
+end

data/lib/origen_arm_debug/dut_swd.rb

@@ -0,0 +1,14 @@
+module OrigenARMDebug
+  class SWD_DUT < DUT
+    include OrigenSWD
+    include Origen::Pins
+
+    # Adds swd-required pins to the simple dut model
+    # Returns nothing.
+    def initialize
+      super
+      add_pin :swd_clk
+      add_pin :swd_dio
+    end
+  end
+end

data/lib/origen_arm_debug/mem_ap.rb

@@ -0,0 +1,387 @@
+module OrigenARMDebug
+  class MemAP
+    # ARM Debug Interface v5.1
+    MEM_ADDR_CSW  = 0x00000000
+    MEM_ADDR_TAR  = 0x00000004
+    MEM_ADDR_DRW  = 0x0000000C
+    MEM_ADDR_BD0  = 0x00000010
+    MEM_ADDR_BD1  = 0x00000014
+    MEM_ADDR_BD2  = 0x00000018
+    MEM_ADDR_BD3  = 0x0000001C
+    MEM_ADDR_CFG  = 0x000000F4
+    MEM_ADDR_BASE = 0x000000F8
+    MEM_ADDR_IDR  = 0x000000FC
+
+    # Returns the parent object that instantiated the driver
+    attr_reader :owner
+
+    # Initialize class variables
+    #
+    # @param [Object] owner Parent object
+    # @param [Hash] options Options to customize the operation
+    #
+    # @example
+    #   DUT.new.arm_debug.mem_ap
+    #
+    def initialize(owner, options = {})
+      @owner = owner
+      @name = options[:name].nil? ? 'default' : options[:name]
+      @base_address = options[:base_address].nil? ? 0x00000000 : options[:base_address]
+
+      # reset values for MEM-AP registers
+      @current_csw = 0x00000000
+      @current_tar = 0xffffffff
+      @current_dsw = 0x00000000
+    end
+
+    # Shortcut name to SWJ-DP Debug Port
+    def debug_port
+      owner.swj_dp
+    end
+    alias_method :dp, :debug_port
+
+    # -----------------------------------------------------------------------------
+    # User API
+    # -----------------------------------------------------------------------------
+
+    # Method to read from a mem_ap register
+    #
+    # @param [Integer] addr Address of register to be read from
+    # @param [Hash] options Options to customize the operation
+    #
+    # @example
+    #   # don't care what data actually is
+    #   mem_ap.read(0x2000000, size: 32)
+    #
+    #   # expect read data to be = 0x5a5a5a5a
+    #   mem_ap.read(0x2000000, size: 32, edata: 0x5a5a5a5a)
+    #
+    #   # expect read data to be = 0xXXXXXX5a (mask out all bits except [7:0])
+    #   mem_ap.read(0x2000000, size: 32, edata: 0x5a5a5a5a, r_mask: 0x000000ff)
+    #
+    # Returns nothing.
+    def read(addr, options = {})
+      options = { size: 32 }.merge(options)
+      options = { r_mask: 'mask', r_attempts: 1 }.merge(options)
+      msg = 'Arm Debug: Shift out data for reading'
+      options = { arm_debug_comment: msg }.merge(options)
+      size = options[:size]
+
+      set_size(size)
+      set_addr(addr)
+      debug_port.read_ap(drw_reg_addr, options)
+      rdata = get_rdata(size, addr, rdata)
+      increment_addr
+
+      cc "MEM-AP(#{@name}): R-#{size.to_s(10)}: "\
+        "addr=0x#{addr.to_s(16).rjust(size / 4, '0')}"
+    end
+
+    # Method to write to a mem_ap register
+    #
+    # @param [Integer] addr Address of register to be read from
+    # @param [Integer] wdata Data to be written
+    # @param [Hash] options Options to customize the operation
+    #
+    # @example
+    #   mem_ap.write(0x2000000, 0xc3c3a5a5, size: 32)
+    #
+    # Returns nothing.
+    def write(addr, wdata, options = {});
+      options = { size: 32 }.merge(options)
+      options = { w_attempts: 1 }.merge(options)
+      msg = "Arm Debug: Shift in data to write: #{wdata.to_hex}"
+      options = { arm_debug_comment: msg }.merge(options)
+      size = options[:size]
+
+      set_size(size)
+      set_addr(addr)
+      wdata = get_wdata(size, addr, wdata)
+      debug_port.write_ap(drw_reg_addr, wdata, options)
+      increment_addr
+
+      cc "MEM-AP(#{@name}): WR-#{size.to_s(10)}: "\
+        "addr=0x#{addr.to_s(16).rjust(size / 4, '0')}, "\
+        "data=0x#{wdata.to_s(16).rjust(size / 4, '0')}"
+    end
+
+    # Method to write and then read from a mem_ap register (legacy)
+    #
+    # @param [Integer] addr Address of register to be read from
+    # @param [Integer] wdata Data to be written
+    # @param [Hash] options Options to customize the operation
+    #
+    # @example
+    #   # don't care what read-back data actually is
+    #   mem_ap.write_read(0x2000000, 0xc3c3a5a5, size: 32)
+    #
+    #   # expect read-back data to be same as write data = 0xc3c3a5a5
+    #   mem_ap.read(0x2000000, 0xc3c3a5a5, size: 32, edata: 0xc3c3a5a5)
+    #
+    #   # expect read-back data to be = 0xXXXXXXa5 (mask out all bits except [7:0])
+    #   mem_ap.read(0x2000000, 0xc3c3a5a5, size: 32, edata: 0xc3c3a5a5, r_mask: 0x000000ff)
+    #
+    # Returns nothing.
+    def write_read(addr, wdata, options = {})
+      options = { size: 32 }.merge(options)
+      options = { edata: 0x00000000, r_mask: 0xffffffff, actual: 0x00000000 }.merge(options)
+      options = { w_attempts: 1, r_attempts: 2 }.merge(options)
+      size = options[:size]
+
+      write(addr, wdata, options)
+      options[:edata] = wdata & options[:r_mask] if options[:edata] == 0x00000000
+      read(addr, options)
+      actual = wdata & options[:r_mask]
+
+      cc "MEM-AP(#{@name}): WR-#{size.to_s(10)}: "\
+        "addr=0x#{addr.to_s(16).rjust(size / 4, '0')}, "\
+        "wdata=0x#{wdata.to_s(16).rjust(size / 4, '0')}, "\
+        "read=0x#{actual.to_s(16).rjust(size / 4, '0')}, "\
+        "expect=0x#{options[:edata].to_s(16).rjust(size / 4, '0')}, "\
+        "mask=0x#{options[:r_mask].to_s(16).rjust(size / 4, '0')}"
+    end
+
+    # -----------------------------------------------------------------------------
+    # Legacy Support (to be phased out)
+    # -----------------------------------------------------------------------------
+
+    # Method to read from a mem_ap register (legacy)
+    #
+    # @param [Integer] addr Address of register to be read from
+    # @param [Integer] rdata This really does nothing since only care about value
+    #   of options[:edata]
+    # @param [Hash] options Options to customize the operation
+    # Returns nothing.
+    def R(addr, rdata, options = {})
+      # Warn caller that this method is being deprecated
+      msg = 'Use mem_ap.read(addr, options) instead of R(addr, rdata, options)'
+      Origen.deprecate msg
+
+      # Patch arguments and send to new method
+      options = { rdata: rdata }.merge(options)
+      read(addr, options)
+    end
+
+    # Method to write to a mem_ap register (legacy)
+    #
+    # @param [Integer] addr Address of register to be written to
+    # @param [Integer] wdata Data to be written
+    # @param [Hash] options Options to customize the operation
+    # Returns nothing.
+    def W(addr, wdata, options = {})
+      # Warn caller that this method is being deprecated
+      msg = 'Use mem_ap.write(addr, wdata, options) instead of W(addr, wdata, options)'
+      Origen.deprecate msg
+
+      # Patch arguments and send to new method
+      write(addr, wdata, options)
+    end
+
+    # Method to write and then read from a mem_ap register (legacy)
+    #
+    # @param [Integer] addr Address of register to be read from
+    # @param [Integer] wdata Data to be written
+    # @param [Hash] options Options to customize the operation
+    # Returns nothing.
+    def WR(addr, wdata, options = {})
+      # Warn caller that this method is being deprecated
+      msg = 'Use mem_ap.write_read(addr, wdata, options) instead of WR(addr, wdata, options)'
+      Origen.deprecate msg
+
+      # Patch arguments and send to new method
+      write_read(addr, wdata, options)
+    end
+
+    # -----------------------------------------------------------------------------
+    # Support Code
+    # -----------------------------------------------------------------------------
+
+    private
+
+    # Sets the size of the data (by writing to the CSW size bits).  It will only
+    #   write to the size if the size from the previous transaction has changed
+    #
+    # @param [Integer] size Size of data, supports 8-bit, 16-bit, and 32-bit
+    def set_size(size)
+      case size
+        when 8 then  new_size = 0x00000000
+        when 16 then new_size = 0x00000001
+        when 32 then new_size = 0x00000002
+        else new_size = 0x00000002
+      end
+
+      if (@current_csw == 0x00000000)
+        debug_port.read_ap(csw_reg_addr)
+        @current_csw = 0x23000040
+      end
+
+      csw_size = @current_csw & 0x00000003
+      if (csw_size != new_size)
+        new_csw = (@current_csw & 0xfffffffc) | new_size
+        debug_port.write_ap(csw_reg_addr, new_csw)
+        @current_csw = new_csw
+      end
+    end
+
+    # Sets the addr of the transaction.
+    #
+    # @param [Integer] addr Address of data to be read from or written to
+    def set_addr(addr)
+      arm_debug_comment = "Arm Debug: Shift in read/write address: #{addr.to_hex}"
+      options = { arm_debug_comment: arm_debug_comment }
+
+      if (@current_tar != addr)
+        debug_port.write_ap(tar_reg_addr, addr, options)
+      end
+      @current_tar = addr;
+    end
+
+    # Increment the address for the next transaction.
+    def increment_addr
+      current_csw_5_4 = (@current_csw & 0x00000030) >> 4
+      current_csw_2_0 = @current_csw & 0x00000007
+      if (current_csw_5_4 == 0b01)
+        case current_csw_2_0
+          when 0b000 then @current_tar += 1   # Increment single
+          when 0b001 then @current_tar += 2   # Increment single
+          when 0b010 then @current_tar += 4   # Increment single
+        end
+      elsif (current_csw_5_4 == 0b10)
+        @current_tar += 4                     # Increment packed
+      end
+
+      if current_csw_5_4 && ((@current_tar & 0xfffffc00) == 0xffffffff)
+        # reset tar when attempting to increment past 1kB boundary
+        @current_tar = 0xffffffff
+      end
+    end
+
+    # Create a bit-wise mask based on size, address and mask parameters.
+    #
+    # @param [Integer] size Size of data, supports 8-bit, 16-bit, and 32-bit
+    # @param [Integer] addr Address of data to be read from or written to
+    # @param [Integer] mask Mask for full data, used to create nibble mask
+    def get_mask(size, addr, mask)
+      addr_1_0 &= 0x00000003
+      case size
+        when 8
+          case addr_1_0
+            when 0b00 then mask &= 0x000000ff
+            when 0b01 then mask &= 0x0000ff00
+            when 0b10 then mask &= 0x00ff0000
+            when 0b11 then mask &= 0xff000000
+          end
+        when 16
+          case addr_1_0
+            when 0b00 then mask &= 0x0000ffff
+            when 0b10 then mask &= 0xffff0000
+          end
+        when 32
+          mask &= 0xffffffff
+      end
+      mask
+    end
+
+    # Create a bit-wise read-data based on size, address and rdata parameters.
+    #
+    # @param [Integer] size Size of data, supports 8-bit, 16-bit, and 32-bit
+    # @param [Integer] addr Address of data to be read from or written to
+    # @param [Integer] rdata Full data for read, used to create nibble read data
+    def get_rdata(size, addr, rdata)
+      addr_1_0 &= 0x00000003
+      case size
+        when 8
+          case addr_1_0
+            when 0b00 then rdata = 0x000000ff & rdata
+            when 0b01 then rdata = 0x000000ff & (rdata >> 8)
+            when 0b10 then rdata = 0x000000ff & (rdata >> 16)
+            when 0b11 then rdata = 0x000000ff & (rdata >> 24)
+          end
+        when 16
+          case addr_1_0
+                  when 0b00 then rdata = 0x0000ffff & rdata
+                  when 0b10 then rdata = 0x0000ffff & (rdata >> 16)
+                end
+        when 32
+          rdata = rdata
+      end
+      rdata
+    end
+
+    # Create a bit-wise read-data based on size, address and wdata parameters.
+    #
+    # @param [Integer] size Size of data, supports 8-bit, 16-bit, and 32-bit
+    # @param [Integer] addr Address of data to be read from or written to
+    # @param [Integer] wdata Full data for write, used to create nibble write data
+    def get_wdata(size, addr, wdata);
+      addr_1_0 &= 0x00000003
+      case size
+        when 8
+          case addr_1_0
+                  when 0b00 then wdata = 0x000000ff & wdata
+                  when 0b01 then wdata = 0x0000ff00 & (wdata << 8)
+                  when 0b10 then wdata = 0x00ff0000 & (wdata << 16)
+                  when 0b11 then wdata = 0xff000000 & (wdata << 24)
+                end
+        when 16
+          case addr_1_0
+                  when 0b00 then wdata = 0x0000ffff & wdata
+                  when 0b10 then wdata = 0xffff0000 & (wdata << 16)
+          end
+        when 32
+          wdata = wdata
+      end
+      wdata
+    end
+
+    # Returns address of CSW register for this mem-ap instance
+    def csw_reg_addr
+      MEM_ADDR_CSW + @base_address
+    end
+
+    # Returns address of TAR register for this mem-ap instance
+    def tar_reg_addr
+      MEM_ADDR_TAR + @base_address
+    end
+
+    # Returns address of DRW register for this mem-ap instance
+    def drw_reg_addr
+      MEM_ADDR_DRW + @base_address
+    end
+
+    # Returns address of BD0 register for this mem-ap instance
+    def bdo_reg_addr
+      MEM_ADDR_BD0 + @base_address
+    end
+
+    # Returns address of BD1 register for this mem-ap instance
+    def bd1_reg_addr
+      MEM_ADDR_BD1 + @base_address
+    end
+
+    # Returns address of BD2 register for this mem-ap instance
+    def bd2_reg_addr
+      MEM_ADDR_BD2 + @base_address
+    end
+
+    # Returns address of BD3 register for this mem-ap instance
+    def bd3_reg_addr
+      MEM_ADDR_BD3 + @base_address
+    end
+
+    # Returns address of CFG register for this mem-ap instance
+    def cfg_reg_addr
+      MEM_ADDR_CFG + @base_address
+    end
+
+    # Returns address of BASE register for this mem-ap instance
+    def base_reg_addr
+      MEM_ADDR_BASE + @base_address
+    end
+
+    # Returns address of IDR register for this mem-ap instance
+    def idr_reg_addr
+      MEM_ADDR_IDR + @base_address
+    end
+  end
+end