origen 0.7.47 → 0.8.0
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- checksums.yaml +4 -4
- data/config/version.rb +2 -2
- data/lib/c99/nvm.rb +12 -0
- data/lib/origen/application.rb +8 -1
- data/lib/origen/generator/job.rb +2 -1
- data/lib/origen/model.rb +1 -0
- data/lib/origen/registers.rb +14 -0
- data/lib/origen/registers/bit_collection.rb +78 -18
- data/lib/origen/registers/reg.rb +103 -33
- data/lib/origen/remote_manager.rb +7 -3
- metadata +17 -3
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
|
1
1
|
---
|
2
2
|
SHA1:
|
3
|
-
metadata.gz:
|
4
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-
data.tar.gz:
|
3
|
+
metadata.gz: 7ed980dcd18e1d53defcd27928d2fae2b5c6fe53
|
4
|
+
data.tar.gz: c9d7b163c3c5d219ea8b81f0b624938cf5049877
|
5
5
|
SHA512:
|
6
|
-
metadata.gz:
|
7
|
-
data.tar.gz:
|
6
|
+
metadata.gz: 540490e6a49ea8c7acef2f18d56eec937a14fe826b91f48fc0344a52ee9027d6310ed9546a77f1d2a95a484123feac4ca366228b8b8c01bfa79ed1f575f7ac5a
|
7
|
+
data.tar.gz: 83801037183ae53aa780c1c06c4a15bc9976361e2a552011195176eb8004353a69a1b58b525de23ec4373906dc6ad7b8c4b395aec07a65c300e469fc7728ae22
|
data/config/version.rb
CHANGED
data/lib/c99/nvm.rb
CHANGED
@@ -44,6 +44,18 @@ module C99
|
|
44
44
|
def add_non_byte_aligned_regs
|
45
45
|
add_reg :non_aligned_small, 0x1000, size: 4
|
46
46
|
add_reg :non_aligned_big, 0x1010, size: 10
|
47
|
+
add_reg :non_aligned_small_msb0, 0x2000, size: 4, bit_order: :msb0
|
48
|
+
add_reg :non_aligned_big_msb0, 0x2010, size: 10, bit_order: :msb0
|
49
|
+
end
|
50
|
+
|
51
|
+
def add_msb0_regs
|
52
|
+
reg :SIUL2_MIDR1, 0x4, bit_order: :msb0 do |reg|
|
53
|
+
bit 0..15, :PARTNUM, res: 0b0101011101110111
|
54
|
+
bit 16, :ED
|
55
|
+
bit 17..21, :PKG
|
56
|
+
bit 24..27, :MAJOR_MASK
|
57
|
+
bit 28..31, :MINOR_MASK
|
58
|
+
end
|
47
59
|
end
|
48
60
|
end
|
49
61
|
|
data/lib/origen/application.rb
CHANGED
@@ -23,7 +23,6 @@ module Origen
|
|
23
23
|
require 'origen/users'
|
24
24
|
include Origen::Users
|
25
25
|
|
26
|
-
attr_accessor :current_job
|
27
26
|
attr_accessor :name
|
28
27
|
attr_accessor :namespace
|
29
28
|
|
@@ -99,6 +98,14 @@ module Origen
|
|
99
98
|
end
|
100
99
|
end
|
101
100
|
|
101
|
+
def current_job
|
102
|
+
current_jobs.last
|
103
|
+
end
|
104
|
+
|
105
|
+
def current_jobs
|
106
|
+
@current_jobs ||= []
|
107
|
+
end
|
108
|
+
|
102
109
|
# Load all rake tasks defined in the application's lib/task directory
|
103
110
|
def load_tasks
|
104
111
|
RakeLoader.new.load_tasks
|
data/lib/origen/generator/job.rb
CHANGED
@@ -109,7 +109,7 @@ module Origen
|
|
109
109
|
end
|
110
110
|
|
111
111
|
def run
|
112
|
-
Origen.app.
|
112
|
+
Origen.app.current_jobs << self
|
113
113
|
begin
|
114
114
|
if @options[:compile]
|
115
115
|
Origen.generator.compiler.compile(@requested_pattern, @options)
|
@@ -151,6 +151,7 @@ module Origen
|
|
151
151
|
raise
|
152
152
|
end
|
153
153
|
end
|
154
|
+
Origen.app.current_jobs.pop
|
154
155
|
end
|
155
156
|
end
|
156
157
|
end
|
data/lib/origen/model.rb
CHANGED
@@ -50,6 +50,7 @@ module Origen
|
|
50
50
|
Origen.top_level == self
|
51
51
|
end
|
52
52
|
alias_method :is_dut?, :is_top_level?
|
53
|
+
alias_method :top_level?, :is_top_level?
|
53
54
|
|
54
55
|
# Means that when dealing with a controller/model pair, you can
|
55
56
|
# always call obj.model and obj.controller to get the one you want,
|
data/lib/origen/registers.rb
CHANGED
@@ -24,6 +24,20 @@ module Origen
|
|
24
24
|
|
25
25
|
attr_accessor :owner
|
26
26
|
attr_accessor :name
|
27
|
+
attr_writer :bit_order
|
28
|
+
end
|
29
|
+
|
30
|
+
# Returns the bit order attribute of the model (either :msb0 or :lsb0). If
|
31
|
+
# not explicitly defined on this model it will be inherited from the parent
|
32
|
+
# and will default to :lsb0 at the top-level
|
33
|
+
def bit_order
|
34
|
+
@bit_order ||= begin
|
35
|
+
if parent
|
36
|
+
parent.bit_order
|
37
|
+
else
|
38
|
+
:lsb0
|
39
|
+
end
|
40
|
+
end
|
27
41
|
end
|
28
42
|
|
29
43
|
def method_missing(method, *args, &block) # :nodoc:
|
@@ -17,6 +17,7 @@ module Origen
|
|
17
17
|
STORE_CHAR = 'S'
|
18
18
|
|
19
19
|
attr_accessor :name
|
20
|
+
alias_method :id, :name
|
20
21
|
|
21
22
|
def initialize(reg, name, data = []) # :nodoc:
|
22
23
|
if reg.respond_to?(:has_bits_enabled_by_feature?) && reg.has_parameter_bound_bits?
|
@@ -27,6 +28,11 @@ module Origen
|
|
27
28
|
[data].flatten.each { |item| self << item }
|
28
29
|
end
|
29
30
|
|
31
|
+
# Returns the bit order of the parent register
|
32
|
+
def bit_order
|
33
|
+
parent.bit_order
|
34
|
+
end
|
35
|
+
|
30
36
|
def terminal?
|
31
37
|
true
|
32
38
|
end
|
@@ -103,7 +109,7 @@ module Origen
|
|
103
109
|
v = tester.capture do
|
104
110
|
store!(sync: true)
|
105
111
|
end
|
106
|
-
|
112
|
+
reverse_shift_out_with_index do |bit, i|
|
107
113
|
bit.instance_variable_set('@updated_post_reset', true)
|
108
114
|
bit.instance_variable_set('@data', v.first[i])
|
109
115
|
end
|
@@ -264,7 +270,7 @@ module Origen
|
|
264
270
|
# reg(:control).data # => 0x55, assuming the reg has the required bits to store that
|
265
271
|
def data
|
266
272
|
data = 0
|
267
|
-
|
273
|
+
shift_out_with_index do |bit, i|
|
268
274
|
return undefined if bit.is_a?(Origen::UndefinedClass)
|
269
275
|
data |= bit.data << i
|
270
276
|
end
|
@@ -282,7 +288,7 @@ module Origen
|
|
282
288
|
# Returns the reverse of the data value held by the collection
|
283
289
|
def data_reverse
|
284
290
|
data = 0
|
285
|
-
|
291
|
+
reverse_shift_out_with_index do |bit, i|
|
286
292
|
return undefined if bit.is_a?(Origen::UndefinedClass)
|
287
293
|
data |= bit.data << i
|
288
294
|
end
|
@@ -295,6 +301,11 @@ module Origen
|
|
295
301
|
self
|
296
302
|
end
|
297
303
|
|
304
|
+
# Returns true if the collection contains all bits in the register
|
305
|
+
def whole_reg?
|
306
|
+
size == parent.size
|
307
|
+
end
|
308
|
+
|
298
309
|
# Set the data value of the collection within the patgen, but not on silicon - i.e. calling
|
299
310
|
# write will not trigger a pattern write event.
|
300
311
|
def write(value, options = {})
|
@@ -305,7 +316,10 @@ module Origen
|
|
305
316
|
value = value[0]
|
306
317
|
end
|
307
318
|
value = value.data if value.respond_to?('data')
|
308
|
-
|
319
|
+
|
320
|
+
size.times do |i|
|
321
|
+
self[i].write(value[i], options)
|
322
|
+
end
|
309
323
|
self
|
310
324
|
end
|
311
325
|
alias_method :data=, :write
|
@@ -325,8 +339,8 @@ module Origen
|
|
325
339
|
write(value, force: true)
|
326
340
|
end
|
327
341
|
if options[:mask]
|
328
|
-
|
329
|
-
|
342
|
+
shift_out_with_index { |bit, i| bit.read if options[:mask][i] == 1 }
|
343
|
+
shift_out_with_index { |bit, i| bit.clear_read_flag if options[:mask][i] == 0 }
|
330
344
|
else
|
331
345
|
each(&:read)
|
332
346
|
end
|
@@ -374,12 +388,58 @@ module Origen
|
|
374
388
|
# bist_shift(bit)
|
375
389
|
# end
|
376
390
|
def shift_out_left
|
377
|
-
|
391
|
+
if bit_order == :msb0
|
392
|
+
each { |bit| yield bit }
|
393
|
+
else
|
394
|
+
reverse_each { |bit| yield bit }
|
395
|
+
end
|
396
|
+
end
|
397
|
+
|
398
|
+
# Same as Reg#shift_out_left but includes the index counter
|
399
|
+
def shift_out_left_with_index
|
400
|
+
if bit_order == :msb0
|
401
|
+
each.with_index { |bit, i| yield bit, i }
|
402
|
+
else
|
403
|
+
reverse_each.with_index { |bit, i| yield bit, i }
|
404
|
+
end
|
378
405
|
end
|
379
406
|
|
380
407
|
# Same as Reg#shift_out_left but starts from the MSB
|
381
408
|
def shift_out_right
|
382
|
-
|
409
|
+
if bit_order == :msb0
|
410
|
+
reverse_each { |bit| yield bit }
|
411
|
+
else
|
412
|
+
each { |bit| yield bit }
|
413
|
+
end
|
414
|
+
end
|
415
|
+
|
416
|
+
# Same as Reg#shift_out_right but includes the index counter
|
417
|
+
def shift_out_right_with_index
|
418
|
+
if bit_order == :msb0
|
419
|
+
reverse_each.with_index { |bit, i| yield bit, i }
|
420
|
+
else
|
421
|
+
each_with_index { |bit, i| yield bit, i }
|
422
|
+
end
|
423
|
+
end
|
424
|
+
|
425
|
+
# Yields each bit in the register, LSB first.
|
426
|
+
def shift_out(&block)
|
427
|
+
each(&block)
|
428
|
+
end
|
429
|
+
|
430
|
+
# Yields each bit in the register and its index, LSB first.
|
431
|
+
def shift_out_with_index(&block)
|
432
|
+
each_with_index(&block)
|
433
|
+
end
|
434
|
+
|
435
|
+
# Yields each bit in the register, MSB first.
|
436
|
+
def reverse_shift_out(&block)
|
437
|
+
reverse_each(&block)
|
438
|
+
end
|
439
|
+
|
440
|
+
# Yields each bit in the register and its index, MSB first.
|
441
|
+
def reverse_shift_out_with_index(&block)
|
442
|
+
reverse_each.with_index(&block)
|
383
443
|
end
|
384
444
|
|
385
445
|
# Returns true if any bits have the read flag set - see Bit#is_to_be_read?
|
@@ -410,7 +470,7 @@ module Origen
|
|
410
470
|
# value in these bits
|
411
471
|
def setting(value)
|
412
472
|
result = 0
|
413
|
-
|
473
|
+
shift_out_with_index do |bit, i|
|
414
474
|
result |= bit.setting(value[i])
|
415
475
|
end
|
416
476
|
result
|
@@ -640,11 +700,11 @@ module Origen
|
|
640
700
|
def reset_data(value = nil)
|
641
701
|
# This method was originally setup to set the reset value by passing an argument
|
642
702
|
if value
|
643
|
-
|
703
|
+
shift_out_with_index { |bit, i| bit.reset_val = value[i] }
|
644
704
|
self
|
645
705
|
else
|
646
706
|
data = 0
|
647
|
-
|
707
|
+
shift_out_with_index do |bit, i|
|
648
708
|
return bit.reset_data if bit.reset_data.is_a?(Symbol)
|
649
709
|
data |= bit.reset_data << i
|
650
710
|
end
|
@@ -659,13 +719,13 @@ module Origen
|
|
659
719
|
|
660
720
|
# Modify writable for bits in collection
|
661
721
|
def writable(value)
|
662
|
-
|
722
|
+
shift_out_with_index { |bit, i| bit.writable = (value[i] == 0b1); bit.set_access_from_rw }
|
663
723
|
self
|
664
724
|
end
|
665
725
|
|
666
726
|
# Modify readable for bits in collection
|
667
727
|
def readable(value)
|
668
|
-
|
728
|
+
shift_out_with_index { |bit, i| bit.readable = (value[i] == 0b1); bit.set_access_from_rw }
|
669
729
|
self
|
670
730
|
end
|
671
731
|
|
@@ -718,20 +778,20 @@ module Origen
|
|
718
778
|
|
719
779
|
# Modify clr_only for bits in collection
|
720
780
|
def clr_only(value)
|
721
|
-
|
781
|
+
shift_out_with_index { |bit, i| bit.clr_only = (value[i] == 0b1) }
|
722
782
|
self
|
723
783
|
end
|
724
784
|
|
725
785
|
# Modify set_only for bits in collection
|
726
786
|
def set_only(value)
|
727
|
-
|
787
|
+
shift_out_with_index { |bit, i| bit.set_only = (value[i] == 0b1) }
|
728
788
|
self
|
729
789
|
end
|
730
790
|
|
731
791
|
# Return nvm_dep value held by collection
|
732
792
|
def nvm_dep
|
733
793
|
nvm_dep = 0
|
734
|
-
|
794
|
+
shift_out_with_index { |bit, i| nvm_dep |= bit.nvm_dep << i }
|
735
795
|
nvm_dep
|
736
796
|
end
|
737
797
|
|
@@ -821,7 +881,7 @@ module Origen
|
|
821
881
|
# myreg.data # => 0b0011
|
822
882
|
def shift_left(data = 0)
|
823
883
|
prev_bit = nil
|
824
|
-
|
884
|
+
reverse_shift_out do |bit|
|
825
885
|
prev_bit.write(bit.data) if prev_bit
|
826
886
|
prev_bit = bit
|
827
887
|
end
|
@@ -844,7 +904,7 @@ module Origen
|
|
844
904
|
# myreg.data # => 0b1100
|
845
905
|
def shift_right(data = 0)
|
846
906
|
prev_bit = nil
|
847
|
-
|
907
|
+
shift_out do |bit|
|
848
908
|
prev_bit.write(bit.data) if prev_bit
|
849
909
|
prev_bit = bit
|
850
910
|
end
|
data/lib/origen/registers/reg.rb
CHANGED
@@ -14,12 +14,13 @@ module Origen
|
|
14
14
|
# to all of its contained bits unless a specific bit has its own definition of the same
|
15
15
|
# attribute
|
16
16
|
REG_LEVEL_ATTRIBUTES = {
|
17
|
-
feature:
|
18
|
-
reset:
|
19
|
-
memory:
|
20
|
-
path:
|
21
|
-
abs_path:
|
22
|
-
access:
|
17
|
+
feature: {},
|
18
|
+
reset: { aliases: [:res] },
|
19
|
+
memory: {},
|
20
|
+
path: { aliases: [:hdl_path] },
|
21
|
+
abs_path: { aliases: [:absolute_path] },
|
22
|
+
access: {},
|
23
|
+
bit_order: {}
|
23
24
|
}
|
24
25
|
|
25
26
|
# Returns the object that own the register.
|
@@ -86,6 +87,13 @@ module Origen
|
|
86
87
|
add_bits_from_options(options)
|
87
88
|
end
|
88
89
|
|
90
|
+
# Returns the bit order attribute of the register (either :msb0 or :lsb0). If
|
91
|
+
# not explicitly defined on this register it will be inherited from the parent
|
92
|
+
# and will default to :lsb0 at the top-level
|
93
|
+
def bit_order
|
94
|
+
@bit_order ||= parent.bit_order
|
95
|
+
end
|
96
|
+
|
89
97
|
def freeze
|
90
98
|
bits.each(&:freeze)
|
91
99
|
# Call any methods which cache results to generate the instance variables
|
@@ -122,10 +130,14 @@ module Origen
|
|
122
130
|
bit_width = 13
|
123
131
|
desc = ["\n0x%X - :#{name}" % address]
|
124
132
|
r = size % 8
|
125
|
-
if r == 0
|
133
|
+
if r == 0 || (size > 8 && bit_order == :msb0)
|
126
134
|
desc << (' ' + ('=' * (bit_width + 1) * 8)).chop
|
127
135
|
else
|
128
|
-
|
136
|
+
if bit_order == :lsb0
|
137
|
+
desc << (' ' + (' ' * (bit_width + 1) * (8 - r)) + ('=' * (bit_width + 1) * r)).chop
|
138
|
+
else
|
139
|
+
desc << (' ' + ('=' * (bit_width + 1) * r)).chop
|
140
|
+
end
|
129
141
|
end
|
130
142
|
|
131
143
|
# "<#{self.class}: #{self.name}>"
|
@@ -133,30 +145,48 @@ module Origen
|
|
133
145
|
num_bytes.times do |byte_index|
|
134
146
|
# Need to add support for little endian regs here?
|
135
147
|
byte_number = num_bytes - byte_index
|
136
|
-
|
137
|
-
|
148
|
+
if bit_order == :lsb0
|
149
|
+
max_bit = (byte_number * 8) - 1
|
150
|
+
min_bit = max_bit - 8 + 1
|
151
|
+
else
|
152
|
+
min_bit = (byte_index * 8)
|
153
|
+
max_bit = min_bit + 7
|
154
|
+
end
|
138
155
|
|
139
156
|
# BIT INDEX ROW
|
140
157
|
line = ' '
|
158
|
+
line_complete = false
|
141
159
|
8.times do |i|
|
142
|
-
|
160
|
+
if bit_order == :lsb0
|
161
|
+
bit_num = (byte_number * 8) - i - 1
|
162
|
+
else
|
163
|
+
bit_num = (byte_index * 8) + i
|
164
|
+
end
|
143
165
|
if bit_num > size - 1
|
144
|
-
|
166
|
+
if bit_order == :msb0 && bit_num == size
|
167
|
+
line += '|'
|
168
|
+
line_complete = true
|
169
|
+
else
|
170
|
+
line << ' ' + ''.center(bit_width)
|
171
|
+
end
|
145
172
|
else
|
146
173
|
line << '|' + "#{bit_num}".center(bit_width)
|
147
174
|
end
|
148
175
|
end
|
149
|
-
line += '|'
|
176
|
+
line += '|' unless line_complete
|
150
177
|
desc << line
|
151
178
|
|
152
179
|
# BIT NAME ROW
|
153
180
|
line = ' '
|
154
181
|
first_done = false
|
182
|
+
line_complete = false
|
155
183
|
named_bits include_spacers: true do |name, bit, bitcounter|
|
156
184
|
if _bit_in_range?(bit, max_bit, min_bit)
|
157
|
-
if
|
158
|
-
|
159
|
-
|
185
|
+
if bit_order == :lsb0
|
186
|
+
if max_bit > (size - 1) && !first_done
|
187
|
+
(max_bit - (size - 1)).times do
|
188
|
+
line << ' ' * (bit_width + 1)
|
189
|
+
end
|
160
190
|
end
|
161
191
|
end
|
162
192
|
|
@@ -164,13 +194,21 @@ module Origen
|
|
164
194
|
|
165
195
|
if name
|
166
196
|
if bitcounter.nil?
|
167
|
-
|
197
|
+
if bit_order == :lsb0
|
198
|
+
bit_name = "#{name}[#{_max_bit_in_range(bit, max_bit, min_bit)}:#{_min_bit_in_range(bit, max_bit, min_bit)}]"
|
199
|
+
else
|
200
|
+
bit_name = "#{name}[#{_min_bit_in_range(bit, max_bit, min_bit)}:#{_max_bit_in_range(bit, max_bit, min_bit)}]"
|
201
|
+
end
|
168
202
|
bit_span = _num_bits_in_range(bit, max_bit, min_bit)
|
169
203
|
|
170
204
|
else
|
171
205
|
upper = _max_bit_in_range(bit, max_bit, min_bit) + bitcounter - bit.size
|
172
206
|
lower = _min_bit_in_range(bit, max_bit, min_bit) + bitcounter - bit.size
|
173
|
-
|
207
|
+
if bit_order == :lsb0
|
208
|
+
bit_name = "#{name}[#{upper}:#{lower}]"
|
209
|
+
else
|
210
|
+
bit_name = "#{name}[#{upper}:#{lower}]"
|
211
|
+
end
|
174
212
|
bit_span = upper - lower + 1
|
175
213
|
end
|
176
214
|
width = (bit_width * bit_span) + bit_span - 1
|
@@ -212,9 +250,11 @@ module Origen
|
|
212
250
|
first_done = false
|
213
251
|
named_bits include_spacers: true do |name, bit, _bitcounter|
|
214
252
|
if _bit_in_range?(bit, max_bit, min_bit)
|
215
|
-
if
|
216
|
-
|
217
|
-
|
253
|
+
if bit_order == :lsb0
|
254
|
+
if max_bit > (size - 1) && !first_done
|
255
|
+
(max_bit - (size - 1)).times do
|
256
|
+
line << ' ' * (bit_width + 1)
|
257
|
+
end
|
218
258
|
end
|
219
259
|
end
|
220
260
|
|
@@ -265,13 +305,19 @@ module Origen
|
|
265
305
|
|
266
306
|
if size >= 8
|
267
307
|
r = size % 8
|
268
|
-
if byte_index == 0 && r != 0
|
308
|
+
if byte_index == 0 && r != 0 && bit_order == :lsb0
|
269
309
|
desc << (' ' + ('=' * (bit_width + 1) * (8 - r)).chop + ' ' + ('-' * (bit_width + 1) * r)).chop
|
310
|
+
elsif (byte_index == num_bytes - 1) && r != 0 && bit_order == :msb0
|
311
|
+
desc << (' ' + ('-' * (bit_width + 1) * r)).chop
|
270
312
|
else
|
271
313
|
desc << (' ' + ('-' * (bit_width + 1) * 8)).chop
|
272
314
|
end
|
273
315
|
else
|
274
|
-
|
316
|
+
if bit_order == :lsb0
|
317
|
+
desc << (' ' + (' ' * (bit_width + 1) * (8 - size)) + ('-' * (bit_width + 1) * size)).chop
|
318
|
+
else
|
319
|
+
desc << (' ' + ('-' * (bit_width + 1) * size)).chop
|
320
|
+
end
|
275
321
|
end
|
276
322
|
end
|
277
323
|
desc.join("\n")
|
@@ -411,7 +457,6 @@ module Origen
|
|
411
457
|
|
412
458
|
# @api private
|
413
459
|
def add_bits_from_options(options = {}) # :nodoc:
|
414
|
-
# edit Traynor
|
415
460
|
# options is now an array for split bit groups or a hash if single bit/range bits
|
416
461
|
# Now add the requested bits to the register, removing the unwritable bits as required
|
417
462
|
options.each do |bit_id, bit_params|
|
@@ -490,12 +535,24 @@ module Origen
|
|
490
535
|
@lookup.each { |_k, v| split_bits = true if v.is_a? Array }
|
491
536
|
|
492
537
|
if split_bits == false
|
493
|
-
|
494
|
-
|
495
|
-
|
496
|
-
|
538
|
+
if bit_order == :lsb0
|
539
|
+
current_pos = size
|
540
|
+
else
|
541
|
+
current_pos = 0
|
542
|
+
end
|
543
|
+
# Sort by position
|
544
|
+
@lookup.sort_by { |_name, details| bit_order == :lsb0 ? -details[:pos] : details[:pos] }.each do |name, details|
|
545
|
+
if bit_order == :lsb0
|
546
|
+
pos = details[:bits] + details[:pos]
|
547
|
+
else
|
548
|
+
pos = details[:pos]
|
549
|
+
end
|
497
550
|
if options[:include_spacers] && (pos != current_pos)
|
498
|
-
|
551
|
+
if bit_order == :lsb0
|
552
|
+
collection = BitCollection.dummy(self, nil, size: current_pos - pos, pos: pos)
|
553
|
+
else
|
554
|
+
collection = BitCollection.dummy(self, nil, size: pos - current_pos, pos: current_pos)
|
555
|
+
end
|
499
556
|
unless collection.size == 0
|
500
557
|
if block_given?
|
501
558
|
yield nil, collection
|
@@ -515,10 +572,19 @@ module Origen
|
|
515
572
|
result << [name, collection]
|
516
573
|
end
|
517
574
|
end
|
518
|
-
|
575
|
+
if bit_order == :lsb0
|
576
|
+
current_pos = details[:pos]
|
577
|
+
else
|
578
|
+
current_pos = details[:bits] + details[:pos]
|
579
|
+
end
|
519
580
|
end
|
520
|
-
if options[:include_spacers] && current_pos != 0
|
521
|
-
|
581
|
+
if options[:include_spacers] && ((bit_order == :lsb0 && current_pos != 0) ||
|
582
|
+
bit_order == :msb0 && current_pos != size)
|
583
|
+
if bit_order == :lsb0
|
584
|
+
collection = BitCollection.dummy(self, nil, size: current_pos, pos: 0)
|
585
|
+
else
|
586
|
+
collection = BitCollection.dummy(self, nil, size: size - current_pos, pos: current_pos)
|
587
|
+
end
|
522
588
|
unless collection.size == 0
|
523
589
|
if block_given?
|
524
590
|
yield nil, collection
|
@@ -1159,7 +1225,7 @@ module Origen
|
|
1159
1225
|
extract_meta_data(method, *args)
|
1160
1226
|
else
|
1161
1227
|
if BitCollection.instance_methods.include?(method)
|
1162
|
-
|
1228
|
+
to_bit_collection.send(method, *args, &block)
|
1163
1229
|
elsif has_bits?(method)
|
1164
1230
|
bits(method)
|
1165
1231
|
else
|
@@ -1168,6 +1234,10 @@ module Origen
|
|
1168
1234
|
end
|
1169
1235
|
end
|
1170
1236
|
|
1237
|
+
def to_bit_collection
|
1238
|
+
BitCollection.new(self, name, @bits)
|
1239
|
+
end
|
1240
|
+
|
1171
1241
|
# Recognize that Reg responds to all BitCollection methods methods based on
|
1172
1242
|
# application-specific meta data properties
|
1173
1243
|
def respond_to?(*args) # :nodoc:
|
@@ -319,12 +319,16 @@ module Origen
|
|
319
319
|
FileUtils.rm_f(version_file) if File.exist?(version_file)
|
320
320
|
rc = RevisionControl.new remote: rc_url, local: dir
|
321
321
|
rc.checkout version: prefix_tag(tag), force: true
|
322
|
-
|
322
|
+
File.open(version_file, 'w') do |f|
|
323
|
+
f.write tag
|
324
|
+
end
|
323
325
|
else
|
324
326
|
rc = RevisionControl.new remote: rc_url, local: dir
|
325
327
|
rc.checkout version: prefix_tag(tag), force: true
|
326
|
-
|
327
|
-
|
328
|
+
FileUtils.touch "#{dir}/.initial_populate_successful"
|
329
|
+
File.open(version_file, 'w') do |f|
|
330
|
+
f.write tag
|
331
|
+
end
|
328
332
|
end
|
329
333
|
end
|
330
334
|
end
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: origen
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.
|
4
|
+
version: 0.8.0
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Stephen McGinty
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date: 2017-
|
11
|
+
date: 2017-05-23 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: activesupport
|
@@ -324,6 +324,20 @@ dependencies:
|
|
324
324
|
- - '='
|
325
325
|
- !ruby/object:Gem::Version
|
326
326
|
version: 0.12.4
|
327
|
+
- !ruby/object:Gem::Dependency
|
328
|
+
name: sinatra
|
329
|
+
requirement: !ruby/object:Gem::Requirement
|
330
|
+
requirements:
|
331
|
+
- - "~>"
|
332
|
+
- !ruby/object:Gem::Version
|
333
|
+
version: '1'
|
334
|
+
type: :runtime
|
335
|
+
prerelease: false
|
336
|
+
version_requirements: !ruby/object:Gem::Requirement
|
337
|
+
requirements:
|
338
|
+
- - "~>"
|
339
|
+
- !ruby/object:Gem::Version
|
340
|
+
version: '1'
|
327
341
|
description:
|
328
342
|
email:
|
329
343
|
- stephen.f.mcginty@gmail.com
|
@@ -568,7 +582,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
|
|
568
582
|
version: 1.8.11
|
569
583
|
requirements: []
|
570
584
|
rubyforge_project:
|
571
|
-
rubygems_version: 2.
|
585
|
+
rubygems_version: 2.5.2
|
572
586
|
signing_key:
|
573
587
|
specification_version: 4
|
574
588
|
summary: The Semiconductor Developer's Kit
|